Lines Matching +full:rxdma2host +full:- +full:destination +full:- +full:ring +full:- +full:mac3
1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
35 * 4K - 32 = 0xFE0
76 "mhi-er0",
77 "mhi-er1",
94 "host2wbm-desc-feed",
95 "host2reo-re-injection",
96 "host2reo-command",
97 "host2rxdma-monitor-ring3",
98 "host2rxdma-monitor-ring2",
99 "host2rxdma-monitor-ring1",
100 "reo2ost-exception",
101 "wbm2host-rx-release",
102 "reo2host-status",
103 "reo2host-destination-ring4",
104 "reo2host-destination-ring3",
105 "reo2host-destination-ring2",
106 "reo2host-destination-ring1",
107 "rxdma2host-monitor-destination-mac3",
108 "rxdma2host-monitor-destination-mac2",
109 "rxdma2host-monitor-destination-mac1",
110 "ppdu-end-interrupts-mac3",
111 "ppdu-end-interrupts-mac2",
112 "ppdu-end-interrupts-mac1",
113 "rxdma2host-monitor-status-ring-mac3",
114 "rxdma2host-monitor-status-ring-mac2",
115 "rxdma2host-monitor-status-ring-mac1",
116 "host2rxdma-host-buf-ring-mac3",
117 "host2rxdma-host-buf-ring-mac2",
118 "host2rxdma-host-buf-ring-mac1",
119 "rxdma2host-destination-ring-mac3",
120 "rxdma2host-destination-ring-mac2",
121 "rxdma2host-destination-ring-mac1",
122 "host2tcl-input-ring4",
123 "host2tcl-input-ring3",
124 "host2tcl-input-ring2",
125 "host2tcl-input-ring1",
126 "wbm2host-tx-completions-ring4",
127 "wbm2host-tx-completions-ring3",
128 "wbm2host-tx-completions-ring2",
129 "wbm2host-tx-completions-ring1",
130 "tcl2host-status-ring",
137 return mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev); in ath12k_pci_bus_wake_up()
144 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev); in ath12k_pci_bus_release()
159 struct ath12k_base *ab = ab_pci->ab; in ath12k_pci_select_window()
164 lockdep_assert_held(&ab_pci->window_lock); in ath12k_pci_select_window()
167 static_window = ab_pci->register_window & WINDOW_STATIC_MASK; in ath12k_pci_select_window()
170 if (window != ab_pci->register_window) { in ath12k_pci_select_window()
172 ab->mem + WINDOW_REG_ADDRESS); in ath12k_pci_select_window()
173 ioread32(ab->mem + WINDOW_REG_ADDRESS); in ath12k_pci_select_window()
174 ab_pci->register_window = window; in ath12k_pci_select_window()
186 spin_lock_bh(&ab_pci->window_lock); in ath12k_pci_select_static_window()
187 ab_pci->register_window = window; in ath12k_pci_select_static_window()
188 spin_unlock_bh(&ab_pci->window_lock); in ath12k_pci_select_static_window()
190 iowrite32(WINDOW_ENABLE_BIT | window, ab_pci->ab->mem + WINDOW_REG_ADDRESS); in ath12k_pci_select_static_window()
344 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; in ath12k_pci_free_ext_irq()
346 for (j = 0; j < irq_grp->num_irq; j++) in ath12k_pci_free_ext_irq()
347 free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp); in ath12k_pci_free_ext_irq()
349 netif_napi_del(&irq_grp->napi); in ath12k_pci_free_ext_irq()
357 for (i = 0; i < ab->hw_params->ce_count; i++) { in ath12k_pci_free_irq()
361 free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]); in ath12k_pci_free_irq()
375 if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) in ath12k_pci_ce_irq_enable()
379 enable_irq(ab->irq_num[irq_idx]); in ath12k_pci_ce_irq_enable()
390 if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) in ath12k_pci_ce_irq_disable()
394 disable_irq_nosync(ab->irq_num[irq_idx]); in ath12k_pci_ce_irq_disable()
401 clear_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags); in ath12k_pci_ce_irqs_disable()
403 for (i = 0; i < ab->hw_params->ce_count; i++) { in ath12k_pci_ce_irqs_disable()
415 for (i = 0; i < ab->hw_params->ce_count; i++) { in ath12k_pci_sync_ce_irqs()
420 synchronize_irq(ab->irq_num[irq_idx]); in ath12k_pci_sync_ce_irqs()
427 int irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_pipe->pipe_num; in ath12k_pci_ce_tasklet()
429 ath12k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num); in ath12k_pci_ce_tasklet()
431 enable_irq(ce_pipe->ab->irq_num[irq_idx]); in ath12k_pci_ce_tasklet()
437 struct ath12k_base *ab = ce_pipe->ab; in ath12k_pci_ce_interrupt_handler()
438 int irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_pipe->pipe_num; in ath12k_pci_ce_interrupt_handler()
440 if (!test_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags)) in ath12k_pci_ce_interrupt_handler()
444 ce_pipe->timestamp = jiffies; in ath12k_pci_ce_interrupt_handler()
446 disable_irq_nosync(ab->irq_num[irq_idx]); in ath12k_pci_ce_interrupt_handler()
448 tasklet_schedule(&ce_pipe->intr_tq); in ath12k_pci_ce_interrupt_handler()
455 struct ath12k_pci *ab_pci = ath12k_pci_priv(irq_grp->ab); in ath12k_pci_ext_grp_disable()
461 if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) in ath12k_pci_ext_grp_disable()
464 for (i = 0; i < irq_grp->num_irq; i++) in ath12k_pci_ext_grp_disable()
465 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]); in ath12k_pci_ext_grp_disable()
472 clear_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags); in __ath12k_pci_ext_irq_disable()
475 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; in __ath12k_pci_ext_irq_disable()
479 napi_synchronize(&irq_grp->napi); in __ath12k_pci_ext_irq_disable()
480 napi_disable(&irq_grp->napi); in __ath12k_pci_ext_irq_disable()
486 struct ath12k_pci *ab_pci = ath12k_pci_priv(irq_grp->ab); in ath12k_pci_ext_grp_enable()
492 if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) in ath12k_pci_ext_grp_enable()
495 for (i = 0; i < irq_grp->num_irq; i++) in ath12k_pci_ext_grp_enable()
496 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]); in ath12k_pci_ext_grp_enable()
504 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; in ath12k_pci_sync_ext_irqs()
506 for (j = 0; j < irq_grp->num_irq; j++) { in ath12k_pci_sync_ext_irqs()
507 irq_idx = irq_grp->irqs[j]; in ath12k_pci_sync_ext_irqs()
508 synchronize_irq(ab->irq_num[irq_idx]); in ath12k_pci_sync_ext_irqs()
518 struct ath12k_base *ab = irq_grp->ab; in ath12k_pci_ext_grp_napi_poll()
525 for (i = 0; i < irq_grp->num_irq; i++) in ath12k_pci_ext_grp_napi_poll()
526 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]); in ath12k_pci_ext_grp_napi_poll()
538 struct ath12k_base *ab = irq_grp->ab; in ath12k_pci_ext_interrupt_handler()
541 if (!test_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags)) in ath12k_pci_ext_interrupt_handler()
544 ath12k_dbg(irq_grp->ab, ATH12K_DBG_PCI, "ext irq:%d\n", irq); in ath12k_pci_ext_interrupt_handler()
547 irq_grp->timestamp = jiffies; in ath12k_pci_ext_interrupt_handler()
549 for (i = 0; i < irq_grp->num_irq; i++) in ath12k_pci_ext_interrupt_handler()
550 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]); in ath12k_pci_ext_interrupt_handler()
552 napi_schedule(&irq_grp->napi); in ath12k_pci_ext_interrupt_handler()
572 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; in ath12k_pci_ext_irq_config()
575 irq_grp->ab = ab; in ath12k_pci_ext_irq_config()
576 irq_grp->grp_id = i; in ath12k_pci_ext_irq_config()
577 init_dummy_netdev(&irq_grp->napi_ndev); in ath12k_pci_ext_irq_config()
578 netif_napi_add(&irq_grp->napi_ndev, &irq_grp->napi, in ath12k_pci_ext_irq_config()
581 if (ab->hw_params->ring_mask->tx[i] || in ath12k_pci_ext_irq_config()
582 ab->hw_params->ring_mask->rx[i] || in ath12k_pci_ext_irq_config()
583 ab->hw_params->ring_mask->rx_err[i] || in ath12k_pci_ext_irq_config()
584 ab->hw_params->ring_mask->rx_wbm_rel[i] || in ath12k_pci_ext_irq_config()
585 ab->hw_params->ring_mask->reo_status[i] || in ath12k_pci_ext_irq_config()
586 ab->hw_params->ring_mask->host2rxdma[i] || in ath12k_pci_ext_irq_config()
587 ab->hw_params->ring_mask->rx_mon_dest[i]) { in ath12k_pci_ext_irq_config()
591 irq_grp->num_irq = num_irq; in ath12k_pci_ext_irq_config()
592 irq_grp->irqs[0] = base_idx + i; in ath12k_pci_ext_irq_config()
594 for (j = 0; j < irq_grp->num_irq; j++) { in ath12k_pci_ext_irq_config()
595 int irq_idx = irq_grp->irqs[j]; in ath12k_pci_ext_irq_config()
597 int irq = ath12k_pci_get_msi_irq(ab->dev, vector); in ath12k_pci_ext_irq_config()
599 ab->irq_num[irq_idx] = irq; in ath12k_pci_ext_irq_config()
606 ab_pci->irq_flags, in ath12k_pci_ext_irq_config()
623 if (test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) in ath12k_pci_set_irq_affinity_hint()
626 return irq_set_affinity_hint(ab_pci->pdev->irq, m); in ath12k_pci_set_irq_affinity_hint()
647 for (i = 0, msi_data_idx = 0; i < ab->hw_params->ce_count; i++) { in ath12k_pci_config_irq()
652 irq = ath12k_pci_get_msi_irq(ab->dev, msi_data); in ath12k_pci_config_irq()
653 ce_pipe = &ab->ce.ce_pipe[i]; in ath12k_pci_config_irq()
657 tasklet_setup(&ce_pipe->intr_tq, ath12k_pci_ce_tasklet); in ath12k_pci_config_irq()
660 ab_pci->irq_flags, irq_name[irq_idx], in ath12k_pci_config_irq()
668 ab->irq_num[irq_idx] = irq; in ath12k_pci_config_irq()
683 struct ath12k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg; in ath12k_pci_init_qmi_ce_config()
685 cfg->tgt_ce = ab->hw_params->target_ce_config; in ath12k_pci_init_qmi_ce_config()
686 cfg->tgt_ce_len = ab->hw_params->target_ce_count; in ath12k_pci_init_qmi_ce_config()
688 cfg->svc_to_ce_map = ab->hw_params->svc_to_ce_map; in ath12k_pci_init_qmi_ce_config()
689 cfg->svc_to_ce_map_len = ab->hw_params->svc_to_ce_map_len; in ath12k_pci_init_qmi_ce_config()
690 ab->qmi.service_ins_id = ab->hw_params->qmi_service_ins_id; in ath12k_pci_init_qmi_ce_config()
697 set_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags); in ath12k_pci_ce_irqs_enable()
699 for (i = 0; i < ab->hw_params->ce_count; i++) { in ath12k_pci_ce_irqs_enable()
708 struct pci_dev *dev = ab_pci->pdev; in ath12k_pci_msi_config()
711 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); in ath12k_pci_msi_config()
718 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); in ath12k_pci_msi_config()
733 struct ath12k_base *ab = ab_pci->ab; in ath12k_pci_msi_alloc()
734 const struct ath12k_msi_config *msi_config = ab_pci->msi_config; in ath12k_pci_msi_alloc()
739 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev, in ath12k_pci_msi_alloc()
740 msi_config->total_vectors, in ath12k_pci_msi_alloc()
741 msi_config->total_vectors, in ath12k_pci_msi_alloc()
744 if (num_vectors == msi_config->total_vectors) { in ath12k_pci_msi_alloc()
745 set_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags); in ath12k_pci_msi_alloc()
746 ab_pci->irq_flags = IRQF_SHARED; in ath12k_pci_msi_alloc()
748 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev, in ath12k_pci_msi_alloc()
753 ret = -EINVAL; in ath12k_pci_msi_alloc()
756 clear_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags); in ath12k_pci_msi_alloc()
757 ab_pci->msi_config = &msi_config_one_msi; in ath12k_pci_msi_alloc()
758 ab_pci->irq_flags = IRQF_SHARED | IRQF_NOBALANCING; in ath12k_pci_msi_alloc()
766 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq); in ath12k_pci_msi_alloc()
769 ret = -EINVAL; in ath12k_pci_msi_alloc()
773 ab_pci->msi_ep_base_data = msi_desc->msg.data; in ath12k_pci_msi_alloc()
774 if (msi_desc->pci.msi_attrib.is_64) in ath12k_pci_msi_alloc()
775 set_bit(ATH12K_PCI_FLAG_IS_MSI_64, &ab_pci->flags); in ath12k_pci_msi_alloc()
777 ath12k_dbg(ab, ATH12K_DBG_PCI, "msi base data is %d\n", ab_pci->msi_ep_base_data); in ath12k_pci_msi_alloc()
782 pci_free_irq_vectors(ab_pci->pdev); in ath12k_pci_msi_alloc()
790 pci_free_irq_vectors(ab_pci->pdev); in ath12k_pci_msi_free()
797 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq); in ath12k_pci_config_msi_data()
799 ath12k_err(ab_pci->ab, "msi_desc is NULL!\n"); in ath12k_pci_config_msi_data()
800 pci_free_irq_vectors(ab_pci->pdev); in ath12k_pci_config_msi_data()
801 return -EINVAL; in ath12k_pci_config_msi_data()
804 ab_pci->msi_ep_base_data = msi_desc->msg.data; in ath12k_pci_config_msi_data()
806 ath12k_dbg(ab_pci->ab, ATH12K_DBG_PCI, "pci after request_irq msi_ep_base_data %d\n", in ath12k_pci_config_msi_data()
807 ab_pci->msi_ep_base_data); in ath12k_pci_config_msi_data()
814 struct ath12k_base *ab = ab_pci->ab; in ath12k_pci_claim()
819 if (device_id != ab_pci->dev_id) { in ath12k_pci_claim()
821 device_id, ab_pci->dev_id); in ath12k_pci_claim()
822 ret = -EIO; in ath12k_pci_claim()
844 ret = dma_set_mask_and_coherent(&pdev->dev, in ath12k_pci_claim()
854 ab->mem_len = pci_resource_len(pdev, ATH12K_PCI_BAR_NUM); in ath12k_pci_claim()
855 ab->mem = pci_iomap(pdev, ATH12K_PCI_BAR_NUM, 0); in ath12k_pci_claim()
856 if (!ab->mem) { in ath12k_pci_claim()
858 ret = -EIO; in ath12k_pci_claim()
862 ath12k_dbg(ab, ATH12K_DBG_BOOT, "boot pci_mem 0x%pK\n", ab->mem); in ath12k_pci_claim()
875 struct ath12k_base *ab = ab_pci->ab; in ath12k_pci_free_region()
876 struct pci_dev *pci_dev = ab_pci->pdev; in ath12k_pci_free_region()
878 pci_iounmap(pci_dev, ab->mem); in ath12k_pci_free_region()
879 ab->mem = NULL; in ath12k_pci_free_region()
887 struct ath12k_base *ab = ab_pci->ab; in ath12k_pci_aspm_disable()
889 pcie_capability_read_word(ab_pci->pdev, PCI_EXP_LNKCTL, in ath12k_pci_aspm_disable()
890 &ab_pci->link_ctl); in ath12k_pci_aspm_disable()
893 ab_pci->link_ctl, in ath12k_pci_aspm_disable()
894 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L0S), in ath12k_pci_aspm_disable()
895 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L1)); in ath12k_pci_aspm_disable()
898 pcie_capability_clear_word(ab_pci->pdev, PCI_EXP_LNKCTL, in ath12k_pci_aspm_disable()
901 set_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags); in ath12k_pci_aspm_disable()
906 if (test_and_clear_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags)) in ath12k_pci_aspm_restore()
907 pcie_capability_clear_and_set_word(ab_pci->pdev, PCI_EXP_LNKCTL, in ath12k_pci_aspm_restore()
909 ab_pci->link_ctl & in ath12k_pci_aspm_restore()
917 for (i = 0; i < ab->hw_params->ce_count; i++) { in ath12k_pci_kill_tasklets()
918 struct ath12k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i]; in ath12k_pci_kill_tasklets()
923 tasklet_kill(&ce_pipe->intr_tq); in ath12k_pci_kill_tasklets()
941 for (i = 0; i < ab->hw_params->svc_to_ce_map_len; i++) { in ath12k_pci_map_service_to_pipe()
942 entry = &ab->hw_params->svc_to_ce_map[i]; in ath12k_pci_map_service_to_pipe()
944 if (__le32_to_cpu(entry->service_id) != service_id) in ath12k_pci_map_service_to_pipe()
947 switch (__le32_to_cpu(entry->pipedir)) { in ath12k_pci_map_service_to_pipe()
952 *dl_pipe = __le32_to_cpu(entry->pipenum); in ath12k_pci_map_service_to_pipe()
957 *ul_pipe = __le32_to_cpu(entry->pipenum); in ath12k_pci_map_service_to_pipe()
963 *dl_pipe = __le32_to_cpu(entry->pipenum); in ath12k_pci_map_service_to_pipe()
964 *ul_pipe = __le32_to_cpu(entry->pipenum); in ath12k_pci_map_service_to_pipe()
972 return -ENOENT; in ath12k_pci_map_service_to_pipe()
989 const struct ath12k_msi_config *msi_config = ab_pci->msi_config; in ath12k_pci_get_user_msi_assignment()
992 for (idx = 0; idx < msi_config->total_users; idx++) { in ath12k_pci_get_user_msi_assignment()
993 if (strcmp(user_name, msi_config->users[idx].name) == 0) { in ath12k_pci_get_user_msi_assignment()
994 *num_vectors = msi_config->users[idx].num_vectors; in ath12k_pci_get_user_msi_assignment()
995 *base_vector = msi_config->users[idx].base_vector; in ath12k_pci_get_user_msi_assignment()
996 *user_base_data = *base_vector + ab_pci->msi_ep_base_data; in ath12k_pci_get_user_msi_assignment()
1009 return -EINVAL; in ath12k_pci_get_user_msi_assignment()
1016 struct pci_dev *pci_dev = to_pci_dev(ab->dev); in ath12k_pci_get_msi_address()
1018 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO, in ath12k_pci_get_msi_address()
1021 if (test_bit(ATH12K_PCI_FLAG_IS_MSI_64, &ab_pci->flags)) { in ath12k_pci_get_msi_address()
1022 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI, in ath12k_pci_get_msi_address()
1034 for (i = 0, msi_data_idx = 0; i < ab->hw_params->ce_count; i++) { in ath12k_pci_get_ce_msi_idx()
1060 set_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags); in ath12k_pci_ext_irq_enable()
1063 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; in ath12k_pci_ext_irq_enable()
1065 napi_enable(&irq_grp->napi); in ath12k_pci_ext_irq_enable()
1104 set_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags); in ath12k_pci_start()
1106 if (test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) in ath12k_pci_start()
1123 /* for offset beyond BAR + 4K - 32, may in ath12k_pci_read32()
1126 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && in ath12k_pci_read32()
1127 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->wakeup) in ath12k_pci_read32()
1128 ret = ab_pci->pci_ops->wakeup(ab); in ath12k_pci_read32()
1131 val = ioread32(ab->mem + offset); in ath12k_pci_read32()
1133 if (ab->static_window_map) in ath12k_pci_read32()
1139 spin_lock_bh(&ab_pci->window_lock); in ath12k_pci_read32()
1141 val = ioread32(ab->mem + window_start + in ath12k_pci_read32()
1143 spin_unlock_bh(&ab_pci->window_lock); in ath12k_pci_read32()
1148 offset = offset - PCI_MHIREGLEN_REG; in ath12k_pci_read32()
1150 val = ioread32(ab->mem + window_start + in ath12k_pci_read32()
1155 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && in ath12k_pci_read32()
1156 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->release && in ath12k_pci_read32()
1158 ab_pci->pci_ops->release(ab); in ath12k_pci_read32()
1168 /* for offset beyond BAR + 4K - 32, may in ath12k_pci_write32()
1171 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && in ath12k_pci_write32()
1172 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->wakeup) in ath12k_pci_write32()
1173 ret = ab_pci->pci_ops->wakeup(ab); in ath12k_pci_write32()
1176 iowrite32(value, ab->mem + offset); in ath12k_pci_write32()
1178 if (ab->static_window_map) in ath12k_pci_write32()
1184 spin_lock_bh(&ab_pci->window_lock); in ath12k_pci_write32()
1186 iowrite32(value, ab->mem + window_start + in ath12k_pci_write32()
1188 spin_unlock_bh(&ab_pci->window_lock); in ath12k_pci_write32()
1193 offset = offset - PCI_MHIREGLEN_REG; in ath12k_pci_write32()
1195 iowrite32(value, ab->mem + window_start + in ath12k_pci_write32()
1200 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && in ath12k_pci_write32()
1201 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->release && in ath12k_pci_write32()
1203 ab_pci->pci_ops->release(ab); in ath12k_pci_write32()
1211 ab_pci->register_window = 0; in ath12k_pci_power_up()
1212 clear_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags); in ath12k_pci_power_up()
1213 ath12k_pci_sw_reset(ab_pci->ab, true); in ath12k_pci_power_up()
1228 if (ab->static_window_map) in ath12k_pci_power_up()
1241 ath12k_pci_force_wake(ab_pci->ab); in ath12k_pci_power_down()
1244 clear_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags); in ath12k_pci_power_down()
1245 ath12k_pci_sw_reset(ab_pci->ab, false); in ath12k_pci_power_down()
1291 ab = ath12k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH12K_BUS_PCI); in ath12k_pci_probe()
1293 dev_err(&pdev->dev, "failed to allocate ath12k base\n"); in ath12k_pci_probe()
1294 return -ENOMEM; in ath12k_pci_probe()
1297 ab->dev = &pdev->dev; in ath12k_pci_probe()
1300 ab_pci->dev_id = pci_dev->device; in ath12k_pci_probe()
1301 ab_pci->ab = ab; in ath12k_pci_probe()
1302 ab_pci->pdev = pdev; in ath12k_pci_probe()
1303 ab->hif.ops = &ath12k_pci_hif_ops; in ath12k_pci_probe()
1305 spin_lock_init(&ab_pci->window_lock); in ath12k_pci_probe()
1313 switch (pci_dev->device) { in ath12k_pci_probe()
1315 ab_pci->msi_config = &ath12k_msi_config[0]; in ath12k_pci_probe()
1316 ab->static_window_map = true; in ath12k_pci_probe()
1317 ab_pci->pci_ops = &ath12k_pci_ops_qcn9274; in ath12k_pci_probe()
1322 ab->hw_rev = ATH12K_HW_QCN9274_HW20; in ath12k_pci_probe()
1325 ab->hw_rev = ATH12K_HW_QCN9274_HW10; in ath12k_pci_probe()
1328 dev_err(&pdev->dev, in ath12k_pci_probe()
1331 ret = -EOPNOTSUPP; in ath12k_pci_probe()
1336 ab_pci->msi_config = &ath12k_msi_config[0]; in ath12k_pci_probe()
1337 ab->static_window_map = false; in ath12k_pci_probe()
1338 ab_pci->pci_ops = &ath12k_pci_ops_wcn7850; in ath12k_pci_probe()
1343 ab->hw_rev = ATH12K_HW_WCN7850_HW20; in ath12k_pci_probe()
1346 dev_err(&pdev->dev, in ath12k_pci_probe()
1349 ret = -EOPNOTSUPP; in ath12k_pci_probe()
1355 dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n", in ath12k_pci_probe()
1356 pci_dev->device); in ath12k_pci_probe()
1357 ret = -EOPNOTSUPP; in ath12k_pci_probe()
1453 if (test_bit(ATH12K_FLAG_QMI_FAIL, &ab->dev_flags)) { in ath12k_pci_remove()
1459 set_bit(ATH12K_FLAG_UNREGISTERING, &ab->dev_flags); in ath12k_pci_remove()
1461 cancel_work_sync(&ab->reset_work); in ath12k_pci_remove()