Lines Matching full:u32
42 u32 cmd_id;
46 u32 header;
2217 u32 pdev_id;
2218 u32 start_freq;
2219 u32 end_freq;
2223 u32 numss_m1;
2224 u32 ru_bit_mask;
2225 u32 ppet16_ppet8_ru3_ru0[PSOC_HOST_MAX_NUM_SS];
2229 u32 default_conc_scan_config_bits;
2230 u32 default_fw_config_bits;
2232 u32 he_cap_info;
2233 u32 mpdu_density;
2234 u32 max_bssid_rx_filters;
2235 u32 num_hw_modes;
2236 u32 num_phy;
2240 u32 hw_mode_id;
2241 u32 phy_id_map;
2242 u32 hw_mode_config_type;
2254 u32 phy_id;
2255 u32 eeprom_reg_domain;
2256 u32 eeprom_reg_domain_ext;
2257 u32 regcap1;
2258 u32 regcap2;
2259 u32 wireless_modes;
2260 u32 low_2ghz_chan;
2261 u32 high_2ghz_chan;
2262 u32 low_5ghz_chan;
2263 u32 high_5ghz_chan;
2269 u32 tlv_header;
2270 u32 req_id;
2271 u32 ptr;
2272 u32 size;
2278 u32 len;
2279 u32 req_id;
2283 u32 tlv_header;
2287 u32 hw_mode_id;
2288 u32 num_band_to_mac;
2293 u32 tlv_header;
2294 u32 pdev_id;
2295 u32 start_freq;
2296 u32 end_freq;
2300 u32 tlv_header;
2301 u32 pdev_id;
2302 u32 hw_mode_index;
2303 u32 num_band_to_mac;
2307 u32 numss_m1; /** NSS - 1*/
2309 u32 ru_count;
2310 u32 ru_mask;
2312 u32 ppet16_ppet8_ru3_ru0[WMI_MAX_NUM_SS];
2318 u32 abi_version_0;
2319 u32 abi_version_1;
2320 u32 abi_version_ns_0;
2321 u32 abi_version_ns_1;
2322 u32 abi_version_ns_2;
2323 u32 abi_version_ns_3;
2327 u32 tlv_header;
2329 u32 num_host_mem_chunks;
2339 u32 tlv_header;
2340 u32 num_vdevs;
2341 u32 num_peers;
2342 u32 num_offload_peers;
2343 u32 num_offload_reorder_buffs;
2344 u32 num_peer_keys;
2345 u32 num_tids;
2346 u32 ast_skid_limit;
2347 u32 tx_chain_mask;
2348 u32 rx_chain_mask;
2349 u32 rx_timeout_pri[4];
2350 u32 rx_decap_mode;
2351 u32 scan_max_pending_req;
2352 u32 bmiss_offload_max_vdev;
2353 u32 roam_offload_max_vdev;
2354 u32 roam_offload_max_ap_profiles;
2355 u32 num_mcast_groups;
2356 u32 num_mcast_table_elems;
2357 u32 mcast2ucast_mode;
2358 u32 tx_dbg_log_size;
2359 u32 num_wds_entries;
2360 u32 dma_burst_size;
2361 u32 mac_aggr_delim;
2362 u32 rx_skip_defrag_timeout_dup_detection_check;
2363 u32 vow_config;
2364 u32 gtk_offload_max_vdev;
2365 u32 num_msdu_desc;
2366 u32 max_frag_entries;
2367 u32 num_tdls_vdevs;
2368 u32 num_tdls_conn_table_entries;
2369 u32 beacon_tx_offload_max_vdev;
2370 u32 num_multicast_filter_entries;
2371 u32 num_wow_filters;
2372 u32 num_keep_alive_pattern;
2373 u32 keep_alive_pattern_size;
2374 u32 max_tdls_concurrent_sleep_sta;
2375 u32 max_tdls_concurrent_buffer_sta;
2376 u32 wmi_send_separate;
2377 u32 num_ocb_vdevs;
2378 u32 num_ocb_channels;
2379 u32 num_ocb_schedules;
2380 u32 flag1;
2381 u32 smart_ant_cap;
2382 u32 bk_minfree;
2383 u32 be_minfree;
2384 u32 vi_minfree;
2385 u32 vo_minfree;
2386 u32 alloc_frag_desc_for_data_pkt;
2387 u32 num_ns_ext_tuples_cfg;
2388 u32 bpf_instruction_size;
2389 u32 max_bssid_rx_filters;
2390 u32 use_pdev_id;
2391 u32 max_num_dbs_scan_duty_cycle;
2392 u32 max_num_group_keys;
2393 u32 peer_map_unmap_v2_support;
2394 u32 sched_params;
2395 u32 twt_ap_pdev_count;
2396 u32 twt_ap_sta_count;
2397 u32 max_nlo_ssids;
2398 u32 num_pkt_filters;
2399 u32 num_max_sta_vdevs;
2400 u32 max_bssid_indicator;
2401 u32 ul_resp_config;
2402 u32 msdu_flow_override_config0;
2403 u32 msdu_flow_override_config1;
2404 u32 flags2;
2405 u32 host_service_flags;
2406 u32 max_rnr_neighbours;
2407 u32 ema_max_vap_cnt;
2408 u32 ema_max_profile_period;
2412 u32 fw_build_vers;
2414 u32 phy_capability;
2415 u32 max_frag_entry;
2416 u32 num_rf_chains;
2417 u32 ht_cap_info;
2418 u32 vht_cap_info;
2419 u32 vht_supp_mcs;
2420 u32 hw_min_tx_power;
2421 u32 hw_max_tx_power;
2422 u32 sys_cap_info;
2423 u32 min_pkt_size_enable;
2424 u32 max_bcn_ie_size;
2425 u32 num_mem_reqs;
2426 u32 max_num_scan_channels;
2427 u32 hw_bd_id;
2428 u32 hw_bd_info[HW_BD_INFO_SIZE];
2429 u32 max_supported_macs;
2430 u32 wmi_fw_sub_feat_caps;
2431 u32 num_dbs_hw_modes;
2438 u32 txrx_chainmask;
2439 u32 default_dbs_hw_mode_index;
2440 u32 num_msdu_desc;
2443 #define WMI_SERVICE_BM_SIZE ((WMI_MAX_SERVICE + sizeof(u32) - 1) / sizeof(u32))
2445 #define WMI_SERVICE_SEGMENT_BM_SIZE32 4 /* 4x u32 = 128 bits */
2446 #define WMI_SERVICE_EXT_BM_SIZE (WMI_SERVICE_SEGMENT_BM_SIZE32 * sizeof(u32))
2451 u32 default_conc_scan_config_bits;
2452 u32 default_fw_config_bits;
2454 u32 he_cap_info;
2455 u32 mpdu_density;
2456 u32 max_bssid_rx_filters;
2457 u32 fw_build_vers_ext;
2458 u32 max_nlo_ssids;
2459 u32 max_bssid_indicator;
2460 u32 he_cap_info_ext;
2464 u32 num_hw_modes;
2465 u32 num_chainmask_tables;
2469 u32 tlv_header;
2470 u32 hw_mode_id;
2471 u32 phy_id_map;
2472 u32 hw_mode_config_type;
2484 u32 hw_mode_id;
2485 u32 pdev_id;
2486 u32 phy_id;
2487 u32 supported_flags;
2488 u32 supported_bands;
2489 u32 ampdu_density;
2490 u32 max_bw_supported_2g;
2491 u32 ht_cap_info_2g;
2492 u32 vht_cap_info_2g;
2493 u32 vht_supp_mcs_2g;
2494 u32 he_cap_info_2g;
2495 u32 he_supp_mcs_2g;
2496 u32 tx_chain_mask_2g;
2497 u32 rx_chain_mask_2g;
2498 u32 max_bw_supported_5g;
2499 u32 ht_cap_info_5g;
2500 u32 vht_cap_info_5g;
2501 u32 vht_supp_mcs_5g;
2502 u32 he_cap_info_5g;
2503 u32 he_supp_mcs_5g;
2504 u32 tx_chain_mask_5g;
2505 u32 rx_chain_mask_5g;
2506 u32 he_cap_phy_info_2g[WMI_MAX_HECAP_PHY_SIZE];
2507 u32 he_cap_phy_info_5g[WMI_MAX_HECAP_PHY_SIZE];
2510 u32 chainmask_table_id;
2511 u32 lmac_id;
2512 u32 he_cap_info_2g_ext;
2513 u32 he_cap_info_5g_ext;
2514 u32 he_cap_info_internal;
2515 u32 wireless_modes;
2516 u32 low_2ghz_chan_freq;
2517 u32 high_2ghz_chan_freq;
2518 u32 low_5ghz_chan_freq;
2519 u32 high_5ghz_chan_freq;
2520 u32 nss_ratio;
2524 u32 tlv_header;
2525 u32 phy_id;
2526 u32 eeprom_reg_domain;
2527 u32 eeprom_reg_domain_ext;
2528 u32 regcap1;
2529 u32 regcap2;
2530 u32 wireless_modes;
2531 u32 low_2ghz_chan;
2532 u32 high_2ghz_chan;
2533 u32 low_5ghz_chan;
2534 u32 high_5ghz_chan;
2538 u32 num_phy;
2546 u32 word0;
2547 u32 word1;
2553 u32 tlv_header;
2554 u32 pdev_id;
2555 u32 module_id;
2556 u32 min_elem;
2557 u32 min_buf_sz;
2558 u32 min_buf_align;
2564 u32 status;
2565 u32 num_dscp_table;
2566 u32 num_extra_mac_addr;
2567 u32 num_total_peers;
2568 u32 num_extra_peers;
2573 u32 max_ast_index;
2574 u32 pktlog_defs_checksum;
2578 u32 wmi_service_segment_offset;
2579 u32 wmi_service_segment_bitmap[WMI_SERVICE_SEGMENT_BM_SIZE32];
2585 u32 rx_decap_mode;
2591 u32 type;
2592 u32 subtype;
2597 u32 pdev_id;
2598 u32 mbssid_flags;
2599 u32 mbssid_tx_vdev_id;
2603 u32 tlv_header;
2604 u32 vdev_id;
2605 u32 vdev_type;
2606 u32 vdev_subtype;
2608 u32 num_cfg_txrx_streams;
2609 u32 pdev_id;
2610 u32 mbssid_flags;
2611 u32 mbssid_tx_vdev_id;
2615 u32 tlv_header;
2616 u32 band;
2617 u32 supported_tx_streams;
2618 u32 supported_rx_streams;
2622 u32 tlv_header;
2623 u32 vdev_id;
2627 u32 tlv_header;
2628 u32 vdev_id;
2629 u32 vdev_assoc_id;
2632 u32 nontx_profile_idx;
2633 u32 nontx_profile_cnt;
2637 u32 tlv_header;
2638 u32 vdev_id;
2642 u32 tlv_header;
2643 u32 vdev_id;
2652 u32 ssid_len;
2653 u32 ssid[8];
2659 u32 tlv_header;
2660 u32 vdev_id;
2661 u32 requestor_id;
2662 u32 beacon_interval;
2663 u32 dtim_period;
2664 u32 flags;
2666 u32 bcn_tx_rate;
2667 u32 bcn_txpower;
2668 u32 num_noa_descriptors;
2669 u32 disable_hw_ack;
2670 u32 preferred_tx_streams;
2671 u32 preferred_rx_streams;
2672 u32 he_ops;
2673 u32 cac_duration_ms;
2674 u32 regdomain;
2675 u32 min_data_rate;
2676 u32 mbssid_flags;
2677 u32 mbssid_tx_vdev_id;
2688 u32 type_count;
2689 u32 duration;
2690 u32 interval;
2691 u32 start_time;
2697 u32 mhz;
2698 u32 half_rate:1,
2708 u32 phy_mode;
2709 u32 cfreq1;
2710 u32 cfreq2;
2811 u32 freq;
2812 u32 band_center_freq1;
2813 u32 band_center_freq2;
2822 u32 min_power;
2823 u32 max_power;
2824 u32 max_reg_power;
2825 u32 max_antenna_gain;
2830 u32 vdev_id;
2832 u32 bcn_intval;
2833 u32 dtim_period;
2835 u32 ssid_len;
2836 u32 bcn_tx_rate;
2837 u32 bcn_tx_power;
2841 u32 he_ops;
2842 u32 cac_duration_ms;
2843 u32 regdomain;
2844 u32 pref_rx_streams;
2845 u32 pref_tx_streams;
2846 u32 num_noa_descriptors;
2847 u32 min_data_rate;
2848 u32 mbssid_flags;
2849 u32 mbssid_tx_vdev_id;
2854 u32 peer_type;
2855 u32 vdev_id;
2863 u32 peer_tid_bitmap;
2871 u32 ctl_2g;
2872 u32 ctl_5g;
2874 u32 pdev_id;
2880 u32 peer_tid_bitmap;
2969 u32 param_id;
2970 u32 param_value;
2980 u32 tlv_header;
2981 u32 vdev_id;
2983 u32 peer_type;
2987 u32 tlv_header;
2988 u32 vdev_id;
2993 u32 tlv_header;
2994 u32 vdev_id;
2996 u32 tid;
2997 u32 queue_ptr_lo;
2998 u32 queue_ptr_hi;
2999 u32 queue_no;
3000 u32 ba_window_size_valid;
3001 u32 ba_window_size;
3005 u32 tlv_header;
3006 u32 vdev_id;
3008 u32 tid_mask;
3012 u32 gpio_num;
3013 u32 input;
3014 u32 pull_type;
3015 u32 intr_mode;
3039 u32 tlv_header;
3040 u32 gpio_num;
3041 u32 input;
3042 u32 pull_type;
3043 u32 intr_mode;
3047 u32 gpio_num;
3048 u32 set;
3052 u32 tlv_header;
3053 u32 gpio_num;
3054 u32 set;
3058 u32 arg;
3059 u32 value;
3063 u32 tlv_header;
3064 u32 param_id;
3065 u32 param_value;
3069 u32 tlv_header;
3070 u32 pdev_id;
3071 u32 param_id;
3072 u32 param_value;
3076 u32 tlv_header;
3077 u32 vdev_id;
3078 u32 sta_ps_mode;
3082 u32 tlv_header;
3083 u32 pdev_id;
3084 u32 suspend_opt;
3088 u32 tlv_header;
3089 u32 pdev_id;
3093 u32 tlv_header;
3095 u32 req_type;
3096 u32 pdev_id;
3100 u32 tlv_header;
3101 u32 vdev_id;
3103 u32 param;
3104 u32 value;
3108 u32 tlv_header;
3109 u32 vdev_id;
3110 u32 param;
3111 u32 value;
3115 u32 tlv_header;
3116 u32 pdev_id;
3117 u32 reg_domain;
3118 u32 reg_domain_2g;
3119 u32 reg_domain_5g;
3120 u32 conformance_test_limit_2g;
3121 u32 conformance_test_limit_5g;
3122 u32 dfs_domain;
3126 u32 tlv_header;
3127 u32 vdev_id;
3129 u32 param_id;
3130 u32 param_value;
3134 u32 tlv_header;
3135 u32 vdev_id;
3137 u32 peer_tid_bitmap;
3141 u32 tlv_header;
3142 u32 pdev_id;
3146 u32 tlv_header;
3147 u32 vdev_id;
3148 u32 bcn_ctrl_op;
3162 u32 len;
3221 u32 tlv_header;
3222 u32 scan_id;
3223 u32 scan_req_id;
3224 u32 vdev_id;
3225 u32 scan_priority;
3226 u32 notify_scan_events;
3227 u32 dwell_time_active;
3228 u32 dwell_time_passive;
3229 u32 min_rest_time;
3230 u32 max_rest_time;
3231 u32 repeat_probe_time;
3232 u32 probe_spacing_time;
3233 u32 idle_time;
3234 u32 max_scan_time;
3235 u32 probe_delay;
3236 u32 scan_ctrl_flags;
3237 u32 burst_duration;
3238 u32 num_chan;
3239 u32 num_bssid;
3240 u32 num_ssids;
3241 u32 ie_len;
3242 u32 n_probes;
3245 u32 ie_bitmap[WMI_IE_BITMAP_SIZE];
3246 u32 num_vendor_oui;
3247 u32 scan_ctrl_flags_ext;
3248 u32 dwell_time_active_2g;
3249 u32 dwell_time_active_6g;
3250 u32 dwell_time_passive_6g;
3251 u32 scan_start_offset;
3296 u32 freq_flags;
3297 u32 short_ssid;
3301 u32 freq_flags;
3306 u32 scan_id;
3307 u32 scan_req_id;
3308 u32 vdev_id;
3309 u32 pdev_id;
3313 u32 scan_ev_started:1,
3327 u32 scan_events;
3329 u32 scan_ctrl_flags_ext;
3330 u32 dwell_time_active;
3331 u32 dwell_time_active_2g;
3332 u32 dwell_time_passive;
3333 u32 dwell_time_active_6g;
3334 u32 dwell_time_passive_6g;
3335 u32 min_rest_time;
3336 u32 max_rest_time;
3337 u32 repeat_probe_time;
3338 u32 probe_spacing_time;
3339 u32 idle_time;
3340 u32 max_scan_time;
3341 u32 probe_delay;
3344 u32 scan_f_passive:1,
3370 u32 scan_flags;
3373 u32 burst_duration;
3374 u32 num_chan;
3375 u32 num_bssid;
3376 u32 num_ssids;
3377 u32 n_probes;
3378 u32 *chan_list;
3379 u32 notify_scan_events;
3385 u32 num_hint_s_ssid;
3386 u32 num_hint_bssid;
3403 u32 scan_id;
3404 u32 scan_req_id;
3405 u32 vdev_id;
3406 u32 scan_priority;
3407 u32 notify_scan_events;
3408 u32 dwell_time_active;
3409 u32 dwell_time_passive;
3410 u32 min_rest_time;
3411 u32 max_rest_time;
3412 u32 repeat_probe_time;
3413 u32 probe_spacing_time;
3414 u32 idle_time;
3415 u32 max_scan_time;
3416 u32 probe_delay;
3417 u32 scan_ctrl_flags;
3419 u32 ie_len;
3420 u32 n_channels;
3421 u32 n_ssids;
3422 u32 n_bssids;
3425 u32 channels[64];
3446 u32 requester;
3447 u32 scan_id;
3449 u32 vdev_id;
3450 u32 pdev_id;
3454 u32 tlv_header;
3455 u32 vdev_id;
3456 u32 data_len;
3458 u32 frag_ptr;
3459 u32 frag_ptr_lo;
3461 u32 frame_ctrl;
3462 u32 dtim_flag;
3463 u32 bcn_antenna;
3464 u32 frag_ptr_hi;
3491 u32 tlv_header;
3492 u32 mhz;
3493 u32 band_center_freq1;
3494 u32 band_center_freq2;
3495 u32 info;
3496 u32 reg_info_1;
3497 u32 reg_info_2;
3527 u32 tlv_header;
3528 u32 type;
3529 u32 delay_time_ms;
3533 u32 tlv_header;
3534 u32 vdev_id;
3535 u32 param_id;
3536 u32 param_value;
3557 u32 tlv_header;
3559 u32 vdev_id;
3561 u32 pdev_id;
3565 u32 tlv_header;
3566 u32 param;
3567 u32 pdev_id;
3571 u32 len;
3572 u32 msgref;
3573 u32 segmentinfo;
3574 u32 pdev_id;
3578 u32 tlv_header;
3595 u32 tlv_header;
3596 u32 vdev_id;
3597 u32 tim_ie_offset;
3598 u32 buf_len;
3599 u32 csa_switch_count_offset;
3600 u32 ext_csa_switch_count_offset;
3601 u32 csa_event_bitmap;
3602 u32 mbssid_ie_offset;
3603 u32 esp_ie_offset;
3604 u32 csc_switch_count_offset;
3605 u32 csc_event_bitmap;
3606 u32 mu_edca_ie_offset;
3607 u32 feature_enable_bitmap;
3608 u32 ema_params;
3612 u32 key_seq_counter_l;
3613 u32 key_seq_counter_h;
3617 u32 tlv_header;
3618 u32 vdev_id;
3620 u32 key_idx;
3621 u32 key_flags;
3622 u32 key_cipher;
3628 u32 key_len;
3629 u32 key_txmic_len;
3630 u32 key_rxmic_len;
3631 u32 is_group_key_id_valid;
3632 u32 group_key_id;
3640 u32 vdev_id;
3642 u32 key_idx;
3643 u32 key_flags;
3644 u32 key_cipher;
3645 u32 key_len;
3646 u32 key_txmic_len;
3647 u32 key_rxmic_len;
3660 u32 num_rates;
3666 u32 vdev_id;
3667 u32 peer_new_assoc;
3668 u32 peer_associd;
3669 u32 peer_flags;
3670 u32 peer_caps;
3671 u32 peer_listen_intval;
3672 u32 peer_ht_caps;
3673 u32 peer_max_mpdu;
3674 u32 peer_mpdu_density;
3675 u32 peer_rate_caps;
3676 u32 peer_nss;
3677 u32 peer_vht_caps;
3678 u32 peer_phymode;
3679 u32 peer_ht_info[2];
3682 u32 rx_max_rate;
3683 u32 rx_mcs_set;
3684 u32 tx_max_rate;
3685 u32 tx_mcs_set;
3688 u32 tx_max_mcs_nss;
3689 u32 peer_bw_rxnss_override;
3714 u32 peer_he_cap_macinfo[2];
3715 u32 peer_he_cap_macinfo_internal;
3716 u32 peer_he_caps_6ghz;
3717 u32 peer_he_ops;
3718 u32 peer_he_cap_phyinfo[WMI_HOST_MAX_HECAP_PHY_SIZE];
3719 u32 peer_he_mcs_count;
3720 u32 peer_he_rx_mcs_set[WMI_HOST_MAX_HE_RATE_SET];
3721 u32 peer_he_tx_mcs_set[WMI_HOST_MAX_HE_RATE_SET];
3729 u32 tlv_header;
3731 u32 vdev_id;
3732 u32 peer_new_assoc;
3733 u32 peer_associd;
3734 u32 peer_flags;
3735 u32 peer_caps;
3736 u32 peer_listen_intval;
3737 u32 peer_ht_caps;
3738 u32 peer_max_mpdu;
3739 u32 peer_mpdu_density;
3740 u32 peer_rate_caps;
3741 u32 peer_nss;
3742 u32 peer_vht_caps;
3743 u32 peer_phymode;
3744 u32 peer_ht_info[2];
3745 u32 num_peer_legacy_rates;
3746 u32 num_peer_ht_rates;
3747 u32 peer_bw_rxnss_override;
3749 u32 peer_he_cap_info;
3750 u32 peer_he_ops;
3751 u32 peer_he_cap_phy[WMI_MAX_HECAP_PHY_SIZE];
3752 u32 peer_he_mcs;
3753 u32 peer_he_cap_info_ext;
3754 u32 peer_he_cap_info_internal;
3755 u32 min_data_rate;
3756 u32 peer_he_caps_6ghz;
3760 u32 tlv_header;
3761 u32 requestor;
3762 u32 scan_id;
3763 u32 req_type;
3764 u32 vdev_id;
3765 u32 pdev_id;
3769 u32 pdev_id;
3775 u32 tlv_header;
3776 u32 num_scan_chans;
3777 u32 flags;
3778 u32 pdev_id;
3782 u32 tlv_header;
3783 u32 prob_req_oui;
3800 u32 tlv_header;
3801 u32 tx_params_dword0;
3802 u32 tx_params_dword1;
3806 u32 tlv_header;
3807 u32 vdev_id;
3808 u32 desc_id;
3809 u32 chanfreq;
3810 u32 paddr_lo;
3811 u32 paddr_hi;
3812 u32 frame_len;
3813 u32 buf_len;
3814 u32 tx_params_valid;
3822 u32 tlv_header;
3823 u32 vdev_id;
3824 u32 sta_ps_mode;
3828 u32 tlv_header;
3829 u32 vdev_id;
3830 u32 forced_mode;
3834 u32 tlv_header;
3835 u32 vdev_id;
3836 u32 param;
3837 u32 value;
3841 u32 tlv_header;
3842 u32 caps;
3843 u32 erp;
3852 u32 value;
3856 u32 tlv_header;
3857 u32 pdev_id;
3858 u32 enable;
3862 u32 vdev_id;
3863 u32 param;
3864 u32 value;
3868 u32 if_id;
3869 u32 param_id;
3870 u32 param_value;
3874 u32 stats_id;
3875 u32 vdev_id;
3876 u32 pdev_id;
3884 u32 tlv_header;
3885 u32 pdev_id;
3886 u32 new_alpha2;
3912 u32 tlv_header;
3913 u32 pdev_id;
3914 u32 init_cc_type;
3916 u32 country_code;
3917 u32 regdom_id;
3918 u32 alpha2;
3923 u32 vdev_id;
3924 u32 scan_period_msec;
3925 u32 start_interval_msec;
3929 u32 tlv_header;
3930 u32 vdev_id;
3931 u32 scan_period_msec;
3932 u32 start_interval_msec;
3936 u32 tlv_header;
3937 u32 vdev_id;
3941 u32 new_alpha2;
3946 u32 tmplwm;
3947 u32 tmphwm;
3948 u32 dcoffpercent;
3949 u32 priority;
3953 u32 pdev_id;
3954 u32 enable;
3955 u32 dc;
3956 u32 dc_per_event;
3961 u32 tlv_header;
3962 u32 pdev_id;
3963 u32 enable;
3964 u32 dc;
3965 u32 dc_per_event;
3966 u32 therm_throt_levels;
3970 u32 tlv_header;
3971 u32 temp_lwm;
3972 u32 temp_hwm;
3973 u32 dc_off_percent;
3974 u32 prio;
3978 u32 tlv_header;
3979 u32 vdev_id;
3981 u32 tid;
3982 u32 initiator;
3983 u32 reasoncode;
3987 u32 tlv_header;
3988 u32 vdev_id;
3990 u32 tid;
3991 u32 statuscode;
3995 u32 tlv_header;
3996 u32 vdev_id;
3998 u32 tid;
3999 u32 buffersize;
4003 u32 tlv_header;
4004 u32 vdev_id;
4009 u32 tlv_header;
4014 u32 tlv_header;
4015 u32 pdev_id;
4016 u32 enable;
4017 u32 filter_type;
4018 u32 num_mac;
4027 u32 tlv_header;
4028 u32 pdev_id;
4029 u32 evlist; /* WMI_PKTLOG_EVENT */
4030 u32 enable;
4034 u32 tlv_header;
4035 u32 pdev_id;
4050 u32 cmd_id;
4051 u32 pdev_id;
4052 u32 radar_param;
4056 u32 tlv_header;
4057 u32 vdev_id;
4058 u32 module_id;
4059 u32 num_args;
4060 u32 diag_token;
4068 u32 tim_ie_offset;
4069 u32 tmpl_len;
4070 u32 tmpl_len_aligned;
4071 u32 csa_switch_count_offset;
4072 u32 ext_csa_switch_count_offset;
4077 u32 num_rates;
4078 u32 rates[(MAX_SUPPORTED_RATES / 4) + 1];
4082 u32 tlv_header;
4083 u32 rx_max_rate;
4084 u32 rx_mcs_set;
4085 u32 tx_max_rate;
4086 u32 tx_mcs_set;
4087 u32 tx_max_mcs_nss;
4091 u32 tlv_header;
4094 u32 rx_mcs_set;
4097 u32 tx_mcs_set;
4110 u32 vdev_id;
4111 u32 requestor_id;
4113 u32 status;
4114 u32 chain_mask;
4115 u32 smps_mode;
4117 u32 mac_id;
4118 u32 pdev_id;
4120 u32 cfgd_tx_streams;
4121 u32 cfgd_rx_streams;
4374 u32 dfs_region;
4375 u32 phybitmap;
4376 u32 min_bw_2ghz;
4377 u32 max_bw_2ghz;
4378 u32 min_bw_5ghz;
4379 u32 max_bw_5ghz;
4380 u32 num_2ghz_reg_rules;
4381 u32 num_5ghz_reg_rules;
4390 u32 domain_code_6ghz_super_id;
4391 u32 min_bw_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE];
4392 u32 max_bw_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE];
4393 u32 min_bw_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
4394 u32 max_bw_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
4395 u32 num_6ghz_rules_ap[WMI_REG_CURRENT_MAX_AP_TYPE];
4396 u32 num_6ghz_rules_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
4403 u32 status_code;
4404 u32 phy_id;
4405 u32 alpha2;
4406 u32 num_phy;
4407 u32 country_id;
4408 u32 domain_code;
4409 u32 dfs_region;
4410 u32 phybitmap;
4411 u32 min_bw_2ghz;
4412 u32 max_bw_2ghz;
4413 u32 min_bw_5ghz;
4414 u32 max_bw_5ghz;
4415 u32 num_2ghz_reg_rules;
4416 u32 num_5ghz_reg_rules;
4420 u32 tlv_header;
4421 u32 freq_info;
4422 u32 bw_pwr_info;
4423 u32 flag_info;
4429 u32 status_code;
4430 u32 phy_id;
4431 u32 alpha2;
4432 u32 num_phy;
4433 u32 country_id;
4434 u32 domain_code;
4435 u32 dfs_region;
4436 u32 phybitmap;
4437 u32 min_bw_2ghz;
4438 u32 max_bw_2ghz;
4439 u32 min_bw_5ghz;
4440 u32 max_bw_5ghz;
4441 u32 num_2ghz_reg_rules;
4442 u32 num_5ghz_reg_rules;
4443 u32 client_type;
4444 u32 rnr_tpe_usable;
4445 u32 unspecified_ap_usable;
4446 u32 domain_code_6ghz_ap_lpi;
4447 u32 domain_code_6ghz_ap_sp;
4448 u32 domain_code_6ghz_ap_vlp;
4449 u32 domain_code_6ghz_client_lpi[WMI_REG_CLIENT_MAX];
4450 u32 domain_code_6ghz_client_sp[WMI_REG_CLIENT_MAX];
4451 u32 domain_code_6ghz_client_vlp[WMI_REG_CLIENT_MAX];
4452 u32 domain_code_6ghz_super_id;
4453 u32 min_bw_6ghz_ap_sp;
4454 u32 max_bw_6ghz_ap_sp;
4455 u32 min_bw_6ghz_ap_lpi;
4456 u32 max_bw_6ghz_ap_lpi;
4457 u32 min_bw_6ghz_ap_vlp;
4458 u32 max_bw_6ghz_ap_vlp;
4459 u32 min_bw_6ghz_client_sp[WMI_REG_CLIENT_MAX];
4460 u32 max_bw_6ghz_client_sp[WMI_REG_CLIENT_MAX];
4461 u32 min_bw_6ghz_client_lpi[WMI_REG_CLIENT_MAX];
4462 u32 max_bw_6ghz_client_lpi[WMI_REG_CLIENT_MAX];
4463 u32 min_bw_6ghz_client_vlp[WMI_REG_CLIENT_MAX];
4464 u32 max_bw_6ghz_client_vlp[WMI_REG_CLIENT_MAX];
4465 u32 num_6ghz_reg_rules_ap_sp;
4466 u32 num_6ghz_reg_rules_ap_lpi;
4467 u32 num_6ghz_reg_rules_ap_vlp;
4468 u32 num_6ghz_reg_rules_client_sp[WMI_REG_CLIENT_MAX];
4469 u32 num_6ghz_reg_rules_client_lpi[WMI_REG_CLIENT_MAX];
4470 u32 num_6ghz_reg_rules_client_vlp[WMI_REG_CLIENT_MAX];
4474 u32 tlv_header;
4475 u32 freq_info;
4476 u32 bw_pwr_info;
4477 u32 flag_info;
4478 u32 psd_power_info;
4482 u32 vdev_id;
4486 u32 vdev_id;
4491 u32 vdev_id;
4492 u32 tx_status;
4496 u32 vdev_id;
4500 u32 freq; /* Units in MHz */
4501 u32 noise_floor; /* units are dBm */
4503 u32 rx_clear_count_low;
4504 u32 rx_clear_count_high;
4506 u32 cycle_count_low;
4507 u32 cycle_count_high;
4509 u32 tx_cycle_count_low;
4510 u32 tx_cycle_count_high;
4512 u32 rx_cycle_count_low;
4513 u32 rx_cycle_count_high;
4515 u32 rx_bss_cycle_count_low;
4516 u32 rx_bss_cycle_count_high;
4517 u32 pdev_id;
4523 u32 vdev_id;
4525 u32 key_idx;
4526 u32 key_flags;
4527 u32 status;
4531 u32 vdev_id;
4533 u32 key_idx;
4534 u32 key_flags;
4535 u32 status;
4539 u32 vdev_id;
4544 u32 vdev_id;
4549 u32 vdev_id;
4550 u32 fils_tt;
4551 u32 tbtt;
4555 u32 vdev_id;
4556 u32 tx_status;
4564 u32 tx_frame_count; /* Cycles spent transmitting frames */
4565 u32 rx_frame_count; /* Cycles spent receiving frames */
4566 u32 rx_clear_count; /* Total channel busy time, evidently */
4567 u32 cycle_count; /* Total on-channel time */
4568 u32 phy_err_count;
4569 u32 chan_tx_pwr;
4573 u32 ack_rx_bad;
4574 u32 rts_bad;
4575 u32 rts_good;
4576 u32 fcs_bad;
4577 u32 no_beacons;
4578 u32 mib_int_count;
4613 u32 hw_paused;
4622 u32 tx_ko;
4624 u32 tx_xretry;
4627 u32 data_rc;
4630 u32 self_triggers;
4633 u32 sw_retry_failure;
4636 u32 illgl_rate_phy_err;
4639 u32 pdev_cont_xretry;
4642 u32 pdev_tx_timeout;
4645 u32 pdev_resets;
4648 u32 stateless_tid_alloc_failure;
4651 u32 phy_underrun;
4654 u32 txop_ovf;
4657 u32 seq_posted;
4660 u32 seq_failed_queueing;
4663 u32 seq_completed;
4666 u32 seq_restarted;
4669 u32 mu_seq_posted;
4739 u32 vdev_id;
4740 u32 beacon_snr;
4741 u32 data_snr;
4742 u32 num_tx_frames[WLAN_MAX_AC];
4743 u32 num_rx_frames;
4744 u32 num_tx_frames_retries[WLAN_MAX_AC];
4745 u32 num_tx_frames_failures[WLAN_MAX_AC];
4746 u32 num_rts_fail;
4747 u32 num_rts_success;
4748 u32 num_rx_err;
4749 u32 num_rx_discard;
4750 u32 num_tx_not_acked;
4751 u32 tx_rate_history[MAX_TX_RATE_VALUES];
4752 u32 beacon_rssi_history[MAX_TX_RATE_VALUES];
4756 u32 vdev_id;
4757 u32 tx_bcn_succ_cnt;
4758 u32 tx_bcn_outage_cnt;
4762 u32 stats_id;
4763 u32 num_pdev_stats;
4764 u32 num_vdev_stats;
4765 u32 num_peer_stats;
4766 u32 num_bcnflt_stats;
4767 u32 num_chan_stats;
4768 u32 num_mib_stats;
4769 u32 pdev_id;
4770 u32 num_bcn_stats;
4771 u32 num_peer_extd_stats;
4772 u32 num_peer_extd2_stats;
4776 u32 vdev_id;
4777 u32 rssi_avg_beacon[WMI_MAX_CHAINS];
4778 u32 rssi_avg_data[WMI_MAX_CHAINS];
4783 u32 num_per_chain_rssi_stats;
4787 u32 pdev_id;
4788 u32 ctl_failsafe_status;
4792 u32 pdev_id;
4793 u32 current_switch_count;
4794 u32 num_vdevs;
4798 u32 pdev_id;
4799 u32 detection_mode;
4800 u32 chan_freq;
4801 u32 chan_width;
4802 u32 detector_id;
4803 u32 segment_id;
4804 u32 timestamp;
4805 u32 is_chirp;
4813 u32 pdev_id;
4825 u32 chan_freq;
4826 u32 channel;
4827 u32 snr;
4829 u32 rate;
4831 u32 buf_len;
4833 u32 flags;
4835 u32 tsf_delta;
4842 u32 channel;
4843 u32 snr;
4844 u32 rate;
4845 u32 phy_mode;
4846 u32 buf_len;
4847 u32 status;
4848 u32 rssi_ctl[ATH_MAX_ANTENNA];
4849 u32 flags;
4851 u32 tsf_delta;
4852 u32 rx_tsf_l32;
4853 u32 rx_tsf_u32;
4854 u32 pdev_id;
4855 u32 chan_freq;
4861 u32 tlv_header;
4862 u32 rssi_ctl_ext[MAX_ANTENNA_EIGHT - ATH_MAX_ANTENNA];
4866 u32 desc_id;
4867 u32 status;
4868 u32 pdev_id;
4869 u32 ppdu_id;
4870 u32 ack_rssi;
4874 u32 event_type; /* %WMI_SCAN_EVENT_ */
4875 u32 reason; /* %WMI_SCAN_REASON_ */
4876 u32 channel_freq; /* only valid for WMI_SCAN_EVENT_FOREIGN_CHANNEL */
4877 u32 scan_req_id;
4878 u32 scan_id;
4879 u32 vdev_id;
4885 u32 tsf_timestamp;
4908 u32 vdev_id;
4909 u32 reason;
4910 u32 rssi;
4917 u32 err_code;
4918 u32 freq;
4919 u32 cmd_flags;
4920 u32 noise_floor;
4921 u32 rx_clear_count;
4922 u32 cycle_count;
4923 u32 chan_tx_pwr_range;
4924 u32 chan_tx_pwr_tp;
4925 u32 rx_frame_count;
4926 u32 my_bss_rx_cycle_count;
4927 u32 rx_11b_mode_data_duration;
4928 u32 tx_frame_cnt;
4929 u32 mac_clk_mhz;
4930 u32 vdev_id;
4934 u32 phy_capability;
4935 u32 max_frag_entry;
4936 u32 num_rf_chains;
4937 u32 ht_cap_info;
4938 u32 vht_cap_info;
4939 u32 vht_supp_mcs;
4940 u32 hw_min_tx_power;
4941 u32 hw_max_tx_power;
4942 u32 sys_cap_info;
4943 u32 min_pkt_size_enable;
4944 u32 max_bcn_ie_size;
4945 u32 max_num_scan_channels;
4946 u32 max_supported_macs;
4947 u32 wmi_fw_sub_feat_caps;
4948 u32 txrx_chainmask;
4949 u32 default_dbs_hw_mode_index;
4950 u32 num_msdu_desc;
4999 u32 wmm_ac;
5000 u32 user_priority;
5001 u32 service_interval;
5002 u32 suspend_interval;
5003 u32 delay_interval;
5007 u32 vdev_id;
5009 u32 num_ac;
5013 u32 wmm_ac;
5014 u32 user_priority;
5015 u32 service_interval;
5016 u32 suspend_interval;
5017 u32 delay_interval;
5181 u32 eeprom_rd;
5182 u32 eeprom_rd_ext;
5183 u32 regcap1;
5184 u32 regcap2;
5185 u32 wireless_modes;
5186 u32 low_2ghz_chan;
5187 u32 high_2ghz_chan;
5188 u32 low_5ghz_chan;
5189 u32 high_5ghz_chan;
5195 u32 len;
5196 u32 req_id;
5216 u32 tlv_header;
5217 u32 cwmin;
5218 u32 cwmax;
5219 u32 aifs;
5220 u32 txoplimit;
5221 u32 acm;
5222 u32 no_ack;
5235 u32 tlv_header;
5236 u32 vdev_id;
5238 u32 wmm_param_type;
5265 u32 sta_cong_timer_ms;
5266 u32 mbss_support;
5267 u32 default_slot_size;
5268 u32 congestion_thresh_setup;
5269 u32 congestion_thresh_teardown;
5270 u32 congestion_thresh_critical;
5271 u32 interference_thresh_teardown;
5272 u32 interference_thresh_setup;
5273 u32 min_no_sta_setup;
5274 u32 min_no_sta_teardown;
5275 u32 no_of_bcast_mcast_slots;
5276 u32 min_no_twt_slots;
5277 u32 max_no_sta_twt;
5278 u32 mode_check_interval;
5279 u32 add_sta_slot_interval;
5280 u32 remove_sta_slot_interval;
5284 u32 tlv_header;
5285 u32 pdev_id;
5286 u32 sta_cong_timer_ms;
5287 u32 mbss_support;
5288 u32 default_slot_size;
5289 u32 congestion_thresh_setup;
5290 u32 congestion_thresh_teardown;
5291 u32 congestion_thresh_critical;
5292 u32 interference_thresh_teardown;
5293 u32 interference_thresh_setup;
5294 u32 min_no_sta_setup;
5295 u32 min_no_sta_teardown;
5296 u32 no_of_bcast_mcast_slots;
5297 u32 min_no_twt_slots;
5298 u32 max_no_sta_twt;
5299 u32 mode_check_interval;
5300 u32 add_sta_slot_interval;
5301 u32 remove_sta_slot_interval;
5305 u32 tlv_header;
5306 u32 pdev_id;
5326 u32 tlv_header;
5327 u32 vdev_id;
5329 u32 dialog_id;
5330 u32 wake_intvl_us;
5331 u32 wake_intvl_mantis;
5332 u32 wake_dura_us;
5333 u32 sp_offset_us;
5334 u32 flags;
5338 u32 vdev_id;
5340 u32 dialog_id;
5341 u32 wake_intvl_us;
5342 u32 wake_intvl_mantis;
5343 u32 wake_dura_us;
5344 u32 sp_offset_us;
5366 u32 vdev_id;
5368 u32 dialog_id;
5369 u32 status;
5373 u32 vdev_id;
5375 u32 dialog_id;
5379 u32 tlv_header;
5380 u32 vdev_id;
5382 u32 dialog_id;
5386 u32 vdev_id;
5388 u32 dialog_id;
5392 u32 tlv_header;
5393 u32 vdev_id;
5395 u32 dialog_id;
5399 u32 vdev_id;
5401 u32 dialog_id;
5402 u32 sp_offset_us;
5403 u32 next_twt_size;
5407 u32 tlv_header;
5408 u32 vdev_id;
5410 u32 dialog_id;
5411 u32 sp_offset_us;
5412 u32 next_twt_size;
5416 u32 tlv_header;
5417 u32 pdev_id;
5418 u32 enable;
5421 u32 vdev_id;
5425 u32 tlv_header;
5426 u32 pdev_id;
5427 u32 bitmap[2];
5445 u32 tlv_header;
5446 u32 vdev_id;
5447 u32 flags;
5448 u32 evt_type;
5449 u32 current_bss_color;
5450 u32 detection_period_ms;
5451 u32 scan_period_ms;
5452 u32 free_slot_expiry_time_ms;
5456 u32 tlv_header;
5457 u32 vdev_id;
5458 u32 enable;
5462 u32 vdev_id;
5463 u32 evt_type;
5471 u32 tlv_header;
5472 u32 lro_enable;
5473 u32 res;
5474 u32 th_4[ATH11K_IPV4_TH_SEED_SIZE];
5475 u32 th_6[ATH11K_IPV6_TH_SEED_SIZE];
5476 u32 pdev_id;
5499 u32 vdev_id;
5500 u32 scan_count;
5501 u32 scan_period;
5502 u32 scan_priority;
5503 u32 scan_fft_size;
5504 u32 scan_gc_ena;
5505 u32 scan_restart_ena;
5506 u32 scan_noise_floor_ref;
5507 u32 scan_init_delay;
5508 u32 scan_nb_tone_thr;
5509 u32 scan_str_bin_thr;
5510 u32 scan_wb_rpt_mode;
5511 u32 scan_rssi_rpt_mode;
5512 u32 scan_rssi_thr;
5513 u32 scan_pwr_format;
5514 u32 scan_rpt_mode;
5515 u32 scan_bin_scale;
5516 u32 scan_dbm_adj;
5517 u32 scan_chn_mask;
5521 u32 tlv_header;
5531 u32 tlv_header;
5532 u32 vdev_id;
5533 u32 trigger_cmd;
5534 u32 enable_cmd;
5538 u32 tlv_header;
5539 u32 pdev_id;
5540 u32 module_id; /* see enum wmi_direct_buffer_module */
5541 u32 base_paddr_lo;
5542 u32 base_paddr_hi;
5543 u32 head_idx_paddr_lo;
5544 u32 head_idx_paddr_hi;
5545 u32 tail_idx_paddr_lo;
5546 u32 tail_idx_paddr_hi;
5547 u32 num_elems; /* Number of elems in the ring */
5548 u32 buf_size; /* size of allocated buffer in bytes */
5551 u32 num_resp_per_event;
5556 u32 event_timeout_ms;
5560 u32 pdev_id;
5561 u32 module_id;
5562 u32 num_buf_release_entry;
5563 u32 num_meta_data_entry;
5567 u32 tlv_header;
5568 u32 paddr_lo;
5573 u32 paddr_hi;
5582 u32 tlv_header;
5584 u32 reset_delay;
5585 u32 freq1;
5586 u32 freq2;
5587 u32 ch_width;
5596 u32 tlv_header;
5597 u32 vdev_id;
5598 u32 interval;
5599 u32 config; /* enum wmi_fils_discovery_cmd_type */
5603 u32 tlv_header;
5604 u32 vdev_id;
5605 u32 buf_len;
5609 u32 tlv_header;
5610 u32 vdev_id;
5611 u32 buf_len;
5615 u32 num_vdevs;
5616 u32 num_peers;
5617 u32 num_active_peers;
5618 u32 num_offload_peers;
5619 u32 num_offload_reorder_buffs;
5620 u32 num_peer_keys;
5621 u32 num_tids;
5622 u32 ast_skid_limit;
5623 u32 tx_chain_mask;
5624 u32 rx_chain_mask;
5625 u32 rx_timeout_pri[4];
5626 u32 rx_decap_mode;
5627 u32 scan_max_pending_req;
5628 u32 bmiss_offload_max_vdev;
5629 u32 roam_offload_max_vdev;
5630 u32 roam_offload_max_ap_profiles;
5631 u32 num_mcast_groups;
5632 u32 num_mcast_table_elems;
5633 u32 mcast2ucast_mode;
5634 u32 tx_dbg_log_size;
5635 u32 num_wds_entries;
5636 u32 dma_burst_size;
5637 u32 mac_aggr_delim;
5638 u32 rx_skip_defrag_timeout_dup_detection_check;
5639 u32 vow_config;
5640 u32 gtk_offload_max_vdev;
5641 u32 num_msdu_desc;
5642 u32 max_frag_entries;
5643 u32 max_peer_ext_stats;
5644 u32 smart_ant_cap;
5645 u32 bk_minfree;
5646 u32 be_minfree;
5647 u32 vi_minfree;
5648 u32 vo_minfree;
5649 u32 rx_batchmode;
5650 u32 tt_support;
5651 u32 flag1;
5652 u32 iphdr_pad_config;
5653 u32 qwrap_config:16,
5655 u32 num_tdls_vdevs;
5656 u32 num_tdls_conn_table_entries;
5657 u32 beacon_tx_offload_max_vdev;
5658 u32 num_multicast_filter_entries;
5659 u32 num_wow_filters;
5660 u32 num_keep_alive_pattern;
5661 u32 keep_alive_pattern_size;
5662 u32 max_tdls_concurrent_sleep_sta;
5663 u32 max_tdls_concurrent_buffer_sta;
5664 u32 wmi_send_separate;
5665 u32 num_ocb_vdevs;
5666 u32 num_ocb_channels;
5667 u32 num_ocb_schedules;
5668 u32 num_ns_ext_tuples_cfg;
5669 u32 bpf_instruction_size;
5670 u32 max_bssid_rx_filters;
5671 u32 use_pdev_id;
5672 u32 peer_map_unmap_v2_support;
5673 u32 sched_params;
5674 u32 twt_ap_pdev_count;
5675 u32 twt_ap_sta_count;
5677 u32 ema_max_vap_cnt;
5678 u32 ema_max_profile_period;
5691 u32 tlv_header;
5692 u32 dbg_log_param;
5693 u32 value;
5717 u32 peer_ps_state;
5718 u32 ps_supported_bitmap;
5719 u32 peer_ps_valid;
5720 u32 peer_ps_timestamp;
5727 u32 max_msg_len[MAX_RADIOS];
5733 u32 num_mem_chunks;
5734 u32 rx_decap_mode;
5750 u32 tlv_header;
5751 u32 vdev_id;
5752 u32 enable;
5753 u32 hw_filter_bitmap;
5901 u32 vdev_id;
5902 u32 flag;
5904 u32 data_len;
5933 u32 tlv_header;
5934 u32 vdev_id;
5935 u32 is_add;
5936 u32 event_bitmap;
5940 u32 tlv_header;
5941 u32 enable;
5942 u32 pause_iface_config;
5943 u32 flags;
5947 u32 tlv_header;
5948 u32 reserved;
5952 u32 vdev_id;
5953 u32 flag;
5954 u32 wake_reason;
5955 u32 data_len;
5959 u32 tlv_header;
5962 u32 pattern_offset;
5963 u32 pattern_len;
5964 u32 bitmask_len;
5965 u32 pattern_id;
5969 u32 tlv_header;
5970 u32 vdev_id;
5971 u32 pattern_id;
5972 u32 pattern_type;
5976 u32 tlv_header;
5977 u32 vdev_id;
5978 u32 pattern_id;
5979 u32 pattern_type;
6028 u32 valid;
6033 u32 valid;
6034 u32 enc_type;
6038 u32 valid;
6039 u32 auth_type;
6043 u32 valid;
6044 u32 bcast_nw_type;
6048 u32 valid;
6054 u32 tlv_header;
6066 u32 authentication;
6067 u32 encryption;
6068 u32 bcast_nw_type;
6079 u32 fast_scan_period;
6080 u32 slow_scan_period;
6085 u32 delay_start_time;
6086 u32 active_min_time;
6087 u32 active_max_time;
6088 u32 passive_min_time;
6089 u32 passive_max_time;
6092 u32 enable_pno_scan_randomization;
6098 u32 tlv_header;
6099 u32 flags;
6100 u32 vdev_id;
6101 u32 fast_scan_max_cycles;
6102 u32 active_dwell_time;
6103 u32 passive_dwell_time;
6104 u32 probe_bundle_size;
6107 u32 rest_time;
6110 u32 max_rest_time;
6113 u32 scan_backoff_multiplier;
6116 u32 fast_scan_period;
6119 u32 slow_scan_period;
6121 u32 no_of_ssids;
6123 u32 num_of_channels;
6126 u32 delay_start_time;
6135 u32 ie_bitmap[8];
6138 u32 num_vendor_oui;
6141 u32 num_cnlo_band_pref;
6145 * u32 channel_list[num_of_channels];
6157 u32 tlv_header;
6158 u32 flags;
6172 u32 tlv_header;
6173 u32 flags;
6181 u32 tlv_header;
6182 u32 flags;
6183 u32 vdev_id;
6184 u32 num_ns_ext_tuples;
6207 u32 word0;
6208 u32 word1;
6214 u32 vdev_id;
6215 u32 flags;
6216 u32 refresh_cnt;
6229 u32 tlv_header;
6230 u32 vdev_id;
6231 u32 flags;
6242 u32 tlv_header;
6243 u32 pdev_id;
6244 u32 sar_len;
6245 u32 rsvd_len;
6249 u32 tlv_header;
6250 u32 pdev_id;
6251 u32 rsvd_len;
6255 u32 tlv_header;
6256 u32 vdev_id;
6257 u32 enabled;
6260 u32 method;
6263 u32 interval;
6271 u32 tlv_header;
6272 u32 src_ip4_addr;
6273 u32 dest_ip4_addr;
6278 u32 vdev_id;
6279 u32 enabled;
6280 u32 method;
6281 u32 interval;
6282 u32 src_ip4_addr;
6283 u32 dest_ip4_addr;
6301 u32 cmd_id);
6302 struct sk_buff *ath11k_wmi_alloc_skb(struct ath11k_wmi_base *wmi_sc, u32 len);
6303 int ath11k_wmi_mgmt_send(struct ath11k *ar, u32 vdev_id, u32 buf_id,
6305 int ath11k_wmi_bcn_tmpl(struct ath11k *ar, u32 vdev_id,
6307 struct sk_buff *bcn, u32 ema_param);
6309 int ath11k_wmi_vdev_up(struct ath11k *ar, u32 vdev_id, u32 aid,
6310 const u8 *bssid, u8 *tx_bssid, u32 nontx_profile_idx,
6311 u32 nontx_profile_cnt);
6316 u32 vdev_id, u32 param_id, u32 param_val);
6317 int ath11k_wmi_pdev_set_param(struct ath11k *ar, u32 param_id,
6318 u32 param_value, u8 pdev_id);
6334 u32 ba_window_size);
6337 int ath11k_wmi_vdev_set_param_cmd(struct ath11k *ar, u32 vdev_id,
6338 u32 param_id, u32 param_value);
6340 int ath11k_wmi_set_sta_ps_param(struct ath11k *ar, u32 vdev_id,
6341 u32 param, u32 param_value);
6342 int ath11k_wmi_force_fw_hang_cmd(struct ath11k *ar, u32 type, u32 delay_time_ms);
6351 int ath11k_wmi_send_wmm_update_cmd_tlv(struct ath11k *ar, u32 vdev_id,
6353 int ath11k_wmi_pdev_suspend(struct ath11k *ar, u32 suspend_opt,
6354 u32 pdev_id);
6355 int ath11k_wmi_pdev_resume(struct ath11k *ar, u32 pdev_id);
6374 u32 pdev_id);
6375 int ath11k_wmi_addba_clear_resp(struct ath11k *ar, u32 vdev_id, const u8 *mac);
6376 int ath11k_wmi_addba_send(struct ath11k *ar, u32 vdev_id, const u8 *mac,
6377 u32 tid, u32 buf_size);
6378 int ath11k_wmi_addba_set_resp(struct ath11k *ar, u32 vdev_id, const u8 *mac,
6379 u32 tid, u32 status);
6380 int ath11k_wmi_delba_send(struct ath11k *ar, u32 vdev_id, const u8 *mac,
6381 u32 tid, u32 initiator, u32 reason);
6383 u32 vdev_id, u32 bcn_ctrl_op);
6392 int ath11k_wmi_send_11d_scan_stop_cmd(struct ath11k *ar, u32 vdev_id);
6397 int ath11k_wmi_pdev_pktlog_enable(struct ath11k *ar, u32 pktlog_filter);
6408 struct ath11k_fw_stats *fw_stats, u32 stats_id,
6412 int ath11k_wmi_send_twt_enable_cmd(struct ath11k *ar, u32 pdev_id,
6414 int ath11k_wmi_send_twt_disable_cmd(struct ath11k *ar, u32 pdev_id);
6423 int ath11k_wmi_send_obss_spr_cmd(struct ath11k *ar, u32 vdev_id,
6425 int ath11k_wmi_pdev_set_srg_bss_color_bitmap(struct ath11k *ar, u32 *bitmap);
6426 int ath11k_wmi_pdev_set_srg_patial_bssid_bitmap(struct ath11k *ar, u32 *bitmap);
6428 u32 *bitmap);
6430 u32 *bitmap);
6432 u32 *bitmap);
6434 u32 *bitmap);
6435 int ath11k_wmi_send_obss_color_collision_cfg_cmd(struct ath11k *ar, u32 vdev_id,
6436 u8 bss_color, u32 period,
6438 int ath11k_wmi_send_bss_color_change_enable_cmd(struct ath11k *ar, u32 vdev_id,
6443 int ath11k_wmi_vdev_spectral_enable(struct ath11k *ar, u32 vdev_id,
6444 u32 trigger, u32 enable);
6447 int ath11k_wmi_fils_discovery_tmpl(struct ath11k *ar, u32 vdev_id,
6449 int ath11k_wmi_fils_discovery(struct ath11k *ar, u32 vdev_id, u32 interval,
6451 int ath11k_wmi_probe_resp_tmpl(struct ath11k *ar, u32 vdev_id,
6459 int ath11k_wmi_fw_dbglog_cfg(struct ath11k *ar, u32 *module_id_bitmap,
6461 int ath11k_wmi_wow_config_pno(struct ath11k *ar, u32 vdev_id,
6463 int ath11k_wmi_wow_del_pattern(struct ath11k *ar, u32 vdev_id, u32 pattern_id);
6464 int ath11k_wmi_wow_add_pattern(struct ath11k *ar, u32 vdev_id, u32 pattern_id,
6467 int ath11k_wmi_wow_add_wakeup_event(struct ath11k *ar, u32 vdev_id,
6469 u32 enable);
6470 int ath11k_wmi_hw_data_filter_cmd(struct ath11k *ar, u32 vdev_id,
6471 u32 filter_bitmap, bool enable);