ath/ath10k/hw.h

1 /* SPDX-License-Identifier: ISC */
3  * Copyright (c) 2005-2011 Atheros Communications Inc.
4  * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
133 /* WCN3990 1.0 definitions */
135 #define WCN3990_HW_1_0_FW_DIR		ATH10K_FW_DIR "/WCN3990/hw1.0"
141 #define ATH10K_FW_API2_FILE		"firmware-2.bin"
142 #define ATH10K_FW_API3_FILE		"firmware-3.bin"
145 #define ATH10K_FW_API4_FILE		"firmware-4.bin"
148 #define ATH10K_FW_API5_FILE		"firmware-5.bin"
150 /* the firmware-6.bin blob */
151 #define ATH10K_FW_API6_FILE		"firmware-6.bin"
154 #define ATH10K_FW_UTF_API2_FILE		"utf-2.bin"
159 #define ATH10K_FIRMWARE_MAGIC               "QCA-ATH10K"
160 #define ATH10K_BOARD_MAGIC                  "QCA-ATH10K-BOARD"
162 #define ATH10K_BOARD_API2_FILE         "board-2.bin"
405 #define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X)
406 #define QCA_REV_9887(ar) ((ar)->hw_rev == ATH10K_HW_QCA9887)
407 #define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174)
408 #define QCA_REV_99X0(ar) ((ar)->hw_rev == ATH10K_HW_QCA99X0)
409 #define QCA_REV_9888(ar) ((ar)->hw_rev == ATH10K_HW_QCA9888)
410 #define QCA_REV_9984(ar) ((ar)->hw_rev == ATH10K_HW_QCA9984)
411 #define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377)
412 #define QCA_REV_40XX(ar) ((ar)->hw_rev == ATH10K_HW_QCA4019)
413 #define QCA_REV_WCN3990(ar) ((ar)->hw_rev == ATH10K_HW_WCN3990)
416  *  - raw appears in nwifi decap, raw and nwifi appear in ethernet decap
417  *  - raw have FCS, nwifi doesn't
418  *  - ethernet frames have 802.11 header decapped and parts (base hdr, cipher
424 	/* Native Wifi decap mode is used to align IP frames to 4-byte
425 	 * boundaries and avoid a very expensive re-alignment in mac80211.
491 	ATH10K_HW_REFCLK_UNKNOWN = -1,
596 	/* Targets supporting physical addressing capability above 32-bits */
672 	if (hw->hw_ops->tx_data_rssi_pad_bytes)  in ath10k_tx_data_rssi_get_pad_bytes()
673 		return hw->hw_ops->tx_data_rssi_pad_bytes(htt);  in ath10k_tx_data_rssi_get_pad_bytes()
681 	if (hw->hw_ops->is_rssi_enable)  in ath10k_is_rssi_enable()
682 		return hw->hw_ops->is_rssi_enable(resp);  in ath10k_is_rssi_enable()
761 /* Target specific defines for WMI-TLV firmware */
772 /* Target specific defines for WMI-HL-1.0 firmware */
783 #define NUM_TARGET_CE_CONFIG_WLAN ar->hw_values->num_target_ce_config_wlan
803 /* 100 ms for video, best-effort, and background */
849 #define CE_COUNT ar->hw_values->ce_count
863 #define MSI_ASSIGN_CE_MAX	ar->hw_values->msi_assign_ce_max
866 #define RTC_STATE_V_ON				ar->hw_values->rtc_state_val_on
876 #define RTC_SOC_BASE_ADDRESS			ar->regs->rtc_soc_base_address
877 #define RTC_WMAC_BASE_ADDRESS			ar->regs->rtc_wmac_base_address
881 #define SOC_CORE_BASE_ADDRESS			ar->regs->soc_core_base_address
886 #define WLAN_MAC_BASE_ADDRESS			ar->regs->wlan_mac_base_address
890 #define CE_WRAPPER_BASE_ADDRESS			ar->regs->ce_wrapper_base_address
891 #define CE0_BASE_ADDRESS			ar->regs->ce0_base_address
892 #define CE1_BASE_ADDRESS			ar->regs->ce1_base_address
893 #define CE2_BASE_ADDRESS			ar->regs->ce2_base_address
894 #define CE3_BASE_ADDRESS			ar->regs->ce3_base_address
895 #define CE4_BASE_ADDRESS			ar->regs->ce4_base_address
896 #define CE5_BASE_ADDRESS			ar->regs->ce5_base_address
897 #define CE6_BASE_ADDRESS			ar->regs->ce6_base_address
898 #define CE7_BASE_ADDRESS			ar->regs->ce7_base_address
901 #define PCIE_LOCAL_BASE_ADDRESS		ar->regs->pcie_local_base_address
905 #define SOC_RESET_CONTROL_SI0_RST_MASK		ar->regs->soc_reset_control_si0_rst_mask
906 #define SOC_RESET_CONTROL_CE_RST_MASK		ar->regs->soc_reset_control_ce_rst_mask
920 #define SOC_CHIP_ID_ADDRESS			ar->regs->soc_chip_id_address
982 #define PCIE_INTR_CLR_ADDRESS			ar->regs->pcie_intr_clr_address
983 #define SCRATCH_3_ADDRESS			ar->regs->scratch_3_address
987 #define CCNT_TO_MSEC(ar, x) ((x) / ar->hw_params.channel_counters_freq_hz)
990 #define FW_INDICATOR_ADDRESS			ar->regs->fw_indicator_address
996 #define PCIE_INTR_FIRMWARE_MASK			ar->regs->pcie_intr_fw_mask
997 #define PCIE_INTR_CE_MASK_ALL			ar->regs->pcie_intr_ce_mask_all
1208 #define REGION_ACCESS_SIZE_MASK		(REGION_ACCESS_SIZE_LIMIT - 1)