net/wan/hd64572.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3  * hd64572.h	Description of the Hitachi HD64572 (SCA-II), valid for
4  * 		CPU modes 0 & 2.
8  * Copyright:   (c) 2000-2001 Cyclades Corp.
15  * PC300 initial CVS version (3.4.0-pre1)
48 #define	DTX_REG(reg, chan)	(reg + 0x20*(2*chan + 1))	/* DMA Tx */
50 #define	TTX_REG(reg, chan)	(reg + 0x10*(2*chan + 1))	/* Timer Tx */
53 #define IR0_DTX(val, chan)	((val)<<(4*(2*chan + 1)))	/* Int DMA Tx */
62 #define MD2	0x13a	/* Mode reg 2 */
73 #define ST2	0x11a	/* Status reg 2 */
79 #define IE2	0x122	/* Interrupt enable reg 2 */
94 #define CST2	0x10a	/* Current Status Register 2 */
98 #define TFN	0x143	/* Inter-transmit-frame Time Fill Ctl Reg */
125 #define BOLR		0x0c		/* Back-off Length Reg */
126 #define DSR_RX(chan)	(0x48 + 2*chan)	/* DMA Status Reg (Rx) */
127 #define DSR_TX(chan)	(0x49 + 2*chan)	/* DMA Status Reg (Tx) */
128 #define DIR_RX(chan)	(0x4c + 2*chan)	/* DMA Interrupt Enable Reg (Rx) */
129 #define DIR_TX(chan)	(0x4d + 2*chan)	/* DMA Interrupt Enable Reg (Tx) */
130 #define FCT_RX(chan)	(0x50 + 2*chan)	/* Frame End Interrupt Counter (Rx) */
131 #define FCT_TX(chan)	(0x51 + 2*chan)	/* Frame End Interrupt Counter (Tx) */
132 #define DMR_RX(chan)	(0x54 + 2*chan)	/* DMA Mode Reg (Rx) */
133 #define DMR_TX(chan)	(0x55 + 2*chan)	/* DMA Mode Reg (Tx) */
134 #define DCR_RX(chan)	(0x58 + 2*chan)	/* DMA Command Reg (Rx) */
135 #define DCR_TX(chan)	(0x59 + 2*chan)	/* DMA Command Reg (Tx) */
143 #define DARL	0x80	/* Dest Addr Register L (single-block, RX only) */
144 #define DARH	0x81	/* Dest Addr Register H (single-block, RX only) */
145 #define DARB	0x82	/* Dest Addr Register B (single-block, RX only) */
146 #define DARBH	0x83	/* Dest Addr Register BH (single-block, RX only) */
147 #define SARL	0x80	/* Source Addr Register L (single-block, TX only) */
148 #define SARH	0x81	/* Source Addr Register H (single-block, TX only) */
149 #define SARB	0x82	/* Source Addr Register B (single-block, TX only) */
150 #define DARBH	0x83	/* Source Addr Register BH (single-block, TX only) */
151 #define BARL	0x80	/* Buffer Addr Register L (chained-block) */
152 #define BARH	0x81	/* Buffer Addr Register H (chained-block) */
153 #define BARB	0x82	/* Buffer Addr Register B (chained-block) */
154 #define BARBH	0x83	/* Buffer Addr Register BH (chained-block) */
183 	u8 unused;		/* pads to 4-byte boundary */
193 	6	-		Short Frame
194 	5	-		Abort
195 	4	-		Residual bit
197 	2	-		CRC
199 	0	EOT		-
228 /* Status Counter Registers */
229 #define CMCR	0x158	/* Counter Master Ctl Reg */
230 #define TECNTL	0x160	/* Tx EOM Counter L */
231 #define TECNTM	0x161	/* Tx EOM Counter M */
232 #define TECNTH	0x162	/* Tx EOM Counter H */
233 #define TECCR	0x163	/* Tx EOM Counter Ctl Reg */
234 #define URCNTL	0x164	/* Underrun Counter L */
235 #define URCNTH	0x165	/* Underrun Counter H */
236 #define URCCR	0x167	/* Underrun Counter Ctl Reg */
237 #define RECNTL	0x168	/* Rx EOM Counter L */
238 #define RECNTM	0x169	/* Rx EOM Counter M */
239 #define RECNTH	0x16a	/* Rx EOM Counter H */
240 #define RECCR	0x16b	/* Rx EOM Counter Ctl Reg */
241 #define ORCNTL	0x16c	/* Overrun Counter L */
242 #define ORCNTH	0x16d	/* Overrun Counter H */
243 #define ORCCR	0x16f	/* Overrun Counter Ctl Reg */
244 #define CECNTL	0x170	/* CRC Counter L */
245 #define CECNTH	0x171	/* CRC Counter H */
246 #define CECCR	0x173	/* CRC Counter Ctl Reg */
247 #define ABCNTL	0x174	/* Abort frame Counter L */
248 #define ABCNTH	0x175	/* Abort frame Counter H */
249 #define ABCCR	0x177	/* Abort frame Counter Ctl Reg */
250 #define SHCNTL	0x178	/* Short frame Counter L */
251 #define SHCNTH	0x179	/* Short frame Counter H */
252 #define SHCCR	0x17b	/* Short frame Counter Ctl Reg */
253 #define RSCNTL	0x17c	/* Residual bit Counter L */
254 #define RSCNTH	0x17d	/* Residual bit Counter H */
255 #define RSCCR	0x17f	/* Residual bit Counter Ctl Reg */
284 #define MD0_HDLC        0x80	/* Bit-sync HDLC mode */