Lines Matching +full:gen +full:- +full:2
4 * Copyright (C) 2008-2022, VMware, Inc. All Rights Reserved.
8 * Free Software Foundation; version 2 of the License and no later version.
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
23 * Maintained by: pv-drivers@vmware.com
57 VMXNET3_REG_RXPROD2 = 0xA00 /* Rx Producer Index for ring 2 */
64 VMXNET3_REG_LB_RXPROD2 = 0x1800, /* Rx Producer Index for ring 2 */
73 #define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */
129 * Little Endian layout of bitfields -
131 * Byte 1 : oco gen 13.len.8
132 * Byte 2 : 5.msscof.0 ext1 dtype
135 * Big Endian layout of bitfields -
138 * Byte 2 : oco gen 13.len.8
154 u32 gen:1; /* generation bit */ member
158 u32 gen:1; /* generation bit */ member
171 u32 om:2; /* offload mode */
175 u32 om:2; /* offload mode */
187 #define VMXNET3_OM_CSUM 2
195 #define VMXNET3_TXD_GEN_DWORD_SHIFT 2
225 u32 gen:1; /* generation bit */ member
232 u32 gen:1; /* Generation bit */ member
242 u32 gen:1; /* Generation bit */ member
265 u32 ext1:2; /* bit 0: indicating v4/v6/.. is for inner header */
270 u32 ext1:2; /* bit 0: indicating v4/v6/.. is for inner header */
296 u32 gen:1; /* generation bit */ member
318 u32 gen:1; /* generation bit */ member
329 u32 gen:1; /* generation bit */ member
351 u32 gen:1; /* generation bit */ member
373 #define VMXNET3_RCD_RSS_TYPE_TCPIPV4 2
384 __le64 qword[2];
400 #define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / \
403 /* max # of tx descs for a non-tso pkt */
409 #define VMXNET3_MAX_RX_BUF_SIZE ((1 << 14) - 1)
416 #define VMXNET3_RING_BA_MASK (VMXNET3_RING_BA_ALIGN - 1)
420 #define VMXNET3_RING_SIZE_MASK (VMXNET3_RING_SIZE_ALIGN - 1)
424 #define VMXNET3_TXDATA_DESC_SIZE_MASK (VMXNET3_TXDATA_DESC_SIZE_ALIGN - 1)
428 #define VMXNET3_RXDATA_DESC_SIZE_MASK (VMXNET3_RXDATA_DESC_SIZE_ALIGN - 1)
463 VMXNET3_GOS_BITS_64 = 2,
474 u32 gosBits:2; /* 32-bit or 64-bit? */
476 u32 gosBits:2; /* 32-bit or 64-bit? */
535 __le64 rxRingBasePA[2];
539 __le32 rxRingSize[2]; /* # of rx desc */
552 VMXNET3_IMM_LAZY = 2
558 VMXNET3_IT_MSI = 2,
585 __le32 reserved[2];
706 VMXNET3_COALESCE_STATIC = 2,
768 __le64 data[2];
772 /* read-only region for device, read by dev in response to a SET cmd */
782 /* read-only region for device, read by dev in response to a SET cmd */
807 #define VMXNET3_ECR_LINK (1 << 2)
811 /* flip the gen bit of a ring */
812 #define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1) argument
814 /* only use this if moving the idx won't affect the gen bit */
841 #define VMXNET3_CAP_GENEVE_CHECKSUM_OFFLOAD 2 /* bit 2 of DCR 0 */