Lines Matching full:phydev
15 * @phydev: target phy_device struct
17 static bool genphy_c45_baset1_able(struct phy_device *phydev) in genphy_c45_baset1_able() argument
21 if (phydev->pma_extable == -ENODATA) { in genphy_c45_baset1_able()
22 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); in genphy_c45_baset1_able()
26 phydev->pma_extable = val; in genphy_c45_baset1_able()
29 return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1); in genphy_c45_baset1_able()
34 * @phydev: target phy_device struct
36 static bool genphy_c45_pma_can_sleep(struct phy_device *phydev) in genphy_c45_pma_can_sleep() argument
40 stat1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT1); in genphy_c45_pma_can_sleep()
49 * @phydev: target phy_device struct
51 int genphy_c45_pma_resume(struct phy_device *phydev) in genphy_c45_pma_resume() argument
53 if (!genphy_c45_pma_can_sleep(phydev)) in genphy_c45_pma_resume()
56 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, in genphy_c45_pma_resume()
63 * @phydev: target phy_device struct
65 int genphy_c45_pma_suspend(struct phy_device *phydev) in genphy_c45_pma_suspend() argument
67 if (!genphy_c45_pma_can_sleep(phydev)) in genphy_c45_pma_suspend()
70 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, in genphy_c45_pma_suspend()
78 * @phydev: target phy_device struct
80 int genphy_c45_pma_baset1_setup_master_slave(struct phy_device *phydev) in genphy_c45_pma_baset1_setup_master_slave() argument
84 switch (phydev->master_slave_set) { in genphy_c45_pma_baset1_setup_master_slave()
96 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); in genphy_c45_pma_baset1_setup_master_slave()
100 return phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL, in genphy_c45_pma_baset1_setup_master_slave()
107 * @phydev: target phy_device struct
109 int genphy_c45_pma_setup_forced(struct phy_device *phydev) in genphy_c45_pma_setup_forced() argument
114 if (phydev->duplex != DUPLEX_FULL) in genphy_c45_pma_setup_forced()
117 ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); in genphy_c45_pma_setup_forced()
121 ctrl2 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2); in genphy_c45_pma_setup_forced()
132 switch (phydev->speed) { in genphy_c45_pma_setup_forced()
134 if (genphy_c45_baset1_able(phydev)) in genphy_c45_pma_setup_forced()
167 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1); in genphy_c45_pma_setup_forced()
171 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2); in genphy_c45_pma_setup_forced()
175 if (genphy_c45_baset1_able(phydev)) { in genphy_c45_pma_setup_forced()
176 ret = genphy_c45_pma_baset1_setup_master_slave(phydev); in genphy_c45_pma_setup_forced()
181 if (phydev->speed == SPEED_1000) in genphy_c45_pma_setup_forced()
184 ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL, in genphy_c45_pma_setup_forced()
190 return genphy_c45_an_disable_aneg(phydev); in genphy_c45_pma_setup_forced()
202 static int genphy_c45_baset1_an_config_aneg(struct phy_device *phydev) in genphy_c45_baset1_an_config_aneg() argument
213 switch (phydev->master_slave_set) { in genphy_c45_baset1_an_config_aneg()
232 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); in genphy_c45_baset1_an_config_aneg()
236 adv_l |= linkmode_adv_to_mii_t1_adv_l_t(phydev->advertising); in genphy_c45_baset1_an_config_aneg()
238 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L, in genphy_c45_baset1_an_config_aneg()
245 adv_m |= linkmode_adv_to_mii_t1_adv_m_t(phydev->advertising); in genphy_c45_baset1_an_config_aneg()
247 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M, in genphy_c45_baset1_an_config_aneg()
259 * @phydev: target phy_device struct
261 * Configure advertisement registers based on modes set in phydev->advertising
266 int genphy_c45_an_config_aneg(struct phy_device *phydev) in genphy_c45_an_config_aneg() argument
271 linkmode_and(phydev->advertising, phydev->advertising, in genphy_c45_an_config_aneg()
272 phydev->supported); in genphy_c45_an_config_aneg()
274 ret = genphy_c45_an_config_eee_aneg(phydev); in genphy_c45_an_config_aneg()
280 if (genphy_c45_baset1_able(phydev)) in genphy_c45_an_config_aneg()
281 return genphy_c45_baset1_an_config_aneg(phydev); in genphy_c45_an_config_aneg()
283 adv = linkmode_adv_to_mii_adv_t(phydev->advertising); in genphy_c45_an_config_aneg()
285 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, in genphy_c45_an_config_aneg()
294 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); in genphy_c45_an_config_aneg()
296 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, in genphy_c45_an_config_aneg()
311 * @phydev: target phy_device struct
318 int genphy_c45_an_disable_aneg(struct phy_device *phydev) in genphy_c45_an_disable_aneg() argument
322 if (genphy_c45_baset1_able(phydev)) in genphy_c45_an_disable_aneg()
325 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, in genphy_c45_an_disable_aneg()
332 * @phydev: target phy_device struct
338 int genphy_c45_restart_aneg(struct phy_device *phydev) in genphy_c45_restart_aneg() argument
342 if (genphy_c45_baset1_able(phydev)) in genphy_c45_restart_aneg()
345 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, reg, in genphy_c45_restart_aneg()
352 * @phydev: target phy_device struct
359 int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart) in genphy_c45_check_and_restart_aneg() argument
364 if (genphy_c45_baset1_able(phydev)) in genphy_c45_check_and_restart_aneg()
369 ret = phy_read_mmd(phydev, MDIO_MMD_AN, reg); in genphy_c45_check_and_restart_aneg()
378 return genphy_c45_restart_aneg(phydev); in genphy_c45_check_and_restart_aneg()
386 * @phydev: target phy_device struct
395 int genphy_c45_aneg_done(struct phy_device *phydev) in genphy_c45_aneg_done() argument
400 if (genphy_c45_baset1_able(phydev)) in genphy_c45_aneg_done()
403 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); in genphy_c45_aneg_done()
411 * @phydev: target phy_device struct
414 * that the link is up, set phydev->link to 1. If an error is encountered,
417 int genphy_c45_read_link(struct phy_device *phydev) in genphy_c45_read_link() argument
423 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { in genphy_c45_read_link()
424 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); in genphy_c45_read_link()
432 phydev->link = 0; in genphy_c45_read_link()
446 if (!phy_polling_mode(phydev) || !phydev->link) { in genphy_c45_read_link()
447 val = phy_read_mmd(phydev, devad, MDIO_STAT1); in genphy_c45_read_link()
454 val = phy_read_mmd(phydev, devad, MDIO_STAT1); in genphy_c45_read_link()
462 phydev->link = link; in genphy_c45_read_link()
471 * pause and asym_pause members in phydev.
473 static int genphy_c45_baset1_read_lpa(struct phy_device *phydev) in genphy_c45_baset1_read_lpa() argument
477 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT); in genphy_c45_baset1_read_lpa()
482 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising); in genphy_c45_baset1_read_lpa()
483 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, 0); in genphy_c45_baset1_read_lpa()
484 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, 0); in genphy_c45_baset1_read_lpa()
486 phydev->pause = 0; in genphy_c45_baset1_read_lpa()
487 phydev->asym_pause = 0; in genphy_c45_baset1_read_lpa()
492 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 1); in genphy_c45_baset1_read_lpa()
494 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_L); in genphy_c45_baset1_read_lpa()
498 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, val); in genphy_c45_baset1_read_lpa()
499 phydev->pause = val & MDIO_AN_T1_ADV_L_PAUSE_CAP ? 1 : 0; in genphy_c45_baset1_read_lpa()
500 phydev->asym_pause = val & MDIO_AN_T1_ADV_L_PAUSE_ASYM ? 1 : 0; in genphy_c45_baset1_read_lpa()
502 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_M); in genphy_c45_baset1_read_lpa()
506 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, val); in genphy_c45_baset1_read_lpa()
513 * @phydev: target phy_device struct
517 * in @phydev. This assumes that the auto-negotiation MMD is present, and
521 int genphy_c45_read_lpa(struct phy_device *phydev) in genphy_c45_read_lpa() argument
525 if (genphy_c45_baset1_able(phydev)) in genphy_c45_read_lpa()
526 return genphy_c45_baset1_read_lpa(phydev); in genphy_c45_read_lpa()
528 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in genphy_c45_read_lpa()
534 phydev->lp_advertising); in genphy_c45_read_lpa()
535 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); in genphy_c45_read_lpa()
536 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, 0); in genphy_c45_read_lpa()
537 phydev->pause = 0; in genphy_c45_read_lpa()
538 phydev->asym_pause = 0; in genphy_c45_read_lpa()
543 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, in genphy_c45_read_lpa()
547 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA); in genphy_c45_read_lpa()
551 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, val); in genphy_c45_read_lpa()
552 phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0; in genphy_c45_read_lpa()
553 phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0; in genphy_c45_read_lpa()
556 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); in genphy_c45_read_lpa()
560 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val); in genphy_c45_read_lpa()
569 * @phydev: target phy_device struct
571 int genphy_c45_pma_baset1_read_master_slave(struct phy_device *phydev) in genphy_c45_pma_baset1_read_master_slave() argument
575 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; in genphy_c45_pma_baset1_read_master_slave()
576 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; in genphy_c45_pma_baset1_read_master_slave()
578 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL); in genphy_c45_pma_baset1_read_master_slave()
583 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; in genphy_c45_pma_baset1_read_master_slave()
584 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; in genphy_c45_pma_baset1_read_master_slave()
586 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; in genphy_c45_pma_baset1_read_master_slave()
587 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; in genphy_c45_pma_baset1_read_master_slave()
596 * @phydev: target phy_device struct
598 int genphy_c45_read_pma(struct phy_device *phydev) in genphy_c45_read_pma() argument
602 linkmode_zero(phydev->lp_advertising); in genphy_c45_read_pma()
604 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); in genphy_c45_read_pma()
610 phydev->speed = SPEED_10; in genphy_c45_read_pma()
613 phydev->speed = SPEED_100; in genphy_c45_read_pma()
616 phydev->speed = SPEED_1000; in genphy_c45_read_pma()
619 phydev->speed = SPEED_2500; in genphy_c45_read_pma()
622 phydev->speed = SPEED_5000; in genphy_c45_read_pma()
625 phydev->speed = SPEED_10000; in genphy_c45_read_pma()
628 phydev->speed = SPEED_UNKNOWN; in genphy_c45_read_pma()
632 phydev->duplex = DUPLEX_FULL; in genphy_c45_read_pma()
634 if (genphy_c45_baset1_able(phydev)) { in genphy_c45_read_pma()
635 val = genphy_c45_pma_baset1_read_master_slave(phydev); in genphy_c45_read_pma()
646 * @phydev: target phy_device struct
648 int genphy_c45_read_mdix(struct phy_device *phydev) in genphy_c45_read_mdix() argument
652 if (phydev->speed == SPEED_10000) { in genphy_c45_read_mdix()
653 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, in genphy_c45_read_mdix()
660 phydev->mdix = ETH_TP_MDI; in genphy_c45_read_mdix()
664 phydev->mdix = ETH_TP_MDI_X; in genphy_c45_read_mdix()
668 phydev->mdix = ETH_TP_MDI_INVALID; in genphy_c45_read_mdix()
679 * @phydev: target phy_device struct
682 int genphy_c45_write_eee_adv(struct phy_device *phydev, unsigned long *adv) in genphy_c45_write_eee_adv() argument
686 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { in genphy_c45_write_eee_adv()
692 val &= ~phydev->eee_broken_modes; in genphy_c45_write_eee_adv()
697 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, in genphy_c45_write_eee_adv()
710 phydev->supported_eee)) { in genphy_c45_write_eee_adv()
715 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, in genphy_c45_write_eee_adv()
730 * @phydev: target phy_device struct
733 int genphy_c45_read_eee_adv(struct phy_device *phydev, unsigned long *adv) in genphy_c45_read_eee_adv() argument
737 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { in genphy_c45_read_eee_adv()
741 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV); in genphy_c45_read_eee_adv()
749 phydev->supported_eee)) { in genphy_c45_read_eee_adv()
753 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10BT1_AN_CTRL); in genphy_c45_read_eee_adv()
765 * @phydev: target phy_device struct
768 static int genphy_c45_read_eee_lpa(struct phy_device *phydev, in genphy_c45_read_eee_lpa() argument
773 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { in genphy_c45_read_eee_lpa()
777 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); in genphy_c45_read_eee_lpa()
785 phydev->supported_eee)) { in genphy_c45_read_eee_lpa()
789 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10BT1_AN_STAT); in genphy_c45_read_eee_lpa()
801 * @phydev: target phy_device struct
803 static int genphy_c45_read_eee_cap1(struct phy_device *phydev) in genphy_c45_read_eee_cap1() argument
810 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); in genphy_c45_read_eee_cap1()
822 mii_eee_cap1_mod_linkmode_t(phydev->supported_eee, val); in genphy_c45_read_eee_cap1()
827 linkmode_and(phydev->supported_eee, phydev->supported_eee, in genphy_c45_read_eee_cap1()
828 phydev->supported); in genphy_c45_read_eee_cap1()
835 * @phydev: target phy_device struct
837 int genphy_c45_read_eee_abilities(struct phy_device *phydev) in genphy_c45_read_eee_abilities() argument
845 if (linkmode_intersects(phydev->supported, PHY_EEE_CAP1_FEATURES)) { in genphy_c45_read_eee_abilities()
846 val = genphy_c45_read_eee_cap1(phydev); in genphy_c45_read_eee_abilities()
852 phydev->supported)) { in genphy_c45_read_eee_abilities()
856 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10T1L_STAT); in genphy_c45_read_eee_abilities()
861 phydev->supported_eee, in genphy_c45_read_eee_abilities()
871 * @phydev: target phy_device struct
873 int genphy_c45_an_config_eee_aneg(struct phy_device *phydev) in genphy_c45_an_config_eee_aneg() argument
875 if (!phydev->eee_enabled) { in genphy_c45_an_config_eee_aneg()
878 return genphy_c45_write_eee_adv(phydev, adv); in genphy_c45_an_config_eee_aneg()
881 return genphy_c45_write_eee_adv(phydev, phydev->advertising_eee); in genphy_c45_an_config_eee_aneg()
886 * @phydev: target phy_device struct
890 int genphy_c45_pma_baset1_read_abilities(struct phy_device *phydev) in genphy_c45_pma_baset1_read_abilities() argument
894 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1); in genphy_c45_pma_baset1_read_abilities()
899 phydev->supported, in genphy_c45_pma_baset1_read_abilities()
903 phydev->supported, in genphy_c45_pma_baset1_read_abilities()
907 phydev->supported, in genphy_c45_pma_baset1_read_abilities()
910 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT); in genphy_c45_pma_baset1_read_abilities()
915 phydev->supported, in genphy_c45_pma_baset1_read_abilities()
924 * @phydev: target phy_device struct
929 int genphy_c45_pma_read_ext_abilities(struct phy_device *phydev) in genphy_c45_pma_read_ext_abilities() argument
933 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); in genphy_c45_pma_read_ext_abilities()
938 phydev->supported, in genphy_c45_pma_read_ext_abilities()
941 phydev->supported, in genphy_c45_pma_read_ext_abilities()
944 phydev->supported, in genphy_c45_pma_read_ext_abilities()
947 phydev->supported, in genphy_c45_pma_read_ext_abilities()
950 phydev->supported, in genphy_c45_pma_read_ext_abilities()
953 phydev->supported, in genphy_c45_pma_read_ext_abilities()
957 phydev->supported, in genphy_c45_pma_read_ext_abilities()
960 phydev->supported, in genphy_c45_pma_read_ext_abilities()
964 phydev->supported, in genphy_c45_pma_read_ext_abilities()
967 phydev->supported, in genphy_c45_pma_read_ext_abilities()
971 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, in genphy_c45_pma_read_ext_abilities()
977 phydev->supported, in genphy_c45_pma_read_ext_abilities()
981 phydev->supported, in genphy_c45_pma_read_ext_abilities()
986 val = genphy_c45_pma_baset1_read_abilities(phydev); in genphy_c45_pma_read_ext_abilities()
997 * @phydev: target phy_device struct
1006 int genphy_c45_pma_read_abilities(struct phy_device *phydev) in genphy_c45_pma_read_abilities() argument
1010 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); in genphy_c45_pma_read_abilities()
1011 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { in genphy_c45_pma_read_abilities()
1012 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in genphy_c45_pma_read_abilities()
1018 phydev->supported); in genphy_c45_pma_read_abilities()
1021 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2); in genphy_c45_pma_read_abilities()
1026 phydev->supported, in genphy_c45_pma_read_abilities()
1030 phydev->supported, in genphy_c45_pma_read_abilities()
1034 phydev->supported, in genphy_c45_pma_read_abilities()
1038 val = genphy_c45_pma_read_ext_abilities(phydev); in genphy_c45_pma_read_abilities()
1046 genphy_c45_read_eee_abilities(phydev); in genphy_c45_pma_read_abilities()
1058 int genphy_c45_baset1_read_status(struct phy_device *phydev) in genphy_c45_baset1_read_status() argument
1063 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; in genphy_c45_baset1_read_status()
1064 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; in genphy_c45_baset1_read_status()
1066 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L); in genphy_c45_baset1_read_status()
1070 cfg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M); in genphy_c45_baset1_read_status()
1076 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; in genphy_c45_baset1_read_status()
1078 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; in genphy_c45_baset1_read_status()
1081 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_PREFERRED; in genphy_c45_baset1_read_status()
1083 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_PREFERRED; in genphy_c45_baset1_read_status()
1092 * @phydev: target phy_device struct
1096 int genphy_c45_read_status(struct phy_device *phydev) in genphy_c45_read_status() argument
1100 ret = genphy_c45_read_link(phydev); in genphy_c45_read_status()
1104 phydev->speed = SPEED_UNKNOWN; in genphy_c45_read_status()
1105 phydev->duplex = DUPLEX_UNKNOWN; in genphy_c45_read_status()
1106 phydev->pause = 0; in genphy_c45_read_status()
1107 phydev->asym_pause = 0; in genphy_c45_read_status()
1109 if (phydev->autoneg == AUTONEG_ENABLE) { in genphy_c45_read_status()
1110 ret = genphy_c45_read_lpa(phydev); in genphy_c45_read_status()
1114 if (genphy_c45_baset1_able(phydev)) { in genphy_c45_read_status()
1115 ret = genphy_c45_baset1_read_status(phydev); in genphy_c45_read_status()
1120 phy_resolve_aneg_linkmode(phydev); in genphy_c45_read_status()
1122 ret = genphy_c45_read_pma(phydev); in genphy_c45_read_status()
1131 * @phydev: target phy_device struct
1137 int genphy_c45_config_aneg(struct phy_device *phydev) in genphy_c45_config_aneg() argument
1142 if (phydev->autoneg == AUTONEG_DISABLE) in genphy_c45_config_aneg()
1143 return genphy_c45_pma_setup_forced(phydev); in genphy_c45_config_aneg()
1145 ret = genphy_c45_an_config_aneg(phydev); in genphy_c45_config_aneg()
1151 return genphy_c45_check_and_restart_aneg(phydev, changed); in genphy_c45_config_aneg()
1157 int gen10g_config_aneg(struct phy_device *phydev) in gen10g_config_aneg() argument
1163 int genphy_c45_loopback(struct phy_device *phydev, bool enable) in genphy_c45_loopback() argument
1165 return phy_modify_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, in genphy_c45_loopback()
1173 * @phydev: target phy_device struct
1181 int genphy_c45_fast_retrain(struct phy_device *phydev, bool enable) in genphy_c45_fast_retrain() argument
1186 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR, in genphy_c45_fast_retrain()
1189 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported)) { in genphy_c45_fast_retrain()
1190 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, in genphy_c45_fast_retrain()
1195 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_CTRL2, in genphy_c45_fast_retrain()
1201 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR, in genphy_c45_fast_retrain()
1208 * @phydev: target phy_device struct
1215 int genphy_c45_plca_get_cfg(struct phy_device *phydev, in genphy_c45_plca_get_cfg() argument
1220 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_IDVER); in genphy_c45_plca_get_cfg()
1229 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL0); in genphy_c45_plca_get_cfg()
1235 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL1); in genphy_c45_plca_get_cfg()
1242 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_TOTMR); in genphy_c45_plca_get_cfg()
1248 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_BURST); in genphy_c45_plca_get_cfg()
1261 * @phydev: target phy_device struct
1269 int genphy_c45_plca_set_cfg(struct phy_device *phydev, in genphy_c45_plca_set_cfg() argument
1281 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1296 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1313 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1321 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1336 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1353 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1362 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1376 * @phydev: target phy_device struct
1383 int genphy_c45_plca_get_status(struct phy_device *phydev, in genphy_c45_plca_get_status() argument
1388 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_STATUS); in genphy_c45_plca_get_status()
1399 * @phydev: target phy_device struct
1407 int genphy_c45_eee_is_active(struct phy_device *phydev, unsigned long *adv, in genphy_c45_eee_is_active() argument
1416 ret = genphy_c45_read_eee_adv(phydev, tmp_adv); in genphy_c45_eee_is_active()
1420 ret = genphy_c45_read_eee_lpa(phydev, tmp_lp); in genphy_c45_eee_is_active()
1427 eee_active = phy_check_valid(phydev->speed, phydev->duplex, in genphy_c45_eee_is_active()
1445 * @phydev: target phy_device struct
1451 int genphy_c45_ethtool_get_eee(struct phy_device *phydev, in genphy_c45_ethtool_get_eee() argument
1459 ret = genphy_c45_eee_is_active(phydev, adv, lp, &is_enabled); in genphy_c45_ethtool_get_eee()
1467 phydev->supported_eee)) in genphy_c45_ethtool_get_eee()
1475 …phydev_warn(phydev, "Not all supported or advertised EEE link modes were passed to the user space\… in genphy_c45_ethtool_get_eee()
1483 * @phydev: target phy_device struct
1492 int genphy_c45_ethtool_set_eee(struct phy_device *phydev, in genphy_c45_ethtool_set_eee() argument
1503 linkmode_andnot(adv, adv, phydev->supported_eee); in genphy_c45_ethtool_set_eee()
1505 phydev_warn(phydev, "At least some EEE link modes are not supported.\n"); in genphy_c45_ethtool_set_eee()
1509 ethtool_convert_legacy_u32_to_link_mode(phydev->advertising_eee, in genphy_c45_ethtool_set_eee()
1512 linkmode_copy(phydev->advertising_eee, in genphy_c45_ethtool_set_eee()
1513 phydev->supported_eee); in genphy_c45_ethtool_set_eee()
1516 phydev->eee_enabled = true; in genphy_c45_ethtool_set_eee()
1518 phydev->eee_enabled = false; in genphy_c45_ethtool_set_eee()
1521 ret = genphy_c45_an_config_eee_aneg(phydev); in genphy_c45_ethtool_set_eee()
1525 return phy_restart_aneg(phydev); in genphy_c45_ethtool_set_eee()