Lines Matching full:phydev
276 void (*counters_enable)(struct phy_device *phydev);
280 void (*ptp_init)(struct phy_device *phydev);
281 void (*ptp_enable)(struct phy_device *phydev, bool enable);
282 void (*nmi_handler)(struct phy_device *phydev,
287 struct nxp_c45_phy_data *nxp_c45_get_data(struct phy_device *phydev) in nxp_c45_get_data() argument
289 return phydev->drv->driver_data; in nxp_c45_get_data()
293 struct nxp_c45_regmap *nxp_c45_get_regmap(struct phy_device *phydev) in nxp_c45_get_regmap() argument
295 const struct nxp_c45_phy_data *phy_data = nxp_c45_get_data(phydev); in nxp_c45_get_regmap()
300 static int nxp_c45_read_reg_field(struct phy_device *phydev, in nxp_c45_read_reg_field() argument
307 phydev_err(phydev, "Trying to read a reg field of size 0.\n"); in nxp_c45_read_reg_field()
311 ret = phy_read_mmd(phydev, reg_field->devad, reg_field->reg); in nxp_c45_read_reg_field()
324 static int nxp_c45_write_reg_field(struct phy_device *phydev, in nxp_c45_write_reg_field() argument
332 phydev_err(phydev, "Trying to write a reg field of size 0.\n"); in nxp_c45_write_reg_field()
341 return phy_modify_mmd_changed(phydev, reg_field->devad, in nxp_c45_write_reg_field()
345 static int nxp_c45_set_reg_field(struct phy_device *phydev, in nxp_c45_set_reg_field() argument
349 phydev_err(phydev, "Trying to set a reg field of size different than 1.\n"); in nxp_c45_set_reg_field()
353 return nxp_c45_write_reg_field(phydev, reg_field, 1); in nxp_c45_set_reg_field()
356 static int nxp_c45_clear_reg_field(struct phy_device *phydev, in nxp_c45_clear_reg_field() argument
360 phydev_err(phydev, "Trying to set a reg field of size different than 1.\n"); in nxp_c45_clear_reg_field()
364 return nxp_c45_write_reg_field(phydev, reg_field, 0); in nxp_c45_clear_reg_field()
367 static bool nxp_c45_poll_txts(struct phy_device *phydev) in nxp_c45_poll_txts() argument
369 return phydev->irq <= 0; in nxp_c45_poll_txts()
377 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev); in _nxp_c45_ptp_gettimex64()
379 nxp_c45_set_reg_field(priv->phydev, ®map->ltc_read); in _nxp_c45_ptp_gettimex64()
380 ts->tv_nsec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in _nxp_c45_ptp_gettimex64()
382 ts->tv_nsec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in _nxp_c45_ptp_gettimex64()
384 ts->tv_sec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in _nxp_c45_ptp_gettimex64()
386 ts->tv_sec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in _nxp_c45_ptp_gettimex64()
409 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev); in _nxp_c45_ptp_settime64()
411 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_nsec_0, in _nxp_c45_ptp_settime64()
413 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_nsec_1, in _nxp_c45_ptp_settime64()
415 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_sec_0, in _nxp_c45_ptp_settime64()
417 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_sec_1, in _nxp_c45_ptp_settime64()
419 nxp_c45_set_reg_field(priv->phydev, ®map->ltc_write); in _nxp_c45_ptp_settime64()
439 const struct nxp_c45_phy_data *data = nxp_c45_get_data(priv->phydev); in nxp_c45_ptp_adjfine()
451 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_ptp_adjfine()
459 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_ptp_adjfine()
504 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev); in nxp_c45_get_extts()
506 extts->tv_nsec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_get_extts()
508 extts->tv_nsec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_get_extts()
510 extts->tv_sec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_get_extts()
512 extts->tv_sec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_get_extts()
514 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_get_extts()
520 static bool tja1120_extts_is_valid(struct phy_device *phydev) in tja1120_extts_is_valid() argument
525 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, in tja1120_extts_is_valid()
535 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev); in tja1120_get_extts()
536 struct phy_device *phydev = priv->phydev; in tja1120_get_extts() local
541 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, in tja1120_get_extts()
545 valid = tja1120_extts_is_valid(phydev); in tja1120_get_extts()
553 phy_write_mmd(phydev, MDIO_MMD_VEND1, in tja1120_get_extts()
555 valid = tja1120_extts_is_valid(phydev); in tja1120_get_extts()
568 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev); in nxp_c45_read_egress_ts()
569 struct phy_device *phydev = priv->phydev; in nxp_c45_read_egress_ts() local
572 nxp_c45_read_reg_field(phydev, ®map->domain_number); in nxp_c45_read_egress_ts()
574 nxp_c45_read_reg_field(phydev, ®map->msg_type); in nxp_c45_read_egress_ts()
576 nxp_c45_read_reg_field(phydev, ®map->sequence_id); in nxp_c45_read_egress_ts()
578 nxp_c45_read_reg_field(phydev, ®map->nsec_15_0); in nxp_c45_read_egress_ts()
580 nxp_c45_read_reg_field(phydev, ®map->nsec_29_16) << 16; in nxp_c45_read_egress_ts()
581 hwts->sec = nxp_c45_read_reg_field(phydev, ®map->sec_1_0); in nxp_c45_read_egress_ts()
582 hwts->sec |= nxp_c45_read_reg_field(phydev, ®map->sec_4_2) << 2; in nxp_c45_read_egress_ts()
592 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_EGR_RING_CTRL, in nxp_c45_get_hwtxts()
594 reg = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_EGR_RING_DATA_0); in nxp_c45_get_hwtxts()
605 static bool tja1120_egress_ts_is_valid(struct phy_device *phydev) in tja1120_egress_ts_is_valid() argument
610 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, TJA1120_EGRESS_TS_DATA_S); in tja1120_egress_ts_is_valid()
619 struct phy_device *phydev = priv->phydev; in tja1120_get_hwtxts() local
625 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, TJA1120_EGRESS_TS_END); in tja1120_get_hwtxts()
627 valid = tja1120_egress_ts_is_valid(phydev); in tja1120_get_hwtxts()
635 phy_write_mmd(phydev, MDIO_MMD_VEND1, in tja1120_get_hwtxts()
637 valid = tja1120_egress_ts_is_valid(phydev); in tja1120_get_hwtxts()
642 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, TJA1120_EGRESS_TS_DATA_S, in tja1120_get_hwtxts()
679 phydev_warn(priv->phydev, in nxp_c45_process_txts()
687 const struct nxp_c45_phy_data *data = nxp_c45_get_data(priv->phydev); in nxp_c45_do_aux_work()
688 bool poll_txts = nxp_c45_poll_txts(priv->phydev); in nxp_c45_do_aux_work()
739 struct phy_device *phydev = priv->phydev; in nxp_c45_gpio_config() local
741 phy_write_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_gpio_config()
748 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev); in nxp_c45_perout_enable()
749 struct phy_device *phydev = priv->phydev; in nxp_c45_perout_enable() local
760 nxp_c45_clear_reg_field(priv->phydev, in nxp_c45_perout_enable()
762 nxp_c45_clear_reg_field(priv->phydev, in nxp_c45_perout_enable()
775 phydev_warn(phydev, "The period can be set only to 1 second."); in nxp_c45_perout_enable()
781 …phydev_warn(phydev, "The start time is not configurable. Should be set to 0 seconds and 0 nanoseco… in nxp_c45_perout_enable()
787 phydev_warn(phydev, "The phase can be set only to 0 or 500000000 nanoseconds."); in nxp_c45_perout_enable()
792 nxp_c45_clear_reg_field(priv->phydev, in nxp_c45_perout_enable()
795 nxp_c45_set_reg_field(priv->phydev, in nxp_c45_perout_enable()
801 nxp_c45_set_reg_field(priv->phydev, ®map->pps_enable); in nxp_c45_perout_enable()
806 static void nxp_c45_set_rising_or_falling(struct phy_device *phydev, in nxp_c45_set_rising_or_falling() argument
810 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_set_rising_or_falling()
814 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_set_rising_or_falling()
818 static void nxp_c45_set_rising_and_falling(struct phy_device *phydev, in nxp_c45_set_rising_and_falling() argument
826 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_set_rising_and_falling()
830 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_set_rising_and_falling()
835 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_set_rising_and_falling()
839 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_set_rising_and_falling()
847 const struct nxp_c45_phy_data *data = nxp_c45_get_data(priv->phydev); in nxp_c45_extts_enable()
874 nxp_c45_set_rising_and_falling(priv->phydev, extts); in nxp_c45_extts_enable()
876 nxp_c45_set_rising_or_falling(priv->phydev, extts); in nxp_c45_extts_enable()
954 &priv->phydev->mdio.dev); in nxp_c45_init_ptp_clock()
977 if (nxp_c45_poll_txts(priv->phydev)) in nxp_c45_txtstamp()
1013 struct phy_device *phydev = priv->phydev; in nxp_c45_hwtstamp() local
1019 data = nxp_c45_get_data(phydev); in nxp_c45_hwtstamp()
1037 phy_write_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_hwtstamp()
1040 data->ptp_enable(phydev, true); in nxp_c45_hwtstamp()
1042 phy_write_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_hwtstamp()
1045 data->ptp_enable(phydev, false); in nxp_c45_hwtstamp()
1048 if (nxp_c45_poll_txts(priv->phydev)) in nxp_c45_hwtstamp()
1052 nxp_c45_set_reg_field(phydev, &data->regmap->irq_egr_ts_en); in nxp_c45_hwtstamp()
1054 nxp_c45_clear_reg_field(phydev, &data->regmap->irq_egr_ts_en); in nxp_c45_hwtstamp()
1124 static int nxp_c45_get_sset_count(struct phy_device *phydev) in nxp_c45_get_sset_count() argument
1126 const struct nxp_c45_phy_data *phy_data = nxp_c45_get_data(phydev); in nxp_c45_get_sset_count()
1131 static void nxp_c45_get_strings(struct phy_device *phydev, u8 *data) in nxp_c45_get_strings() argument
1133 const struct nxp_c45_phy_data *phy_data = nxp_c45_get_data(phydev); in nxp_c45_get_strings()
1134 size_t count = nxp_c45_get_sset_count(phydev); in nxp_c45_get_strings()
1150 static void nxp_c45_get_stats(struct phy_device *phydev, in nxp_c45_get_stats() argument
1153 const struct nxp_c45_phy_data *phy_data = nxp_c45_get_data(phydev); in nxp_c45_get_stats()
1154 size_t count = nxp_c45_get_sset_count(phydev); in nxp_c45_get_stats()
1168 ret = nxp_c45_read_reg_field(phydev, reg_field); in nxp_c45_get_stats()
1176 static int nxp_c45_config_enable(struct phy_device *phydev) in nxp_c45_config_enable() argument
1178 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL, in nxp_c45_config_enable()
1183 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_CONTROL, in nxp_c45_config_enable()
1185 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONTROL, in nxp_c45_config_enable()
1187 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_INFRA_CONTROL, in nxp_c45_config_enable()
1193 static int nxp_c45_start_op(struct phy_device *phydev) in nxp_c45_start_op() argument
1195 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONTROL, in nxp_c45_start_op()
1199 static int nxp_c45_config_intr(struct phy_device *phydev) in nxp_c45_config_intr() argument
1203 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in nxp_c45_config_intr()
1204 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_config_intr()
1209 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_config_intr()
1213 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_config_intr()
1218 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_config_intr()
1222 static int tja1103_config_intr(struct phy_device *phydev) in tja1103_config_intr() argument
1227 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_ALWAYS_ACCESSIBLE, in tja1103_config_intr()
1232 return nxp_c45_config_intr(phydev); in tja1103_config_intr()
1235 static int tja1120_config_intr(struct phy_device *phydev) in tja1120_config_intr() argument
1239 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) in tja1120_config_intr()
1240 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1120_config_intr()
1244 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1120_config_intr()
1250 return nxp_c45_config_intr(phydev); in tja1120_config_intr()
1253 static irqreturn_t nxp_c45_handle_interrupt(struct phy_device *phydev) in nxp_c45_handle_interrupt() argument
1255 const struct nxp_c45_phy_data *data = nxp_c45_get_data(phydev); in nxp_c45_handle_interrupt()
1256 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_handle_interrupt()
1261 irq = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_IRQ_STATUS); in nxp_c45_handle_interrupt()
1263 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_IRQ_ACK, in nxp_c45_handle_interrupt()
1265 phy_trigger_machine(phydev); in nxp_c45_handle_interrupt()
1269 irq = nxp_c45_read_reg_field(phydev, &data->regmap->irq_egr_ts_status); in nxp_c45_handle_interrupt()
1276 phy_write_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_handle_interrupt()
1284 data->nmi_handler(phydev, &ret); in nxp_c45_handle_interrupt()
1285 nxp_c45_handle_macsec_interrupt(phydev, &ret); in nxp_c45_handle_interrupt()
1290 static int nxp_c45_soft_reset(struct phy_device *phydev) in nxp_c45_soft_reset() argument
1294 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL, in nxp_c45_soft_reset()
1299 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, in nxp_c45_soft_reset()
1305 static int nxp_c45_cable_test_start(struct phy_device *phydev) in nxp_c45_cable_test_start() argument
1307 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(phydev); in nxp_c45_cable_test_start()
1309 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_cable_test_start()
1311 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, regmap->cable_test, in nxp_c45_cable_test_start()
1315 static int nxp_c45_cable_test_get_status(struct phy_device *phydev, in nxp_c45_cable_test_get_status() argument
1318 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(phydev); in nxp_c45_cable_test_get_status()
1322 ret = nxp_c45_read_reg_field(phydev, ®map->cable_test_valid); in nxp_c45_cable_test_get_status()
1329 cable_test_result = nxp_c45_read_reg_field(phydev, in nxp_c45_cable_test_get_status()
1334 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A, in nxp_c45_cable_test_get_status()
1338 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A, in nxp_c45_cable_test_get_status()
1342 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A, in nxp_c45_cable_test_get_status()
1346 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A, in nxp_c45_cable_test_get_status()
1350 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, regmap->cable_test, in nxp_c45_cable_test_get_status()
1352 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_cable_test_get_status()
1355 return nxp_c45_start_op(phydev); in nxp_c45_cable_test_get_status()
1358 static int nxp_c45_get_sqi(struct phy_device *phydev) in nxp_c45_get_sqi() argument
1362 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_SIGNAL_QUALITY); in nxp_c45_get_sqi()
1371 static void tja1120_link_change_notify(struct phy_device *phydev) in tja1120_link_change_notify() argument
1376 if (phydev->state == PHY_NOLINK) { in tja1120_link_change_notify()
1377 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1120_link_change_notify()
1379 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1120_link_change_notify()
1384 static int nxp_c45_get_sqi_max(struct phy_device *phydev) in nxp_c45_get_sqi_max() argument
1389 static int nxp_c45_check_delay(struct phy_device *phydev, u32 delay) in nxp_c45_check_delay() argument
1392 phydev_err(phydev, "delay value smaller than %u\n", MIN_ID_PS); in nxp_c45_check_delay()
1397 phydev_err(phydev, "delay value higher than %u\n", MAX_ID_PS); in nxp_c45_check_delay()
1404 static void nxp_c45_counters_enable(struct phy_device *phydev) in nxp_c45_counters_enable() argument
1406 const struct nxp_c45_phy_data *data = nxp_c45_get_data(phydev); in nxp_c45_counters_enable()
1408 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_LINK_DROP_COUNTER, in nxp_c45_counters_enable()
1411 data->counters_enable(phydev); in nxp_c45_counters_enable()
1414 static void nxp_c45_ptp_init(struct phy_device *phydev) in nxp_c45_ptp_init() argument
1416 const struct nxp_c45_phy_data *data = nxp_c45_get_data(phydev); in nxp_c45_ptp_init()
1418 phy_write_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_ptp_init()
1421 nxp_c45_clear_reg_field(phydev, &data->regmap->ltc_lock_ctrl); in nxp_c45_ptp_init()
1423 data->ptp_init(phydev); in nxp_c45_ptp_init()
1437 static void nxp_c45_disable_delays(struct phy_device *phydev) in nxp_c45_disable_delays() argument
1439 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, ID_ENABLE); in nxp_c45_disable_delays()
1440 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, ID_ENABLE); in nxp_c45_disable_delays()
1443 static void nxp_c45_set_delays(struct phy_device *phydev) in nxp_c45_set_delays() argument
1445 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_set_delays()
1450 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in nxp_c45_set_delays()
1451 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { in nxp_c45_set_delays()
1453 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, in nxp_c45_set_delays()
1456 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, in nxp_c45_set_delays()
1460 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in nxp_c45_set_delays()
1461 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { in nxp_c45_set_delays()
1463 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, in nxp_c45_set_delays()
1466 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, in nxp_c45_set_delays()
1471 static int nxp_c45_get_delays(struct phy_device *phydev) in nxp_c45_get_delays() argument
1473 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_get_delays()
1476 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in nxp_c45_get_delays()
1477 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { in nxp_c45_get_delays()
1478 ret = device_property_read_u32(&phydev->mdio.dev, in nxp_c45_get_delays()
1484 ret = nxp_c45_check_delay(phydev, priv->tx_delay); in nxp_c45_get_delays()
1486 phydev_err(phydev, in nxp_c45_get_delays()
1492 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in nxp_c45_get_delays()
1493 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { in nxp_c45_get_delays()
1494 ret = device_property_read_u32(&phydev->mdio.dev, in nxp_c45_get_delays()
1500 ret = nxp_c45_check_delay(phydev, priv->rx_delay); in nxp_c45_get_delays()
1502 phydev_err(phydev, in nxp_c45_get_delays()
1511 static int nxp_c45_set_phy_mode(struct phy_device *phydev) in nxp_c45_set_phy_mode() argument
1515 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_ABILITIES); in nxp_c45_set_phy_mode()
1516 phydev_dbg(phydev, "Clause 45 managed PHY abilities 0x%x\n", ret); in nxp_c45_set_phy_mode()
1518 switch (phydev->interface) { in nxp_c45_set_phy_mode()
1521 phydev_err(phydev, "rgmii mode not supported\n"); in nxp_c45_set_phy_mode()
1524 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1526 nxp_c45_disable_delays(phydev); in nxp_c45_set_phy_mode()
1532 phydev_err(phydev, "rgmii-id, rgmii-txid, rgmii-rxid modes are not supported\n"); in nxp_c45_set_phy_mode()
1535 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1537 ret = nxp_c45_get_delays(phydev); in nxp_c45_set_phy_mode()
1541 nxp_c45_set_delays(phydev); in nxp_c45_set_phy_mode()
1545 phydev_err(phydev, "mii mode not supported\n"); in nxp_c45_set_phy_mode()
1548 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1553 phydev_err(phydev, "rev-mii mode not supported\n"); in nxp_c45_set_phy_mode()
1556 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1561 phydev_err(phydev, "rmii mode not supported\n"); in nxp_c45_set_phy_mode()
1564 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1569 phydev_err(phydev, "sgmii mode not supported\n"); in nxp_c45_set_phy_mode()
1572 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1584 static int nxp_c45_config_init(struct phy_device *phydev) in nxp_c45_config_init() argument
1588 ret = nxp_c45_config_enable(phydev); in nxp_c45_config_init()
1590 phydev_err(phydev, "Failed to enable config\n"); in nxp_c45_config_init()
1597 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 1); in nxp_c45_config_init()
1598 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 2); in nxp_c45_config_init()
1600 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONFIG, in nxp_c45_config_init()
1603 ret = nxp_c45_set_phy_mode(phydev); in nxp_c45_config_init()
1607 phydev->autoneg = AUTONEG_DISABLE; in nxp_c45_config_init()
1609 nxp_c45_counters_enable(phydev); in nxp_c45_config_init()
1610 nxp_c45_ptp_init(phydev); in nxp_c45_config_init()
1611 ret = nxp_c45_macsec_config_init(phydev); in nxp_c45_config_init()
1615 return nxp_c45_start_op(phydev); in nxp_c45_config_init()
1618 static int nxp_c45_get_features(struct phy_device *phydev) in nxp_c45_get_features() argument
1620 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, phydev->supported); in nxp_c45_get_features()
1621 linkmode_set_bit(ETHTOOL_LINK_MODE_MII_BIT, phydev->supported); in nxp_c45_get_features()
1623 return genphy_c45_pma_read_abilities(phydev); in nxp_c45_get_features()
1626 static int nxp_c45_probe(struct phy_device *phydev) in nxp_c45_probe() argument
1634 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); in nxp_c45_probe()
1641 priv->phydev = phydev; in nxp_c45_probe()
1643 phydev->priv = priv; in nxp_c45_probe()
1647 phy_abilities = phy_read_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_probe()
1651 phydev_dbg(phydev, "the phy does not support PTP"); in nxp_c45_probe()
1661 phydev->mii_ts = &priv->mii_ts; in nxp_c45_probe()
1664 phydev_dbg(phydev, "PTP support not enabled even if the phy supports it"); in nxp_c45_probe()
1670 phydev_info(phydev, "the phy does not support MACsec\n"); in nxp_c45_probe()
1675 ret = nxp_c45_macsec_probe(phydev); in nxp_c45_probe()
1676 phydev_dbg(phydev, "MACsec support enabled."); in nxp_c45_probe()
1678 phydev_dbg(phydev, "MACsec support not enabled even if the phy supports it"); in nxp_c45_probe()
1686 static void nxp_c45_remove(struct phy_device *phydev) in nxp_c45_remove() argument
1688 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_remove()
1695 nxp_c45_macsec_remove(phydev); in nxp_c45_remove()
1698 static void tja1103_counters_enable(struct phy_device *phydev) in tja1103_counters_enable() argument
1700 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RX_PREAMBLE_COUNT, in tja1103_counters_enable()
1702 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TX_PREAMBLE_COUNT, in tja1103_counters_enable()
1704 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RX_IPG_LENGTH, in tja1103_counters_enable()
1706 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TX_IPG_LENGTH, in tja1103_counters_enable()
1710 static void tja1103_ptp_init(struct phy_device *phydev) in tja1103_ptp_init() argument
1712 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RX_TS_INSRT_CTRL, in tja1103_ptp_init()
1714 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_FUNC_ENABLES, in tja1103_ptp_init()
1718 static void tja1103_ptp_enable(struct phy_device *phydev, bool enable) in tja1103_ptp_enable() argument
1721 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1103_ptp_enable()
1725 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1103_ptp_enable()
1730 static void tja1103_nmi_handler(struct phy_device *phydev, in tja1103_nmi_handler() argument
1735 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, in tja1103_nmi_handler()
1738 phy_write_mmd(phydev, MDIO_MMD_VEND1, in tja1103_nmi_handler()
1813 static void tja1120_counters_enable(struct phy_device *phydev) in tja1120_counters_enable() argument
1815 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_SYMBOL_ERROR_CNT_XTD, in tja1120_counters_enable()
1817 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_MONITOR_STATUS, in tja1120_counters_enable()
1819 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_MONITOR_CONFIG, in tja1120_counters_enable()
1823 static void tja1120_ptp_init(struct phy_device *phydev) in tja1120_ptp_init() argument
1825 phy_write_mmd(phydev, MDIO_MMD_VEND1, TJA1120_RX_TS_INSRT_CTRL, in tja1120_ptp_init()
1827 phy_write_mmd(phydev, MDIO_MMD_VEND1, TJA1120_VEND1_EXT_TS_MODE, in tja1120_ptp_init()
1829 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONFIG, in tja1120_ptp_init()
1833 static void tja1120_ptp_enable(struct phy_device *phydev, bool enable) in tja1120_ptp_enable() argument
1836 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1120_ptp_enable()
1840 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1120_ptp_enable()
1845 static void tja1120_nmi_handler(struct phy_device *phydev, in tja1120_nmi_handler() argument
1850 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, in tja1120_nmi_handler()
1853 phy_write_mmd(phydev, MDIO_MMD_VEND1, in tja1120_nmi_handler()