Lines Matching full:phydev
151 bool (*has_downshift)(struct phy_device *phydev);
153 int (*get_mactype)(struct phy_device *phydev);
154 int (*set_mactype)(struct phy_device *phydev, int mactype);
161 int (*hwmon_read_temp_reg)(struct phy_device *phydev);
176 static const struct mv3310_chip *to_mv3310_chip(struct phy_device *phydev) in to_mv3310_chip() argument
178 return phydev->drv->driver_data; in to_mv3310_chip()
193 static int mv3310_hwmon_read_temp_reg(struct phy_device *phydev) in mv3310_hwmon_read_temp_reg() argument
195 return phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP); in mv3310_hwmon_read_temp_reg()
198 static int mv2110_hwmon_read_temp_reg(struct phy_device *phydev) in mv2110_hwmon_read_temp_reg() argument
200 return phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_TEMP); in mv2110_hwmon_read_temp_reg()
206 struct phy_device *phydev = dev_get_drvdata(dev); in mv3310_hwmon_read() local
207 const struct mv3310_chip *chip = to_mv3310_chip(phydev); in mv3310_hwmon_read()
216 temp = chip->hwmon_read_temp_reg(phydev); in mv3310_hwmon_read()
264 static int mv3310_hwmon_config(struct phy_device *phydev, bool enable) in mv3310_hwmon_config() argument
269 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310) in mv3310_hwmon_config()
272 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP, in mv3310_hwmon_config()
279 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL, in mv3310_hwmon_config()
283 static int mv3310_hwmon_probe(struct phy_device *phydev) in mv3310_hwmon_probe() argument
285 struct device *dev = &phydev->mdio.dev; in mv3310_hwmon_probe()
286 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_hwmon_probe()
302 ret = mv3310_hwmon_config(phydev, true); in mv3310_hwmon_probe()
307 priv->hwmon_name, phydev, in mv3310_hwmon_probe()
313 static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable) in mv3310_hwmon_config() argument
318 static int mv3310_hwmon_probe(struct phy_device *phydev) in mv3310_hwmon_probe() argument
324 static int mv3310_power_down(struct phy_device *phydev) in mv3310_power_down() argument
326 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, in mv3310_power_down()
330 static int mv3310_power_up(struct phy_device *phydev) in mv3310_power_up() argument
332 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_power_up()
335 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, in mv3310_power_up()
345 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 || in mv3310_power_up()
349 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, in mv3310_power_up()
353 static int mv3310_reset(struct phy_device *phydev, u32 unit) in mv3310_reset() argument
357 err = phy_modify_mmd(phydev, MDIO_MMD_PCS, unit + MDIO_CTRL1, in mv3310_reset()
362 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PCS, in mv3310_reset()
368 static int mv3310_get_downshift(struct phy_device *phydev, u8 *ds) in mv3310_get_downshift() argument
370 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_get_downshift()
376 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1); in mv3310_get_downshift()
389 static int mv3310_set_downshift(struct phy_device *phydev, u8 ds) in mv3310_set_downshift() argument
391 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_set_downshift()
399 return phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1, in mv3310_set_downshift()
418 err = phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC2, in mv3310_set_downshift()
428 return phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1, in mv3310_set_downshift()
433 static int mv3310_get_edpd(struct phy_device *phydev, u16 *edpd) in mv3310_get_edpd() argument
437 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1); in mv3310_get_edpd()
455 static int mv3310_set_edpd(struct phy_device *phydev, u16 edpd) in mv3310_set_edpd() argument
478 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1, in mv3310_set_edpd()
481 err = mv3310_reset(phydev, MV_PCS_BASE_T); in mv3310_set_edpd()
488 struct phy_device *phydev = upstream; in mv3310_sfp_insert() local
493 sfp_parse_support(phydev->sfp_bus, id, support, interfaces); in mv3310_sfp_insert()
494 iface = sfp_select_interface(phydev->sfp_bus, support); in mv3310_sfp_insert()
497 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n"); in mv3310_sfp_insert()
509 static int mv3310_probe(struct phy_device *phydev) in mv3310_probe() argument
511 const struct mv3310_chip *chip = to_mv3310_chip(phydev); in mv3310_probe()
516 if (!phydev->is_c45 || in mv3310_probe()
517 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask) in mv3310_probe()
520 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT); in mv3310_probe()
525 dev_warn(&phydev->mdio.dev, in mv3310_probe()
530 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); in mv3310_probe()
534 dev_set_drvdata(&phydev->mdio.dev, priv); in mv3310_probe()
536 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER0); in mv3310_probe()
542 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER1); in mv3310_probe()
548 phydev_info(phydev, "Firmware version %u.%u.%u.%u\n", in mv3310_probe()
553 priv->has_downshift = chip->has_downshift(phydev); in mv3310_probe()
556 ret = mv3310_power_down(phydev); in mv3310_probe()
560 ret = mv3310_hwmon_probe(phydev); in mv3310_probe()
566 return phy_sfp_probe(phydev, &mv3310_sfp_ops); in mv3310_probe()
569 static void mv3310_remove(struct phy_device *phydev) in mv3310_remove() argument
571 mv3310_hwmon_config(phydev, false); in mv3310_remove()
574 static int mv3310_suspend(struct phy_device *phydev) in mv3310_suspend() argument
576 return mv3310_power_down(phydev); in mv3310_suspend()
579 static int mv3310_resume(struct phy_device *phydev) in mv3310_resume() argument
583 ret = mv3310_power_up(phydev); in mv3310_resume()
587 return mv3310_hwmon_config(phydev, true); in mv3310_resume()
597 static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev) in mv3310_has_pma_ngbaset_quirk() argument
599 if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD)) in mv3310_has_pma_ngbaset_quirk()
603 return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & in mv3310_has_pma_ngbaset_quirk()
607 static int mv2110_get_mactype(struct phy_device *phydev) in mv2110_get_mactype() argument
611 mactype = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL); in mv2110_get_mactype()
618 static int mv2110_set_mactype(struct phy_device *phydev, int mactype) in mv2110_set_mactype() argument
623 err = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL, in mv2110_set_mactype()
630 err = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2, in mv2110_set_mactype()
636 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_AN, in mv2110_set_mactype()
644 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2, in mv2110_set_mactype()
661 static int mv3310_get_mactype(struct phy_device *phydev) in mv3310_get_mactype() argument
665 mactype = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL); in mv3310_get_mactype()
672 static int mv3310_set_mactype(struct phy_device *phydev, int mactype) in mv3310_set_mactype() argument
677 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, in mv3310_set_mactype()
683 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, in mv3310_set_mactype()
806 static void mv3310_fill_possible_interfaces(struct phy_device *phydev) in mv3310_fill_possible_interfaces() argument
808 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_fill_possible_interfaces()
809 unsigned long *possible = phydev->possible_interfaces; in mv3310_fill_possible_interfaces()
822 static int mv3310_config_init(struct phy_device *phydev) in mv3310_config_init() argument
824 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_config_init()
825 const struct mv3310_chip *chip = to_mv3310_chip(phydev); in mv3310_config_init()
829 if (!test_bit(phydev->interface, priv->supported_interfaces)) in mv3310_config_init()
832 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; in mv3310_config_init()
835 err = mv3310_power_up(phydev); in mv3310_config_init()
842 if (!phy_interface_empty(phydev->host_interfaces)) { in mv3310_config_init()
843 mactype = chip->select_mactype(phydev->host_interfaces); in mv3310_config_init()
845 phydev_info(phydev, "Changing MACTYPE to %i\n", in mv3310_config_init()
847 err = chip->set_mactype(phydev, mactype); in mv3310_config_init()
853 mactype = chip->get_mactype(phydev); in mv3310_config_init()
858 phydev_err(phydev, "MACTYPE configuration invalid\n"); in mv3310_config_init()
864 mv3310_fill_possible_interfaces(phydev); in mv3310_config_init()
867 err = mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS); in mv3310_config_init()
872 err = mv3310_set_downshift(phydev, DOWNSHIFT_DEV_DEFAULT_COUNT); in mv3310_config_init()
879 static int mv3310_get_features(struct phy_device *phydev) in mv3310_get_features() argument
883 ret = genphy_c45_pma_read_abilities(phydev); in mv3310_get_features()
887 if (mv3310_has_pma_ngbaset_quirk(phydev)) { in mv3310_get_features()
888 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, in mv3310_get_features()
894 phydev->supported, in mv3310_get_features()
898 phydev->supported, in mv3310_get_features()
905 static int mv3310_config_mdix(struct phy_device *phydev) in mv3310_config_mdix() argument
910 switch (phydev->mdix_ctrl) { in mv3310_config_mdix()
924 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1, in mv3310_config_mdix()
927 err = mv3310_reset(phydev, MV_PCS_BASE_T); in mv3310_config_mdix()
932 static int mv3310_config_aneg(struct phy_device *phydev) in mv3310_config_aneg() argument
938 ret = mv3310_config_mdix(phydev); in mv3310_config_aneg()
942 if (phydev->autoneg == AUTONEG_DISABLE) in mv3310_config_aneg()
943 return genphy_c45_pma_setup_forced(phydev); in mv3310_config_aneg()
945 ret = genphy_c45_an_config_aneg(phydev); in mv3310_config_aneg()
954 reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); in mv3310_config_aneg()
955 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000, in mv3310_config_aneg()
962 return genphy_c45_check_and_restart_aneg(phydev, changed); in mv3310_config_aneg()
965 static int mv3310_aneg_done(struct phy_device *phydev) in mv3310_aneg_done() argument
969 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); in mv3310_aneg_done()
976 return genphy_c45_aneg_done(phydev); in mv3310_aneg_done()
979 static void mv3310_update_interface(struct phy_device *phydev) in mv3310_update_interface() argument
981 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_update_interface()
983 if (!phydev->link) in mv3310_update_interface()
993 phydev->interface = priv->mactype->interface_10g; in mv3310_update_interface()
1000 * Florian suggests setting phydev->interface to communicate this to the in mv3310_update_interface()
1003 switch (phydev->speed) { in mv3310_update_interface()
1005 phydev->interface = priv->mactype->interface_10g; in mv3310_update_interface()
1008 phydev->interface = PHY_INTERFACE_MODE_5GBASER; in mv3310_update_interface()
1011 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; in mv3310_update_interface()
1016 phydev->interface = PHY_INTERFACE_MODE_SGMII; in mv3310_update_interface()
1024 static int mv3310_read_status_10gbaser(struct phy_device *phydev) in mv3310_read_status_10gbaser() argument
1026 phydev->link = 1; in mv3310_read_status_10gbaser()
1027 phydev->speed = SPEED_10000; in mv3310_read_status_10gbaser()
1028 phydev->duplex = DUPLEX_FULL; in mv3310_read_status_10gbaser()
1029 phydev->port = PORT_FIBRE; in mv3310_read_status_10gbaser()
1034 static int mv3310_read_status_copper(struct phy_device *phydev) in mv3310_read_status_copper() argument
1038 val = genphy_c45_read_link(phydev); in mv3310_read_status_copper()
1042 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in mv3310_read_status_copper()
1046 cssr1 = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSSR1); in mv3310_read_status_copper()
1052 phydev->link = 0; in mv3310_read_status_copper()
1063 phydev->speed = SPEED_10000; in mv3310_read_status_copper()
1067 phydev->speed = SPEED_5000; in mv3310_read_status_copper()
1071 phydev->speed = SPEED_2500; in mv3310_read_status_copper()
1075 phydev->speed = SPEED_1000; in mv3310_read_status_copper()
1079 phydev->speed = SPEED_100; in mv3310_read_status_copper()
1083 phydev->speed = SPEED_10; in mv3310_read_status_copper()
1087 phydev->duplex = cssr1 & MV_PCS_CSSR1_DUPLEX_FULL ? in mv3310_read_status_copper()
1089 phydev->port = PORT_TP; in mv3310_read_status_copper()
1090 phydev->mdix = cssr1 & MV_PCS_CSSR1_MDIX ? in mv3310_read_status_copper()
1094 val = genphy_c45_read_lpa(phydev); in mv3310_read_status_copper()
1099 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000); in mv3310_read_status_copper()
1103 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); in mv3310_read_status_copper()
1106 phy_resolve_aneg_pause(phydev); in mv3310_read_status_copper()
1112 static int mv3310_read_status(struct phy_device *phydev) in mv3310_read_status() argument
1116 phydev->speed = SPEED_UNKNOWN; in mv3310_read_status()
1117 phydev->duplex = DUPLEX_UNKNOWN; in mv3310_read_status()
1118 linkmode_zero(phydev->lp_advertising); in mv3310_read_status()
1119 phydev->link = 0; in mv3310_read_status()
1120 phydev->pause = 0; in mv3310_read_status()
1121 phydev->asym_pause = 0; in mv3310_read_status()
1122 phydev->mdix = ETH_TP_MDI_INVALID; in mv3310_read_status()
1124 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); in mv3310_read_status()
1129 err = mv3310_read_status_10gbaser(phydev); in mv3310_read_status()
1131 err = mv3310_read_status_copper(phydev); in mv3310_read_status()
1135 if (phydev->link) in mv3310_read_status()
1136 mv3310_update_interface(phydev); in mv3310_read_status()
1141 static int mv3310_get_tunable(struct phy_device *phydev, in mv3310_get_tunable() argument
1146 return mv3310_get_downshift(phydev, data); in mv3310_get_tunable()
1148 return mv3310_get_edpd(phydev, data); in mv3310_get_tunable()
1154 static int mv3310_set_tunable(struct phy_device *phydev, in mv3310_set_tunable() argument
1159 return mv3310_set_downshift(phydev, *(u8 *)data); in mv3310_set_tunable()
1161 return mv3310_set_edpd(phydev, *(u16 *)data); in mv3310_set_tunable()
1167 static bool mv3310_has_downshift(struct phy_device *phydev) in mv3310_has_downshift() argument
1169 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_has_downshift()
1271 static int mv3310_get_number_of_ports(struct phy_device *phydev) in mv3310_get_number_of_ports() argument
1275 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PORT_INFO); in mv3310_get_number_of_ports()
1285 static int mv3310_match_phy_device(struct phy_device *phydev) in mv3310_match_phy_device() argument
1287 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & in mv3310_match_phy_device()
1291 return mv3310_get_number_of_ports(phydev) == 1; in mv3310_match_phy_device()
1294 static int mv3340_match_phy_device(struct phy_device *phydev) in mv3340_match_phy_device() argument
1296 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & in mv3340_match_phy_device()
1300 return mv3310_get_number_of_ports(phydev) == 4; in mv3340_match_phy_device()
1303 static int mv211x_match_phy_device(struct phy_device *phydev, bool has_5g) in mv211x_match_phy_device() argument
1307 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & in mv211x_match_phy_device()
1311 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_SPEED); in mv211x_match_phy_device()
1318 static int mv2110_match_phy_device(struct phy_device *phydev) in mv2110_match_phy_device() argument
1320 return mv211x_match_phy_device(phydev, true); in mv2110_match_phy_device()
1323 static int mv2111_match_phy_device(struct phy_device *phydev) in mv2111_match_phy_device() argument
1325 return mv211x_match_phy_device(phydev, false); in mv2111_match_phy_device()
1328 static void mv3110_get_wol(struct phy_device *phydev, in mv3110_get_wol() argument
1336 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_WOL_CTRL); in mv3110_get_wol()
1344 static int mv3110_set_wol(struct phy_device *phydev, in mv3110_set_wol() argument
1351 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
1358 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
1360 ((phydev->attached_dev->dev_addr[5] << 8) | in mv3110_set_wol()
1361 phydev->attached_dev->dev_addr[4])); in mv3110_set_wol()
1365 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
1367 ((phydev->attached_dev->dev_addr[3] << 8) | in mv3110_set_wol()
1368 phydev->attached_dev->dev_addr[2])); in mv3110_set_wol()
1372 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
1374 ((phydev->attached_dev->dev_addr[1] << 8) | in mv3110_set_wol()
1375 phydev->attached_dev->dev_addr[0])); in mv3110_set_wol()
1380 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
1388 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
1397 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()