1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2015 - 2023 Beijing WangXun Technology Co., Ltd. */
4 #include <linux/pcs/pcs-xpcs.h>
6 #include "pcs-xpcs.h"
12 #define TXGBE_TX_GENCTL1_VBOOST_EN0	BIT(4)
14 #define TXGBE_TX_GEN_CTL2_TX0_WIDTH(v)	FIELD_PREP(GENMASK(9, 8), v)  argument
16 #define TXGBE_TX_RATE_CTL_TX0_RATE(v)	FIELD_PREP(GENMASK(2, 0), v)  argument
18 #define TXGBE_RX_GEN_CTL2_RX0_WIDTH(v)	FIELD_PREP(GENMASK(9, 8), v)  argument
22 #define TXGBE_RX_RATE_CTL_RX0_RATE(v)	FIELD_PREP(GENMASK(1, 0), v)  argument
26 #define TXGBE_RX_EQ_CTL0_VGA1_GAIN(v)	FIELD_PREP(GENMASK(15, 12), v)  argument
27 #define TXGBE_RX_EQ_CTL0_VGA2_GAIN(v)	FIELD_PREP(GENMASK(11, 8), v)  argument
28 #define TXGBE_RX_EQ_CTL0_CTLE_POLE(v)	FIELD_PREP(GENMASK(7, 5), v)  argument
29 #define TXGBE_RX_EQ_CTL0_CTLE_BOOST(v)	FIELD_PREP(GENMASK(4, 0), v)  argument
31 #define TXGBE_RX_EQ_CTL4_CONT_OFF_CAN0	BIT(4)
32 #define TXGBE_RX_EQ_CTL4_CONT_ADAPT0	BIT(0)
34 #define TXGBE_DFE_EN_0			BIT(4)
35 #define TXGBE_AFE_EN_0			BIT(0)
39 #define TXGBE_MPLLA_CTL2_DIV16P5_CLK_EN	BIT(10)
40 #define TXGBE_MPLLA_CTL2_DIV10_CLK_EN	BIT(9)
43 #define TXGBE_MISC_CTL0_PLL		BIT(15)
44 #define TXGBE_MISC_CTL0_CR_PARA_SEL	BIT(14)
45 #define TXGBE_MISC_CTL0_RX_VREF(v)	FIELD_PREP(GENMASK(12, 8), v)  argument
131 	/* Wait xpcs power-up good */  in txgbe_pcs_poll_power_up()
137 		dev_err(&xpcs->mdiodev->dev, "xpcs power-up timeout\n");  in txgbe_pcs_poll_power_up()
153 		dev_err(&xpcs->mdiodev->dev, "xpcs pma initialization timeout\n");  in txgbe_pma_init_done()
162 	/* When txgbe do LAN reset, PCS will change to default 10GBASE-R mode */  in txgbe_xpcs_mode_quirk()
166 	     xpcs->interface != PHY_INTERFACE_MODE_10GBASER) ||  in txgbe_xpcs_mode_quirk()
167 	    xpcs->interface == PHY_INTERFACE_MODE_SGMII)  in txgbe_xpcs_mode_quirk()
186 	if (xpcs->interface == interface && !txgbe_xpcs_mode_quirk(xpcs))  in txgbe_xpcs_switch_mode()
189 	xpcs->interface = interface;  in txgbe_xpcs_switch_mode()