1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
35 /* MDIO clock source frequency is fixed to 100M */
48 	struct ipq4019_mdio_data *priv = bus->priv;  in ipq4019_mdio_wait_busy()
51 	return readl_poll_timeout(priv->membase + MDIO_CMD_REG, busy,  in ipq4019_mdio_wait_busy()
59 	struct ipq4019_mdio_data *priv = bus->priv;  in ipq4019_mdio_read_c45()
64 		return -ETIMEDOUT;  in ipq4019_mdio_read_c45()
66 	data = readl(priv->membase + MDIO_MODE_REG);  in ipq4019_mdio_read_c45()
70 	writel(data, priv->membase + MDIO_MODE_REG);  in ipq4019_mdio_read_c45()
73 	writel((mii_id << 8) | mmd, priv->membase + MDIO_ADDR_REG);  in ipq4019_mdio_read_c45()
76 	writel(reg, priv->membase + MDIO_DATA_WRITE_REG);  in ipq4019_mdio_read_c45()
81 	writel(cmd, priv->membase + MDIO_CMD_REG);  in ipq4019_mdio_read_c45()
85 		return -ETIMEDOUT;  in ipq4019_mdio_read_c45()
89 	writel(cmd, priv->membase + MDIO_CMD_REG);  in ipq4019_mdio_read_c45()
92 		return -ETIMEDOUT;  in ipq4019_mdio_read_c45()
95 	return readl(priv->membase + MDIO_DATA_READ_REG);  in ipq4019_mdio_read_c45()
100 	struct ipq4019_mdio_data *priv = bus->priv;  in ipq4019_mdio_read_c22()
105 		return -ETIMEDOUT;  in ipq4019_mdio_read_c22()
107 	data = readl(priv->membase + MDIO_MODE_REG);  in ipq4019_mdio_read_c22()
111 	writel(data, priv->membase + MDIO_MODE_REG);  in ipq4019_mdio_read_c22()
114 	writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG);  in ipq4019_mdio_read_c22()
119 	writel(cmd, priv->membase + MDIO_CMD_REG);  in ipq4019_mdio_read_c22()
123 		return -ETIMEDOUT;  in ipq4019_mdio_read_c22()
126 	return readl(priv->membase + MDIO_DATA_READ_REG);  in ipq4019_mdio_read_c22()
132 	struct ipq4019_mdio_data *priv = bus->priv;  in ipq4019_mdio_write_c45()
137 		return -ETIMEDOUT;  in ipq4019_mdio_write_c45()
139 	data = readl(priv->membase + MDIO_MODE_REG);  in ipq4019_mdio_write_c45()
143 	writel(data, priv->membase + MDIO_MODE_REG);  in ipq4019_mdio_write_c45()
146 	writel((mii_id << 8) | mmd, priv->membase + MDIO_ADDR_REG);  in ipq4019_mdio_write_c45()
149 	writel(reg, priv->membase + MDIO_DATA_WRITE_REG);  in ipq4019_mdio_write_c45()
153 	writel(cmd, priv->membase + MDIO_CMD_REG);  in ipq4019_mdio_write_c45()
156 		return -ETIMEDOUT;  in ipq4019_mdio_write_c45()
159 	writel(value, priv->membase + MDIO_DATA_WRITE_REG);  in ipq4019_mdio_write_c45()
162 	writel(cmd, priv->membase + MDIO_CMD_REG);  in ipq4019_mdio_write_c45()
166 		return -ETIMEDOUT;  in ipq4019_mdio_write_c45()
174 	struct ipq4019_mdio_data *priv = bus->priv;  in ipq4019_mdio_write_c22()
179 		return -ETIMEDOUT;  in ipq4019_mdio_write_c22()
182 	data = readl(priv->membase + MDIO_MODE_REG);  in ipq4019_mdio_write_c22()
186 	writel(data, priv->membase + MDIO_MODE_REG);  in ipq4019_mdio_write_c22()
189 	writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG);  in ipq4019_mdio_write_c22()
192 	writel(value, priv->membase + MDIO_DATA_WRITE_REG);  in ipq4019_mdio_write_c22()
197 	writel(cmd, priv->membase + MDIO_CMD_REG);  in ipq4019_mdio_write_c22()
201 		return -ETIMEDOUT;  in ipq4019_mdio_write_c22()
208 	struct ipq4019_mdio_data *priv = bus->priv;  in ipq_mdio_reset()
215 	if (priv->eth_ldo_rdy) {  in ipq_mdio_reset()
216 		val = readl(priv->eth_ldo_rdy);  in ipq_mdio_reset()
218 		writel(val, priv->eth_ldo_rdy);  in ipq_mdio_reset()
222 	/* Configure MDIO clock source frequency if clock is specified in the device tree */  in ipq_mdio_reset()
223 	ret = clk_set_rate(priv->mdio_clk, IPQ_MDIO_CLK_RATE);  in ipq_mdio_reset()
227 	ret = clk_prepare_enable(priv->mdio_clk);  in ipq_mdio_reset()
241 	bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*priv));  in ipq4019_mdio_probe()
243 		return -ENOMEM;  in ipq4019_mdio_probe()
245 	priv = bus->priv;  in ipq4019_mdio_probe()
247 	priv->membase = devm_platform_ioremap_resource(pdev, 0);  in ipq4019_mdio_probe()
248 	if (IS_ERR(priv->membase))  in ipq4019_mdio_probe()
249 		return PTR_ERR(priv->membase);  in ipq4019_mdio_probe()
251 	priv->mdio_clk = devm_clk_get_optional(&pdev->dev, "gcc_mdio_ahb_clk");  in ipq4019_mdio_probe()
252 	if (IS_ERR(priv->mdio_clk))  in ipq4019_mdio_probe()
253 		return PTR_ERR(priv->mdio_clk);  in ipq4019_mdio_probe()
259 		priv->eth_ldo_rdy = devm_ioremap_resource(&pdev->dev, res);  in ipq4019_mdio_probe()
261 	bus->name = "ipq4019_mdio";  in ipq4019_mdio_probe()
262 	bus->read = ipq4019_mdio_read_c22;  in ipq4019_mdio_probe()
263 	bus->write = ipq4019_mdio_write_c22;  in ipq4019_mdio_probe()
264 	bus->read_c45 = ipq4019_mdio_read_c45;  in ipq4019_mdio_probe()
265 	bus->write_c45 = ipq4019_mdio_write_c45;  in ipq4019_mdio_probe()
266 	bus->reset = ipq_mdio_reset;  in ipq4019_mdio_probe()
267 	bus->parent = &pdev->dev;  in ipq4019_mdio_probe()
268 	snprintf(bus->id, MII_BUS_ID_SIZE, "%s%d", pdev->name, pdev->id);  in ipq4019_mdio_probe()
270 	ret = of_mdiobus_register(bus, pdev->dev.of_node);  in ipq4019_mdio_probe()
272 		dev_err(&pdev->dev, "Cannot register MDIO bus!\n");  in ipq4019_mdio_probe()
289 	{ .compatible = "qcom,ipq4019-mdio" },
290 	{ .compatible = "qcom,ipq5018-mdio" },
299 		.name = "ipq4019-mdio",
306 MODULE_DESCRIPTION("ipq4019 MDIO interface driver");