Lines Matching +full:29 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0
20 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
21 [GSI_SNOC_BYPASS_DIS] = BIT(1),
22 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
23 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
24 /* Bit 4 reserved */
25 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
26 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
27 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
28 [GSI_MULTI_INORDER_WR_DIS] = BIT(8),
29 [GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9),
30 [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
31 [GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11),
32 [GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12),
33 [GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13),
34 [GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14),
35 [GSI_MULTI_AXI_MASTERS_DIS] = BIT(15),
36 [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
37 [FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(17),
38 /* Bit 18 reserved */
39 [QMB_RAM_RD_CACHE_DISABLE] = BIT(19),
40 [GENQMB_AOOOWR] = BIT(20),
41 [IF_OUT_OF_BUF_STOP_RESET_MASK_EN] = BIT(21),
43 /* Bits 28-29 reserved */
44 [GEN_QMB_1_DYNAMIC_ASIZE] = BIT(30),
45 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
51 [CLKON_RX] = BIT(0),
52 [CLKON_PROC] = BIT(1),
53 [TX_WRAPPER] = BIT(2),
54 [CLKON_MISC] = BIT(3),
55 [RAM_ARB] = BIT(4),
56 [FTCH_HPS] = BIT(5),
57 [FTCH_DPS] = BIT(6),
58 [CLKON_HPS] = BIT(7),
59 [CLKON_DPS] = BIT(8),
60 [RX_HPS_CMDQS] = BIT(9),
61 [HPS_DPS_CMDQS] = BIT(10),
62 [DPS_TX_CMDQS] = BIT(11),
63 [RSRC_MNGR] = BIT(12),
64 [CTX_HANDLER] = BIT(13),
65 [ACK_MNGR] = BIT(14),
66 [D_DCPH] = BIT(15),
67 [H_DCPH] = BIT(16),
68 /* Bit 17 reserved */
69 [NTF_TX_CMDQS] = BIT(18),
70 [CLKON_TX_0] = BIT(19),
71 [CLKON_TX_1] = BIT(20),
72 [CLKON_FNR] = BIT(21),
73 [QSB2AXI_CMDQ_L] = BIT(22),
74 [AGGR_WRAPPER] = BIT(23),
75 [RAM_SLAVEWAY] = BIT(24),
76 [CLKON_QMB] = BIT(25),
77 [WEIGHT_ARB] = BIT(26),
78 [GSI_IF] = BIT(27),
79 [CLKON_GLOBAL] = BIT(28),
80 [GLOBAL_2X_CLK] = BIT(29),
81 [DPL_FIFO] = BIT(30),
82 [DRBIP] = BIT(31),
91 [ROUTE_DEF_HDR_TABLE] = BIT(26),
92 [ROUTE_DEF_RETAIN_HDR] = BIT(27),
93 [ROUTE_DIS] = BIT(28),
94 /* Bits 29-31 reserved */
109 /* Bits 8-31 reserved */
117 /* Bits 8-15 reserved */
124 /* Valid bits defined by ipa->available */
129 [ROUTER_CACHE] = BIT(0),
130 /* Bits 1-3 reserved */
131 [FILTER_CACHE] = BIT(4),
132 /* Bits 5-31 reserved */
139 /* Bits 18-31 reserved */
146 /* Bits 0-1 reserved */
149 [DMAW_SCND_OUTSD_PRED_EN] = BIT(10),
150 [DMAW_MAX_BEATS_256_DIS] = BIT(11),
151 [PA_MASK_EN] = BIT(12),
153 [DUAL_TX_ENABLE] = BIT(17),
154 [SSPND_PA_NO_START_STATE] = BIT(18),
155 /* Bit 19 reserved */
156 [HOLB_STICKY_DROP_EN] = BIT(20),
157 /* Bits 21-31 reserved */
164 [CONST_NON_IDLE_ENABLE] = BIT(16),
165 /* Bits 17-31 reserved */
172 /* Bits 5-6 reserved */
173 [DPL_TIMESTAMP_SEL] = BIT(7),
175 /* Bits 13-15 reserved */
177 /* Bits 21-31 reserved */
184 /* Bits 9-30 reserved */
185 [DIV_ENABLE] = BIT(31),
195 /* Bits 12-31 reserved */
202 /* Bits 6-7 reserved */
204 /* Bits 14-15 reserved */
206 /* Bits 22-23 reserved */
207 [Y_MAX_LIM] = GENMASK(29, 24),
208 /* Bits 30-31 reserved */
216 /* Bits 6-7 reserved */
218 /* Bits 14-15 reserved */
220 /* Bits 22-23 reserved */
221 [Y_MAX_LIM] = GENMASK(29, 24),
222 /* Bits 30-31 reserved */
230 /* Bits 6-7 reserved */
232 /* Bits 14-15 reserved */
234 /* Bits 22-23 reserved */
235 [Y_MAX_LIM] = GENMASK(29, 24),
236 /* Bits 30-31 reserved */
244 /* Bits 6-7 reserved */
246 /* Bits 14-15 reserved */
248 /* Bits 22-23 reserved */
249 [Y_MAX_LIM] = GENMASK(29, 24),
250 /* Bits 30-31 reserved */
258 /* Bits 6-7 reserved */
260 /* Bits 14-15 reserved */
262 /* Bits 22-23 reserved */
263 [Y_MAX_LIM] = GENMASK(29, 24),
264 /* Bits 30-31 reserved */
272 /* Bits 6-7 reserved */
274 /* Bits 14-15 reserved */
276 /* Bits 22-23 reserved */
277 [Y_MAX_LIM] = GENMASK(29, 24),
278 /* Bits 30-31 reserved */
286 /* Bits 6-7 reserved */
288 /* Bits 14-15 reserved */
290 /* Bits 22-23 reserved */
291 [Y_MAX_LIM] = GENMASK(29, 24),
292 /* Bits 30-31 reserved */
300 /* Bits 6-7 reserved */
302 /* Bits 14-15 reserved */
304 /* Bits 22-23 reserved */
305 [Y_MAX_LIM] = GENMASK(29, 24),
306 /* Bits 30-31 reserved */
312 /* Valid bits defined by ipa->available */
317 [FRAG_OFFLOAD_EN] = BIT(0),
320 /* Bit 7 reserved */
321 [CS_GEN_QMB_MASTER_SEL] = BIT(8),
322 /* Bits 9-31 reserved */
329 /* Bits 2-31 reserved */
336 [HDR_OFST_METADATA_VALID] = BIT(6),
339 [HDR_OFST_PKT_SIZE_VALID] = BIT(19),
341 /* Bit 26 reserved */
342 [HDR_LEN_INC_DEAGG_HDR] = BIT(27),
343 [HDR_LEN_MSB] = GENMASK(29, 28),
350 [HDR_ENDIANNESS] = BIT(0),
351 [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
352 [HDR_TOTAL_LEN_OR_PAD] = BIT(2),
353 [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3),
356 /* Bits 14-15 reserved */
360 [HDR_BYTES_TO_REMOVE_VALID] = BIT(22),
361 /* Bit 23 reserved */
372 [DCPH_ENABLE] = BIT(3),
375 [PIPE_REPLICATION_EN] = BIT(28),
376 [PAD_EN] = BIT(29),
377 [DRBIP_ACL_ENABLE] = BIT(30),
378 /* Bit 31 reserved */
387 /* Bit 11 reserved */
390 [SW_EOF_ACTIVE] = BIT(23),
391 [FORCE_CLOSE] = BIT(24),
392 /* Bit 25 reserved */
393 [HARD_BYTE_LIMIT_EN] = BIT(26),
394 [AGGR_GRAN_SEL] = BIT(27),
395 /* Bits 28-31 reserved */
401 [HOL_BLOCK_EN] = BIT(0),
402 /* Bits 1-31 reserved */
410 /* Bits 5-7 reserved */
412 /* Bits 10-31 reserved */
420 [SYSPIPE_ERR_DETECTION] = BIT(6),
421 [PACKET_OFFSET_VALID] = BIT(7),
423 [IGNORE_MIN_PKT_ERR] = BIT(14),
424 /* Bit 15 reserved */
432 /* Bits 3-31 reserved */
439 /* Bits 8-31 reserved */
445 [STATUS_EN] = BIT(0),
447 [STATUS_PKT_SUPPRESS] = BIT(9),
448 /* Bits 10-31 reserved */
454 [CACHE_MSK_SRC_ID] = BIT(0),
455 [CACHE_MSK_SRC_IP] = BIT(1),
456 [CACHE_MSK_DST_IP] = BIT(2),
457 [CACHE_MSK_SRC_PORT] = BIT(3),
458 [CACHE_MSK_DST_PORT] = BIT(4),
459 [CACHE_MSK_PROTOCOL] = BIT(5),
460 [CACHE_MSK_METADATA] = BIT(6),
461 /* Bits 7-31 reserved */
468 [CACHE_MSK_SRC_ID] = BIT(0),
469 [CACHE_MSK_SRC_IP] = BIT(1),
470 [CACHE_MSK_DST_IP] = BIT(2),
471 [CACHE_MSK_SRC_PORT] = BIT(3),
472 [CACHE_MSK_DST_PORT] = BIT(4),
473 [CACHE_MSK_PROTOCOL] = BIT(5),
474 [CACHE_MSK_METADATA] = BIT(6),
475 /* Bits 7-31 reserved */
491 [UC_INTR] = BIT(0),
492 /* Bits 1-31 reserved */
497 /* Valid bits defined by ipa->available */
502 /* Valid bits defined by ipa->available */
507 /* Valid bits defined by ipa->available */