Lines Matching +full:0 +full:- +full:31
1 // SPDX-License-Identifier: GPL-2.0
11 /* Bit 0 reserved */
30 /* Bits 22-31 reserved */
33 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
36 [CLKON_RX] = BIT(0),
67 /* Bit 31 reserved */
70 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
73 [ROUTE_DIS] = BIT(0),
78 /* Bits 22-23 reserved */
80 /* Bits 25-31 reserved */
83 REG_FIELDS(ROUTE, route, 0x00000048);
86 [MEM_SIZE] = GENMASK(15, 0),
87 [MEM_BADDR] = GENMASK(31, 16),
90 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
93 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
95 /* Bits 8-31 reserved */
98 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
101 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
103 /* Bits 8-15 reserved */
105 [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),
108 REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
111 [IPV6_ROUTER_HASH] = BIT(0),
112 /* Bits 1-3 reserved */
114 /* Bits 5-7 reserved */
116 /* Bits 9-11 reserved */
118 /* Bits 13-31 reserved */
121 REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148);
124 [IPV6_ROUTER_HASH] = BIT(0),
125 /* Bits 1-3 reserved */
127 /* Bits 5-7 reserved */
129 /* Bits 9-11 reserved */
131 /* Bits 13-31 reserved */
134 REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c);
136 /* Valid bits defined by ipa->available */
137 REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004);
140 [IPA_BASE_ADDR] = GENMASK(17, 0),
141 /* Bits 18-31 reserved */
145 REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
147 /* Valid bits defined by ipa->available */
148 REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
151 /* Bits 0-1 reserved */
159 /* Bits 18-31 reserved */
162 REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
165 [MAX_PIPES] = GENMASK(3, 0),
166 /* Bits 4-7 reserved */
168 /* Bits 13-15 reserved */
170 /* Bits 21-23 reserved */
172 /* Bits 28-31 reserved */
175 REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);
178 [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),
180 /* Bits 17-31 reserved */
183 REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240);
186 [DPL_TIMESTAMP_LSB] = GENMASK(4, 0),
187 /* Bits 5-6 reserved */
190 /* Bits 13-15 reserved */
192 /* Bits 21-31 reserved */
195 REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c);
198 [DIV_VALUE] = GENMASK(8, 0),
199 /* Bits 9-30 reserved */
200 [DIV_ENABLE] = BIT(31),
203 REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250);
206 [PULSE_GRAN_0] = GENMASK(2, 0),
211 REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254);
214 [X_MIN_LIM] = GENMASK(5, 0),
215 /* Bits 6-7 reserved */
217 /* Bits 14-15 reserved */
219 /* Bits 22-23 reserved */
221 /* Bits 30-31 reserved */
225 0x00000400, 0x0020);
228 [X_MIN_LIM] = GENMASK(5, 0),
229 /* Bits 6-7 reserved */
231 /* Bits 14-15 reserved */
233 /* Bits 22-23 reserved */
235 /* Bits 30-31 reserved */
239 0x00000404, 0x0020);
242 [X_MIN_LIM] = GENMASK(5, 0),
243 /* Bits 6-7 reserved */
245 /* Bits 14-15 reserved */
247 /* Bits 22-23 reserved */
249 /* Bits 30-31 reserved */
253 0x00000408, 0x0020);
256 [X_MIN_LIM] = GENMASK(5, 0),
257 /* Bits 6-7 reserved */
259 /* Bits 14-15 reserved */
261 /* Bits 22-23 reserved */
263 /* Bits 30-31 reserved */
267 0x00000500, 0x0020);
270 [X_MIN_LIM] = GENMASK(5, 0),
271 /* Bits 6-7 reserved */
273 /* Bits 14-15 reserved */
275 /* Bits 22-23 reserved */
277 /* Bits 30-31 reserved */
281 0x00000504, 0x0020);
284 [X_MIN_LIM] = GENMASK(5, 0),
285 /* Bits 6-7 reserved */
287 /* Bits 14-15 reserved */
289 /* Bits 22-23 reserved */
291 /* Bits 30-31 reserved */
295 0x00000508, 0x0020);
298 [FRAG_OFFLOAD_EN] = BIT(0),
303 /* Bits 9-31 reserved */
306 REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
309 [NAT_EN] = GENMASK(1, 0),
310 /* Bits 2-31 reserved */
313 REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
316 [HDR_LEN] = GENMASK(5, 0),
325 [HDR_OFST_METADATA_MSB] = GENMASK(31, 30),
328 REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
331 [HDR_ENDIANNESS] = BIT(0),
337 /* Bits 14-15 reserved */
341 /* Bits 22-31 reserved */
344 REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
347 0x00000818, 0x0070);
350 [ENDP_MODE] = GENMASK(2, 0),
353 /* Bits 9-11 reserved */
357 /* Bits 30-31 reserved */
360 REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
363 [AGGR_EN] = GENMASK(1, 0),
374 /* Bits 28-31 reserved */
377 REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
380 [HOL_BLOCK_EN] = BIT(0),
381 /* Bits 1-31 reserved */
385 0x0000082c, 0x0070);
388 [TIMER_LIMIT] = GENMASK(4, 0),
389 /* Bits 5-7 reserved */
391 /* Bits 9-31 reserved */
395 0x00000830, 0x0070);
398 [DEAGGR_HDR_LEN] = GENMASK(5, 0),
404 [MAX_PACKET_LEN] = GENMASK(31, 16),
407 REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
410 [ENDP_RSRC_GRP] = GENMASK(2, 0),
411 /* Bits 3-31 reserved */
414 REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070);
417 [SEQ_TYPE] = GENMASK(7, 0),
418 /* Bits 8-31 reserved */
421 REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
424 [STATUS_EN] = BIT(0),
426 /* Bits 6-8 reserved */
428 /* Bits 10-31 reserved */
431 REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
434 [FILTER_HASH_MSK_SRC_ID] = BIT(0),
441 [FILTER_HASH_MSK_ALL] = GENMASK(6, 0),
442 /* Bits 7-15 reserved */
451 /* Bits 23-31 reserved */
455 0x0000085c, 0x0070);
458 REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP);
461 REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP);
464 REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP);
467 [UC_INTR] = BIT(0),
468 /* Bits 1-31 reserved */
471 REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP);
473 /* Valid bits defined by ipa->available */
475 0x00003030 + 0x1000 * GSI_EE_AP, 0x0004);
477 /* Valid bits defined by ipa->available */
479 0x00003034 + 0x1000 * GSI_EE_AP, 0x0004);
481 /* Valid bits defined by ipa->available */
483 0x00003038 + 0x1000 * GSI_EE_AP, 0x0004);