Lines Matching +full:ipa +full:- +full:reg
1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2018-2023 Linaro Ltd.
13 #include "reg.h"
15 struct ipa;
18 * DOC: IPA Registers
20 * IPA registers are located within the "ipa-reg" address space defined by
24 * All IPA registers are 32 bits wide.
27 * instances of something. For example, each IPA endpoint has an set of
35 * Each version of IPA implements an array of ipa_reg structures indexed
37 * (for parameterized registers) a non-zero stride value. Not all versions
38 * of IPA define all registers. The offset for a register is returned by
50 * reg_decode(). In addition, for single-bit fields, reg_bit()
55 /* enum ipa_reg_id - IPA register IDs */
63 FILT_ROUT_HASH_EN, /* IPA v4.2 */
64 FILT_ROUT_HASH_FLUSH, /* Not IPA v4.2 nor IPA v5.0+ */
65 FILT_ROUT_CACHE_FLUSH, /* IPA v5.0+ */
67 IPA_BCR, /* Not IPA v4.5+ */
70 COUNTER_CFG, /* Not IPA v4.5+ */
71 IPA_TX_CFG, /* IPA v3.5+ */
72 FLAVOR_0, /* IPA v3.5+ */
73 IDLE_INDICATION_CFG, /* IPA v3.5+ */
74 QTIME_TIMESTAMP_CFG, /* IPA v4.5+ */
75 TIMERS_XO_CLK_DIV_CFG, /* IPA v4.5+ */
76 TIMERS_PULSE_GRAN_CFG, /* IPA v4.5+ */
79 SRC_RSRC_GRP_45_RSRC_TYPE, /* Not IPA v3.5+; IPA v4.5, IPA v5.0 */
80 SRC_RSRC_GRP_67_RSRC_TYPE, /* Not IPA v3.5+; IPA v5.0 */
83 DST_RSRC_GRP_45_RSRC_TYPE, /* Not IPA v3.5+; IPA v4.5, IPA v5.0 */
84 DST_RSRC_GRP_67_RSRC_TYPE, /* Not IPA v3.5+; IPA v5.0 */
85 ENDP_INIT_CTRL, /* Not IPA v4.2+ for TX, not IPA v4.0+ for RX */
99 ENDP_FILTER_ROUTER_HSH_CFG, /* Not IPA v4.2 */
100 ENDP_FILTER_CACHE_CFG, /* IPA v5.0+ */
101 ENDP_ROUTER_CACHE_CFG, /* IPA v5.0+ */
108 IRQ_SUSPEND_EN, /* IPA v3.1+ */
109 IRQ_SUSPEND_CLR, /* IPA v3.1+ */
115 COMP_CFG_ENABLE, /* Not IPA v4.0+ */
116 RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS, /* IPA v4.7+ */
120 IPA_DCMP_FAST_CLK_EN, /* Not IPA v4.5+ */
121 IPA_QMB_SELECT_CONS_EN, /* IPA v4.0+ */
122 IPA_QMB_SELECT_PROD_EN, /* IPA v4.0+ */
123 GSI_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */
124 GSI_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */
125 GEN_QMB_0_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */
126 GEN_QMB_1_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */
127 GEN_QMB_0_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */
128 GEN_QMB_1_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */
129 GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS, /* IPA v4.0+ */
130 GSI_SNOC_CNOC_LOOP_PROT_DISABLE, /* IPA v4.0+ */
131 GSI_MULTI_AXI_MASTERS_DIS, /* IPA v4.0+ */
132 IPA_QMB_SELECT_GLOBAL_EN, /* IPA v4.0+ */
133 QMB_RAM_RD_CACHE_DISABLE, /* IPA v4.9+ */
134 GENQMB_AOOOWR, /* IPA v4.9+ */
135 IF_OUT_OF_BUF_STOP_RESET_MASK_EN, /* IPA v4.9+ */
136 GEN_QMB_1_DYNAMIC_ASIZE, /* IPA v4.9+ */
137 GEN_QMB_0_DYNAMIC_ASIZE, /* IPA v4.9+ */
138 ATOMIC_FETCHER_ARB_LOCK_DIS, /* IPA v4.0+ */
139 FULL_FLUSH_WAIT_RS_CLOSURE_EN, /* IPA v4.5+ */
161 CLKON_DCMP, /* IPA v4.5+ */
162 NTF_TX_CMDQS, /* IPA v3.5+ */
163 CLKON_TX_0, /* IPA v3.5+ */
164 CLKON_TX_1, /* IPA v3.5+ */
165 CLKON_FNR, /* IPA v3.5.1+ */
166 QSB2AXI_CMDQ_L, /* IPA v4.0+ */
167 AGGR_WRAPPER, /* IPA v4.0+ */
168 RAM_SLAVEWAY, /* IPA v4.0+ */
169 CLKON_QMB, /* IPA v4.0+ */
170 WEIGHT_ARB, /* IPA v4.0+ */
171 GSI_IF, /* IPA v4.0+ */
172 CLKON_GLOBAL, /* IPA v4.0+ */
173 GLOBAL_2X_CLK, /* IPA v4.0+ */
174 DPL_FIFO, /* IPA v4.5+ */
175 DRBIP, /* IPA v4.7+ */
204 GEN_QMB_0_MAX_READS_BEATS, /* IPA v4.0+ */
205 GEN_QMB_1_MAX_READS_BEATS, /* IPA v4.0+ */
224 BCR_CMDQ_L_LACK_ONE_ENTRY = 0x0, /* Not IPA v4.2+ */
225 BCR_TX_NOT_USING_BRESP = 0x1, /* Not IPA v4.2+ */
226 BCR_TX_SUSPEND_IRQ_ASSERT_ONCE = 0x2, /* Not IPA v4.0+ */
227 BCR_SUSPEND_L2_IRQ = 0x3, /* Not IPA v4.2+ */
228 BCR_HOLB_DROP_L2_IRQ = 0x4, /* Not IPA v4.2+ */
229 BCR_DUAL_TX = 0x5, /* IPA v3.5+ */
230 BCR_ENABLE_FILTER_DATA_CACHE = 0x6, /* IPA v3.5+ */
231 BCR_NOTIF_PRIORITY_OVER_ZLT = 0x7, /* IPA v3.5+ */
232 BCR_FILTER_PREFETCH_EN = 0x8, /* IPA v3.5+ */
233 BCR_ROUTER_PREFETCH_EN = 0x9, /* IPA v3.5+ */
243 EOT_COAL_GRANULARITY, /* Not IPA v3.5+ */
249 TX0_PREFETCH_DISABLE, /* Not IPA v4.0+ */
250 TX1_PREFETCH_DISABLE, /* Not IPA v4.0+ */
251 PREFETCH_ALMOST_EMPTY_SIZE, /* Not IPA v4.0+ */
252 PREFETCH_ALMOST_EMPTY_SIZE_TX0, /* IPA v4.0+ */
253 DMAW_SCND_OUTSD_PRED_THRESHOLD, /* IPA v4.0+ */
254 DMAW_SCND_OUTSD_PRED_EN, /* IPA v4.0+ */
255 DMAW_MAX_BEATS_256_DIS, /* IPA v4.0+ */
256 PA_MASK_EN, /* IPA v4.0+ */
257 PREFETCH_ALMOST_EMPTY_SIZE_TX1, /* IPA v4.0+ */
258 DUAL_TX_ENABLE, /* IPA v4.5+ */
259 SSPND_PA_NO_START_STATE, /* IPA v4,2+, not IPA v4.5 */
260 SSPND_PA_NO_BQ_STATE, /* IPA v4.2 only */
261 HOLB_STICKY_DROP_EN, /* IPA v5.0+ */
280 DPL_TIMESTAMP_LSB, /* Not IPA v5.5+ */
281 DPL_TIMESTAMP_SEL, /* Not IPA v5.5+ */
322 ENDP_SUSPEND, /* Not IPA v4.0+ */
323 ENDP_DELAY, /* Not IPA v4.2+ */
332 PIPE_REPLICATE_EN, /* IPA v5.5+ */
335 /** enum ipa_cs_offload_en - ENDP_INIT_CFG register CS_OFFLOAD_EN field value */
338 IPA_CS_OFFLOAD_UL /* TX */ = 0x1, /* Not IPA v4.5+ */
339 IPA_CS_OFFLOAD_DL /* RX */ = 0x2, /* Not IPA v4.5+ */
340 IPA_CS_OFFLOAD_INLINE /* TX and RX */ = 0x1, /* IPA v4.5+ */
348 /** enum ipa_nat_type - ENDP_INIT_NAT register NAT_EN field value */
363 HDR_A5_MUX, /* Not IPA v4.9+ */
365 HDR_METADATA_REG_VALID, /* Not IPA v4.5+ */
366 HDR_LEN_MSB, /* IPA v4.5+ */
367 HDR_OFST_METADATA_MSB, /* IPA v4.5+ */
378 HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB, /* IPA v4.5+ */
379 HDR_OFST_PKT_SIZE_MSB, /* IPA v4.5+ */
380 HDR_ADDITIONAL_CONST_LEN_MSB, /* IPA v4.5+ */
381 HDR_BYTES_TO_REMOVE_VALID, /* IPA v5.0+ */
382 HDR_BYTES_TO_REMOVE, /* IPA v5.0+ */
388 DCPH_ENABLE, /* IPA v4.5+ */
391 PIPE_REPLICATION_EN, /* Not IPA v5.5+ */
393 HDR_FTCH_DISABLE, /* IPA v4.5+ */
394 DRBIP_ACL_ENABLE, /* IPA v4.9+ */
397 /** enum ipa_mode - ENDP_INIT_MODE register MODE field value */
416 AGGR_COAL_L2, /* IPA v5.5+ */
419 /** enum ipa_aggr_en - ENDP_INIT_AGGR register AGGR_EN field value */
426 /** enum ipa_aggr_type - ENDP_INIT_AGGR register AGGR_TYPE field value */
444 TIMER_BASE_VALUE, /* Not IPA v4.5+ */
445 TIMER_SCALE, /* IPA v4.2 only */
446 TIMER_LIMIT, /* IPA v4.5+ */
447 TIMER_GRAN_SEL, /* IPA v4.5+ */
468 SEQ_REP_TYPE, /* Not IPA v4.5+ */
472 * enum ipa_seq_type - HPS and DPS sequencer type
481 * The low-order byte of the sequencer type register defines the number of
482 * passes a packet takes through the IPA pipeline. The last pass through can
501 * enum ipa_seq_rep_type - replicated packet sequencer type
517 STATUS_LOCATION, /* Not IPA v4.5+ */
518 STATUS_PKT_SUPPRESS, /* IPA v4.0+ */
555 * enum ipa_irq_id - Bit positions representing type of IPA IRQ
594 IPA_IRQ_BAD_SNOC_ACCESS = 0x0, /* Not IPA v5.5+ */
595 IPA_IRQ_EOT_COAL = 0x1, /* Not IPA v3.5+ */
603 IPA_IRQ_RX_ERR = 0x9, /* Not IPA v5.5+ */
604 IPA_IRQ_DEAGGR_ERR = 0xa, /* Not IPA v5.5+ */
605 IPA_IRQ_TX_ERR = 0xb, /* Not IPA v5.5+ */
606 IPA_IRQ_STEP_MODE = 0xc, /* Not IPA v5.5+ */
607 IPA_IRQ_PROC_ERR = 0xd, /* Not IPA v5.5+ */
616 IPA_IRQ_DCMP = 0x16, /* Not IPA v4.5+ */
620 IPA_IRQ_TLV_LEN_MIN_DSM = 0x1a, /* IPA v4.5-v5.2 */
621 IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN = 0x1b, /* IPA v4.9-v5.2 */
622 IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN = 0x1c, /* IPA v4.9-v5.2 */
623 IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN = 0x1d, /* IPA v4.9-v5.2 */
624 IPA_IRQ_ERROR_NON_FATAL = 0x1e, /* IPA v5.5+ */
625 IPA_IRQ_ERROR_FATAL = 0x1f, /* IPA v5.5+ */
644 const struct reg *ipa_reg(struct ipa *ipa, enum ipa_reg_id reg_id);
646 int ipa_reg_init(struct ipa *ipa);
647 void ipa_reg_exit(struct ipa *ipa);