Lines Matching +full:ipa +full:- +full:reg
1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2018-2023 Linaro Ltd.
19 #include "reg.h"
28 * DOC: The IPA Generic Software Interface
30 * The generic software interface (GSI) is an integral component of the IPA,
31 * providing a well-defined communication layer between the AP subsystem
32 * and the IPA core. The modem uses the GSI layer as well.
34 * -------- ---------
36 * | AP +<---. .----+ Modem |
37 * | +--. | | .->+ |
39 * -------- | | | | ---------
41 * --+-+---+-+--
43 * |-----------|
45 * | IPA |
47 * -------------
50 * (EEs), which are independent operating environments that use the IPA for
54 * of data to or from the IPA. A channel is implemented as a ring buffer,
55 * with a DRAM-resident array of "transfer elements" (TREs) available to
56 * describe transfers to or from other EEs through the IPA. A transfer
57 * element can also contain an immediate command, requesting the IPA perform
60 * Each TRE refers to a block of data--also located in DRAM. After writing
61 * one or more TREs to a channel, the writer (either the IPA or an EE) writes
67 * the IPA to an EE. The IPA notifies an EE (such as the AP) about channel
85 * Note that all GSI registers are little-endian, which is the assumed
90 /* Delay period for interrupt moderation (in 32KHz IPA internal timer ticks) */
115 /** gsi_channel_scratch_gpi - GPI protocol scratch register
134 /** gsi_channel_scratch - channel scratch configuration area
136 * The exact interpretation of this register is protocol-specific.
171 return channel - &channel->gsi->channel[0]; in gsi_channel_id()
174 /* An initialized channel has a non-null GSI pointer */
177 return !!channel->gsi; in gsi_channel_initialized()
182 const struct reg *reg, in ch_c_cntxt_0_type_encode() argument
187 val = reg_encode(reg, CHTYPE_PROTOCOL, type); in ch_c_cntxt_0_type_encode()
191 type >>= hweight32(reg_fmask(reg, CHTYPE_PROTOCOL)); in ch_c_cntxt_0_type_encode()
193 return val | reg_encode(reg, CHTYPE_PROTOCOL_MSB, type); in ch_c_cntxt_0_type_encode()
199 const struct reg *reg = gsi_reg(gsi, CNTXT_TYPE_IRQ_MSK); in gsi_irq_type_update() local
201 gsi->type_enabled_bitmap = val; in gsi_irq_type_update()
202 iowrite32(val, gsi->virt + reg_offset(reg)); in gsi_irq_type_update()
207 gsi_irq_type_update(gsi, gsi->type_enabled_bitmap | type_id); in gsi_irq_type_enable()
212 gsi_irq_type_update(gsi, gsi->type_enabled_bitmap & ~type_id); in gsi_irq_type_disable()
223 const struct reg *reg; in gsi_irq_ev_ctrl_enable() local
229 reg = gsi_reg(gsi, CNTXT_SRC_EV_CH_IRQ_CLR); in gsi_irq_ev_ctrl_enable()
230 iowrite32(~0, gsi->virt + reg_offset(reg)); in gsi_irq_ev_ctrl_enable()
232 reg = gsi_reg(gsi, CNTXT_SRC_EV_CH_IRQ_MSK); in gsi_irq_ev_ctrl_enable()
233 iowrite32(val, gsi->virt + reg_offset(reg)); in gsi_irq_ev_ctrl_enable()
240 const struct reg *reg; in gsi_irq_ev_ctrl_disable() local
244 reg = gsi_reg(gsi, CNTXT_SRC_EV_CH_IRQ_MSK); in gsi_irq_ev_ctrl_disable()
245 iowrite32(0, gsi->virt + reg_offset(reg)); in gsi_irq_ev_ctrl_disable()
256 const struct reg *reg; in gsi_irq_ch_ctrl_enable() local
262 reg = gsi_reg(gsi, CNTXT_SRC_CH_IRQ_CLR); in gsi_irq_ch_ctrl_enable()
263 iowrite32(~0, gsi->virt + reg_offset(reg)); in gsi_irq_ch_ctrl_enable()
265 reg = gsi_reg(gsi, CNTXT_SRC_CH_IRQ_MSK); in gsi_irq_ch_ctrl_enable()
266 iowrite32(val, gsi->virt + reg_offset(reg)); in gsi_irq_ch_ctrl_enable()
274 const struct reg *reg; in gsi_irq_ch_ctrl_disable() local
278 reg = gsi_reg(gsi, CNTXT_SRC_CH_IRQ_MSK); in gsi_irq_ch_ctrl_disable()
279 iowrite32(0, gsi->virt + reg_offset(reg)); in gsi_irq_ch_ctrl_disable()
284 bool enable_ieob = !gsi->ieob_enabled_bitmap; in gsi_irq_ieob_enable_one()
285 const struct reg *reg; in gsi_irq_ieob_enable_one() local
288 gsi->ieob_enabled_bitmap |= BIT(evt_ring_id); in gsi_irq_ieob_enable_one()
290 reg = gsi_reg(gsi, CNTXT_SRC_IEOB_IRQ_MSK); in gsi_irq_ieob_enable_one()
291 val = gsi->ieob_enabled_bitmap; in gsi_irq_ieob_enable_one()
292 iowrite32(val, gsi->virt + reg_offset(reg)); in gsi_irq_ieob_enable_one()
301 const struct reg *reg; in gsi_irq_ieob_disable() local
304 gsi->ieob_enabled_bitmap &= ~event_mask; in gsi_irq_ieob_disable()
307 if (!gsi->ieob_enabled_bitmap) in gsi_irq_ieob_disable()
310 reg = gsi_reg(gsi, CNTXT_SRC_IEOB_IRQ_MSK); in gsi_irq_ieob_disable()
311 val = gsi->ieob_enabled_bitmap; in gsi_irq_ieob_disable()
312 iowrite32(val, gsi->virt + reg_offset(reg)); in gsi_irq_ieob_disable()
323 const struct reg *reg; in gsi_irq_enable() local
329 reg = gsi_reg(gsi, CNTXT_GLOB_IRQ_EN); in gsi_irq_enable()
330 iowrite32(ERROR_INT, gsi->virt + reg_offset(reg)); in gsi_irq_enable()
332 gsi_irq_type_update(gsi, gsi->type_enabled_bitmap | GSI_GLOB_EE); in gsi_irq_enable()
339 reg = gsi_reg(gsi, CNTXT_GSI_IRQ_EN); in gsi_irq_enable()
343 iowrite32(val, gsi->virt + reg_offset(reg)); in gsi_irq_enable()
345 gsi_irq_type_update(gsi, gsi->type_enabled_bitmap | GSI_GENERAL); in gsi_irq_enable()
351 const struct reg *reg; in gsi_irq_disable() local
355 /* Clear the type-specific interrupt masks set by gsi_irq_enable() */ in gsi_irq_disable()
356 reg = gsi_reg(gsi, CNTXT_GSI_IRQ_EN); in gsi_irq_disable()
357 iowrite32(0, gsi->virt + reg_offset(reg)); in gsi_irq_disable()
359 reg = gsi_reg(gsi, CNTXT_GLOB_IRQ_EN); in gsi_irq_disable()
360 iowrite32(0, gsi->virt + reg_offset(reg)); in gsi_irq_disable()
367 return ring->virt + (index % ring->count) * GSI_RING_ELEMENT_SIZE; in gsi_ring_virt()
370 /* Return the 32-bit DMA address associated with a ring index */
373 return lower_32_bits(ring->addr) + index * GSI_RING_ELEMENT_SIZE; in gsi_ring_addr()
376 /* Return the ring index of a 32-bit ring offset */
379 return (offset - gsi_ring_addr(ring, 0)) / GSI_RING_ELEMENT_SIZE; in gsi_ring_index()
386 static bool gsi_command(struct gsi *gsi, u32 reg, u32 val) in gsi_command() argument
389 struct completion *completion = &gsi->completion; in gsi_command()
393 iowrite32(val, gsi->virt + reg); in gsi_command()
402 const struct reg *reg = gsi_reg(gsi, EV_CH_E_CNTXT_0); in gsi_evt_ring_state() local
405 val = ioread32(gsi->virt + reg_n_offset(reg, evt_ring_id)); in gsi_evt_ring_state()
407 return reg_decode(reg, EV_CHSTATE, val); in gsi_evt_ring_state()
414 struct device *dev = gsi->dev; in gsi_evt_ring_command()
415 const struct reg *reg; in gsi_evt_ring_command() local
422 reg = gsi_reg(gsi, EV_CH_CMD); in gsi_evt_ring_command()
423 val = reg_encode(reg, EV_CHID, evt_ring_id); in gsi_evt_ring_command()
424 val |= reg_encode(reg, EV_OPCODE, opcode); in gsi_evt_ring_command()
426 timeout = !gsi_command(gsi, reg_offset(reg), val); in gsi_evt_ring_command()
445 dev_err(gsi->dev, "event ring %u bad state %u before alloc\n", in gsi_evt_ring_alloc_command()
447 return -EINVAL; in gsi_evt_ring_alloc_command()
457 dev_err(gsi->dev, "event ring %u bad state %u after alloc\n", in gsi_evt_ring_alloc_command()
460 return -EIO; in gsi_evt_ring_alloc_command()
471 dev_err(gsi->dev, "event ring %u bad state %u before reset\n", in gsi_evt_ring_reset_command()
483 dev_err(gsi->dev, "event ring %u bad state %u after reset\n", in gsi_evt_ring_reset_command()
487 /* Issue a hardware de-allocation request for an allocated event ring */
494 dev_err(gsi->dev, "event ring %u state %u before dealloc\n", in gsi_evt_ring_de_alloc_command()
506 dev_err(gsi->dev, "event ring %u bad state %u after dealloc\n", in gsi_evt_ring_de_alloc_command()
513 const struct reg *reg = gsi_reg(channel->gsi, CH_C_CNTXT_0); in gsi_channel_state() local
515 struct gsi *gsi = channel->gsi; in gsi_channel_state()
516 void __iomem *virt = gsi->virt; in gsi_channel_state()
519 reg = gsi_reg(gsi, CH_C_CNTXT_0); in gsi_channel_state()
520 val = ioread32(virt + reg_n_offset(reg, channel_id)); in gsi_channel_state()
522 return reg_decode(reg, CHSTATE, val); in gsi_channel_state()
530 struct gsi *gsi = channel->gsi; in gsi_channel_command()
531 struct device *dev = gsi->dev; in gsi_channel_command()
532 const struct reg *reg; in gsi_channel_command() local
539 reg = gsi_reg(gsi, CH_CMD); in gsi_channel_command()
540 val = reg_encode(reg, CH_CHID, channel_id); in gsi_channel_command()
541 val |= reg_encode(reg, CH_OPCODE, opcode); in gsi_channel_command()
543 timeout = !gsi_command(gsi, reg_offset(reg), val); in gsi_channel_command()
557 struct gsi_channel *channel = &gsi->channel[channel_id]; in gsi_channel_alloc_command()
558 struct device *dev = gsi->dev; in gsi_channel_alloc_command()
566 return -EINVAL; in gsi_channel_alloc_command()
579 return -EIO; in gsi_channel_alloc_command()
585 struct device *dev = channel->gsi->dev; in gsi_channel_start_command()
593 return -EINVAL; in gsi_channel_start_command()
606 return -EIO; in gsi_channel_start_command()
612 struct device *dev = channel->gsi->dev; in gsi_channel_stop_command()
627 return -EINVAL; in gsi_channel_stop_command()
639 return -EAGAIN; in gsi_channel_stop_command()
644 return -EIO; in gsi_channel_stop_command()
650 struct device *dev = channel->gsi->dev; in gsi_channel_reset_command()
678 struct gsi_channel *channel = &gsi->channel[channel_id]; in gsi_channel_de_alloc_command()
679 struct device *dev = gsi->dev; in gsi_channel_de_alloc_command()
706 const struct reg *reg = gsi_reg(gsi, EV_CH_E_DOORBELL_0); in gsi_evt_ring_doorbell() local
707 struct gsi_ring *ring = &gsi->evt_ring[evt_ring_id].ring; in gsi_evt_ring_doorbell()
710 ring->index = index; /* Next unused entry */ in gsi_evt_ring_doorbell()
713 val = gsi_ring_addr(ring, (index - 1) % ring->count); in gsi_evt_ring_doorbell()
714 iowrite32(val, gsi->virt + reg_n_offset(reg, evt_ring_id)); in gsi_evt_ring_doorbell()
720 struct gsi_evt_ring *evt_ring = &gsi->evt_ring[evt_ring_id]; in gsi_evt_ring_program()
721 struct gsi_ring *ring = &evt_ring->ring; in gsi_evt_ring_program()
722 const struct reg *reg; in gsi_evt_ring_program() local
725 reg = gsi_reg(gsi, EV_CH_E_CNTXT_0); in gsi_evt_ring_program()
727 val = reg_encode(reg, EV_CHTYPE, GSI_CHANNEL_TYPE_GPI); in gsi_evt_ring_program()
729 val |= reg_bit(reg, EV_INTYPE); in gsi_evt_ring_program()
730 val |= reg_encode(reg, EV_ELEMENT_SIZE, GSI_RING_ELEMENT_SIZE); in gsi_evt_ring_program()
731 iowrite32(val, gsi->virt + reg_n_offset(reg, evt_ring_id)); in gsi_evt_ring_program()
733 reg = gsi_reg(gsi, EV_CH_E_CNTXT_1); in gsi_evt_ring_program()
734 val = reg_encode(reg, R_LENGTH, ring->count * GSI_RING_ELEMENT_SIZE); in gsi_evt_ring_program()
735 iowrite32(val, gsi->virt + reg_n_offset(reg, evt_ring_id)); in gsi_evt_ring_program()
737 /* The context 2 and 3 registers store the low-order and in gsi_evt_ring_program()
738 * high-order 32 bits of the address of the event ring, in gsi_evt_ring_program()
741 reg = gsi_reg(gsi, EV_CH_E_CNTXT_2); in gsi_evt_ring_program()
742 val = lower_32_bits(ring->addr); in gsi_evt_ring_program()
743 iowrite32(val, gsi->virt + reg_n_offset(reg, evt_ring_id)); in gsi_evt_ring_program()
745 reg = gsi_reg(gsi, EV_CH_E_CNTXT_3); in gsi_evt_ring_program()
746 val = upper_32_bits(ring->addr); in gsi_evt_ring_program()
747 iowrite32(val, gsi->virt + reg_n_offset(reg, evt_ring_id)); in gsi_evt_ring_program()
750 reg = gsi_reg(gsi, EV_CH_E_CNTXT_8); in gsi_evt_ring_program()
751 val = reg_encode(reg, EV_MODT, GSI_EVT_RING_INT_MODT); in gsi_evt_ring_program()
752 val |= reg_encode(reg, EV_MODC, 1); /* comes from channel */ in gsi_evt_ring_program()
753 /* EV_MOD_CNT is 0 (no counter-based interrupt coalescing) */ in gsi_evt_ring_program()
754 iowrite32(val, gsi->virt + reg_n_offset(reg, evt_ring_id)); in gsi_evt_ring_program()
757 reg = gsi_reg(gsi, EV_CH_E_CNTXT_9); in gsi_evt_ring_program()
758 iowrite32(0, gsi->virt + reg_n_offset(reg, evt_ring_id)); in gsi_evt_ring_program()
760 reg = gsi_reg(gsi, EV_CH_E_CNTXT_10); in gsi_evt_ring_program()
761 iowrite32(0, gsi->virt + reg_n_offset(reg, evt_ring_id)); in gsi_evt_ring_program()
763 reg = gsi_reg(gsi, EV_CH_E_CNTXT_11); in gsi_evt_ring_program()
764 iowrite32(0, gsi->virt + reg_n_offset(reg, evt_ring_id)); in gsi_evt_ring_program()
767 reg = gsi_reg(gsi, EV_CH_E_CNTXT_12); in gsi_evt_ring_program()
768 iowrite32(0, gsi->virt + reg_n_offset(reg, evt_ring_id)); in gsi_evt_ring_program()
770 reg = gsi_reg(gsi, EV_CH_E_CNTXT_13); in gsi_evt_ring_program()
771 iowrite32(0, gsi->virt + reg_n_offset(reg, evt_ring_id)); in gsi_evt_ring_program()
774 gsi_evt_ring_doorbell(gsi, evt_ring_id, ring->index); in gsi_evt_ring_program()
780 struct gsi_trans_info *trans_info = &channel->trans_info; in gsi_channel_trans_last()
781 u32 pending_id = trans_info->pending_id; in gsi_channel_trans_last()
785 if (channel->toward_ipa && pending_id != trans_info->free_id) { in gsi_channel_trans_last()
791 trans_id = trans_info->free_id - 1; in gsi_channel_trans_last()
792 } else if (trans_info->polled_id != pending_id) { in gsi_channel_trans_last()
799 trans_id = pending_id - 1; in gsi_channel_trans_last()
805 trans = &trans_info->trans[trans_id % channel->tre_count]; in gsi_channel_trans_last()
806 refcount_inc(&trans->refcount); in gsi_channel_trans_last()
819 wait_for_completion(&trans->completion); in gsi_channel_trans_quiesce()
827 size_t size = channel->tre_ring.count * GSI_RING_ELEMENT_SIZE; in gsi_channel_program()
831 struct gsi *gsi = channel->gsi; in gsi_channel_program()
832 const struct reg *reg; in gsi_channel_program() local
837 reg = gsi_reg(gsi, CH_C_CNTXT_0); in gsi_channel_program()
840 val = ch_c_cntxt_0_type_encode(gsi->version, reg, GSI_CHANNEL_TYPE_GPI); in gsi_channel_program()
841 if (channel->toward_ipa) in gsi_channel_program()
842 val |= reg_bit(reg, CHTYPE_DIR); in gsi_channel_program()
843 if (gsi->version < IPA_VERSION_5_0) in gsi_channel_program()
844 val |= reg_encode(reg, ERINDEX, channel->evt_ring_id); in gsi_channel_program()
845 val |= reg_encode(reg, ELEMENT_SIZE, GSI_RING_ELEMENT_SIZE); in gsi_channel_program()
846 iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id)); in gsi_channel_program()
848 reg = gsi_reg(gsi, CH_C_CNTXT_1); in gsi_channel_program()
849 val = reg_encode(reg, CH_R_LENGTH, size); in gsi_channel_program()
850 if (gsi->version >= IPA_VERSION_5_0) in gsi_channel_program()
851 val |= reg_encode(reg, CH_ERINDEX, channel->evt_ring_id); in gsi_channel_program()
852 iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id)); in gsi_channel_program()
854 /* The context 2 and 3 registers store the low-order and in gsi_channel_program()
855 * high-order 32 bits of the address of the channel ring, in gsi_channel_program()
858 reg = gsi_reg(gsi, CH_C_CNTXT_2); in gsi_channel_program()
859 val = lower_32_bits(channel->tre_ring.addr); in gsi_channel_program()
860 iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id)); in gsi_channel_program()
862 reg = gsi_reg(gsi, CH_C_CNTXT_3); in gsi_channel_program()
863 val = upper_32_bits(channel->tre_ring.addr); in gsi_channel_program()
864 iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id)); in gsi_channel_program()
866 reg = gsi_reg(gsi, CH_C_QOS); in gsi_channel_program()
868 /* Command channel gets low weighted round-robin priority */ in gsi_channel_program()
869 if (channel->command) in gsi_channel_program()
870 wrr_weight = reg_field_max(reg, WRR_WEIGHT); in gsi_channel_program()
871 val = reg_encode(reg, WRR_WEIGHT, wrr_weight); in gsi_channel_program()
875 /* No need to use the doorbell engine starting at IPA v4.0 */ in gsi_channel_program()
876 if (gsi->version < IPA_VERSION_4_0 && doorbell) in gsi_channel_program()
877 val |= reg_bit(reg, USE_DB_ENG); in gsi_channel_program()
882 if (gsi->version >= IPA_VERSION_4_0 && !channel->command) { in gsi_channel_program()
884 if (gsi->version < IPA_VERSION_4_5) in gsi_channel_program()
885 val |= reg_bit(reg, USE_ESCAPE_BUF_ONLY); in gsi_channel_program()
887 val |= reg_encode(reg, PREFETCH_MODE, ESCAPE_BUF_ONLY); in gsi_channel_program()
890 if (gsi->version >= IPA_VERSION_4_9) in gsi_channel_program()
891 val |= reg_bit(reg, DB_IN_BYTES); in gsi_channel_program()
893 iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id)); in gsi_channel_program()
897 gpi->max_outstanding_tre = channel->trans_tre_max * in gsi_channel_program()
899 gpi->outstanding_threshold = 2 * GSI_RING_ELEMENT_SIZE; in gsi_channel_program()
901 reg = gsi_reg(gsi, CH_C_SCRATCH_0); in gsi_channel_program()
903 iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id)); in gsi_channel_program()
905 reg = gsi_reg(gsi, CH_C_SCRATCH_1); in gsi_channel_program()
907 iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id)); in gsi_channel_program()
909 reg = gsi_reg(gsi, CH_C_SCRATCH_2); in gsi_channel_program()
911 iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id)); in gsi_channel_program()
917 reg = gsi_reg(gsi, CH_C_SCRATCH_3); in gsi_channel_program()
918 offset = reg_n_offset(reg, channel_id); in gsi_channel_program()
919 val = ioread32(gsi->virt + offset); in gsi_channel_program()
921 iowrite32(val, gsi->virt + offset); in gsi_channel_program()
928 struct gsi *gsi = channel->gsi; in __gsi_channel_start()
931 /* Prior to IPA v4.0 suspend/resume is not implemented by GSI */ in __gsi_channel_start()
932 if (resume && gsi->version < IPA_VERSION_4_0) in __gsi_channel_start()
935 mutex_lock(&gsi->mutex); in __gsi_channel_start()
939 mutex_unlock(&gsi->mutex); in __gsi_channel_start()
947 struct gsi_channel *channel = &gsi->channel[channel_id]; in gsi_channel_start()
951 napi_enable(&channel->napi); in gsi_channel_start()
952 gsi_irq_ieob_enable_one(gsi, channel->evt_ring_id); in gsi_channel_start()
956 gsi_irq_ieob_disable_one(gsi, channel->evt_ring_id); in gsi_channel_start()
957 napi_disable(&channel->napi); in gsi_channel_start()
970 if (ret != -EAGAIN) in gsi_channel_stop_retry()
973 } while (retries--); in gsi_channel_stop_retry()
980 struct gsi *gsi = channel->gsi; in __gsi_channel_stop()
986 /* Prior to IPA v4.0 suspend/resume is not implemented by GSI */ in __gsi_channel_stop()
987 if (suspend && gsi->version < IPA_VERSION_4_0) in __gsi_channel_stop()
990 mutex_lock(&gsi->mutex); in __gsi_channel_stop()
994 mutex_unlock(&gsi->mutex); in __gsi_channel_stop()
1002 struct gsi_channel *channel = &gsi->channel[channel_id]; in gsi_channel_stop()
1010 gsi_irq_ieob_disable_one(gsi, channel->evt_ring_id); in gsi_channel_stop()
1011 napi_disable(&channel->napi); in gsi_channel_stop()
1019 struct gsi_channel *channel = &gsi->channel[channel_id]; in gsi_channel_reset()
1021 mutex_lock(&gsi->mutex); in gsi_channel_reset()
1025 if (gsi->version < IPA_VERSION_4_0 && !channel->toward_ipa) in gsi_channel_reset()
1029 channel->tre_ring.index = 0; in gsi_channel_reset()
1033 mutex_unlock(&gsi->mutex); in gsi_channel_reset()
1039 struct gsi_channel *channel = &gsi->channel[channel_id]; in gsi_channel_suspend()
1047 napi_synchronize(&channel->napi); in gsi_channel_suspend()
1055 struct gsi_channel *channel = &gsi->channel[channel_id]; in gsi_channel_resume()
1063 disable_irq(gsi->irq); in gsi_suspend()
1069 enable_irq(gsi->irq); in gsi_resume()
1074 struct gsi_channel *channel = &trans->gsi->channel[trans->channel_id]; in gsi_trans_tx_committed()
1076 channel->trans_count++; in gsi_trans_tx_committed()
1077 channel->byte_count += trans->len; in gsi_trans_tx_committed()
1079 trans->trans_count = channel->trans_count; in gsi_trans_tx_committed()
1080 trans->byte_count = channel->byte_count; in gsi_trans_tx_committed()
1085 u32 channel_id = trans->channel_id; in gsi_trans_tx_queued()
1086 struct gsi *gsi = trans->gsi; in gsi_trans_tx_queued()
1091 channel = &gsi->channel[channel_id]; in gsi_trans_tx_queued()
1093 byte_count = channel->byte_count - channel->queued_byte_count; in gsi_trans_tx_queued()
1094 trans_count = channel->trans_count - channel->queued_trans_count; in gsi_trans_tx_queued()
1095 channel->queued_byte_count = channel->byte_count; in gsi_trans_tx_queued()
1096 channel->queued_trans_count = channel->trans_count; in gsi_trans_tx_queued()
1102 * gsi_trans_tx_completed() - Report completed TX transactions
1118 u32 channel_id = trans->channel_id; in gsi_trans_tx_completed()
1119 struct gsi *gsi = trans->gsi; in gsi_trans_tx_completed()
1124 channel = &gsi->channel[channel_id]; in gsi_trans_tx_completed()
1125 trans_count = trans->trans_count - channel->compl_trans_count; in gsi_trans_tx_completed()
1126 byte_count = trans->byte_count - channel->compl_byte_count; in gsi_trans_tx_completed()
1128 channel->compl_trans_count += trans_count; in gsi_trans_tx_completed()
1129 channel->compl_byte_count += byte_count; in gsi_trans_tx_completed()
1137 const struct reg *reg; in gsi_isr_chan_ctrl() local
1140 reg = gsi_reg(gsi, CNTXT_SRC_CH_IRQ); in gsi_isr_chan_ctrl()
1141 channel_mask = ioread32(gsi->virt + reg_offset(reg)); in gsi_isr_chan_ctrl()
1143 reg = gsi_reg(gsi, CNTXT_SRC_CH_IRQ_CLR); in gsi_isr_chan_ctrl()
1144 iowrite32(channel_mask, gsi->virt + reg_offset(reg)); in gsi_isr_chan_ctrl()
1151 complete(&gsi->completion); in gsi_isr_chan_ctrl()
1158 const struct reg *reg; in gsi_isr_evt_ctrl() local
1161 reg = gsi_reg(gsi, CNTXT_SRC_EV_CH_IRQ); in gsi_isr_evt_ctrl()
1162 event_mask = ioread32(gsi->virt + reg_offset(reg)); in gsi_isr_evt_ctrl()
1164 reg = gsi_reg(gsi, CNTXT_SRC_EV_CH_IRQ_CLR); in gsi_isr_evt_ctrl()
1165 iowrite32(event_mask, gsi->virt + reg_offset(reg)); in gsi_isr_evt_ctrl()
1172 complete(&gsi->completion); in gsi_isr_evt_ctrl()
1181 dev_err(gsi->dev, "channel %u out of resources\n", channel_id); in gsi_isr_glob_chan_err()
1182 complete(&gsi->completion); in gsi_isr_glob_chan_err()
1187 dev_err(gsi->dev, "channel %u global error ee 0x%08x code 0x%08x\n", in gsi_isr_glob_chan_err()
1196 struct gsi_evt_ring *evt_ring = &gsi->evt_ring[evt_ring_id]; in gsi_isr_glob_evt_err()
1197 u32 channel_id = gsi_channel_id(evt_ring->channel); in gsi_isr_glob_evt_err()
1199 complete(&gsi->completion); in gsi_isr_glob_evt_err()
1200 dev_err(gsi->dev, "evt_ring for channel %u out of resources\n", in gsi_isr_glob_evt_err()
1206 dev_err(gsi->dev, "event ring %u global error ee %u code 0x%08x\n", in gsi_isr_glob_evt_err()
1213 const struct reg *log_reg; in gsi_isr_glob_err()
1214 const struct reg *clr_reg; in gsi_isr_glob_err()
1225 val = ioread32(gsi->virt + offset); in gsi_isr_glob_err()
1226 iowrite32(0, gsi->virt + offset); in gsi_isr_glob_err()
1229 iowrite32(~0, gsi->virt + reg_offset(clr_reg)); in gsi_isr_glob_err()
1242 dev_err(gsi->dev, "unexpected global error 0x%08x\n", type); in gsi_isr_glob_err()
1248 const struct reg *reg; in gsi_isr_gp_int1() local
1254 * modem's behalf due to a hardware quirk on IPA v4.2. The modem in gsi_isr_gp_int1()
1259 * control for IPA v4.2+. in gsi_isr_gp_int1()
1271 reg = gsi_reg(gsi, CNTXT_SCRATCH_0); in gsi_isr_gp_int1()
1272 val = ioread32(gsi->virt + reg_offset(reg)); in gsi_isr_gp_int1()
1273 result = reg_decode(reg, GENERIC_EE_RESULT, val); in gsi_isr_gp_int1()
1278 gsi->result = 0; in gsi_isr_gp_int1()
1282 gsi->result = -EAGAIN; in gsi_isr_gp_int1()
1286 dev_err(gsi->dev, "global INT1 generic result %u\n", result); in gsi_isr_gp_int1()
1287 gsi->result = -EIO; in gsi_isr_gp_int1()
1291 complete(&gsi->completion); in gsi_isr_gp_int1()
1294 /* Inter-EE interrupt handler */
1297 const struct reg *reg; in gsi_isr_glob_ee() local
1300 reg = gsi_reg(gsi, CNTXT_GLOB_IRQ_STTS); in gsi_isr_glob_ee()
1301 val = ioread32(gsi->virt + reg_offset(reg)); in gsi_isr_glob_ee()
1306 reg = gsi_reg(gsi, CNTXT_GLOB_IRQ_CLR); in gsi_isr_glob_ee()
1307 iowrite32(val, gsi->virt + reg_offset(reg)); in gsi_isr_glob_ee()
1317 dev_err(gsi->dev, "unexpected global interrupt 0x%08x\n", val); in gsi_isr_glob_ee()
1323 const struct reg *reg; in gsi_isr_ieob() local
1326 reg = gsi_reg(gsi, CNTXT_SRC_IEOB_IRQ); in gsi_isr_ieob()
1327 event_mask = ioread32(gsi->virt + reg_offset(reg)); in gsi_isr_ieob()
1331 reg = gsi_reg(gsi, CNTXT_SRC_IEOB_IRQ_CLR); in gsi_isr_ieob()
1332 iowrite32(event_mask, gsi->virt + reg_offset(reg)); in gsi_isr_ieob()
1339 napi_schedule(&gsi->evt_ring[evt_ring_id].channel->napi); in gsi_isr_ieob()
1346 struct device *dev = gsi->dev; in gsi_isr_general()
1347 const struct reg *reg; in gsi_isr_general() local
1350 reg = gsi_reg(gsi, CNTXT_GSI_IRQ_STTS); in gsi_isr_general()
1351 val = ioread32(gsi->virt + reg_offset(reg)); in gsi_isr_general()
1353 reg = gsi_reg(gsi, CNTXT_GSI_IRQ_CLR); in gsi_isr_general()
1354 iowrite32(val, gsi->virt + reg_offset(reg)); in gsi_isr_general()
1360 * gsi_isr() - Top level GSI interrupt service routine
1370 const struct reg *reg; in gsi_isr() local
1375 reg = gsi_reg(gsi, CNTXT_TYPE_IRQ); in gsi_isr()
1376 offset = reg_offset(reg); in gsi_isr()
1379 while ((intr_mask = ioread32(gsi->virt + offset))) { in gsi_isr()
1387 * when the type-specific register is updated. in gsi_isr()
1406 dev_err(gsi->dev, in gsi_isr()
1414 dev_err(gsi->dev, "interrupt flood\n"); in gsi_isr()
1429 return ret ? : -EINVAL; in gsi_irq_init()
1431 gsi->irq = ret; in gsi_irq_init()
1440 u32 channel_id = event->chid; in gsi_event_trans()
1446 channel = &gsi->channel[channel_id]; in gsi_event_trans()
1447 if (WARN(!channel->gsi, "event has bad channel %u\n", channel_id)) in gsi_event_trans()
1451 tre_offset = lower_32_bits(le64_to_cpu(event->xfer_ptr)); in gsi_event_trans()
1452 tre_index = gsi_ring_index(&channel->tre_ring, tre_offset); in gsi_event_trans()
1463 * gsi_evt_ring_update() - Update transaction state from hardware
1488 struct gsi_evt_ring *evt_ring = &gsi->evt_ring[evt_ring_id]; in gsi_evt_ring_update()
1489 struct gsi_ring *ring = &evt_ring->ring; in gsi_evt_ring_update()
1495 /* Starting with the oldest un-processed event, determine which in gsi_evt_ring_update()
1502 old_index = ring->index; in gsi_evt_ring_update()
1508 event_avail = ring->count - old_index % ring->count; in gsi_evt_ring_update()
1517 if (trans->direction == DMA_FROM_DEVICE) in gsi_evt_ring_update()
1518 trans->len = __le16_to_cpu(event->len); in gsi_evt_ring_update()
1525 if (--event_avail) in gsi_evt_ring_update()
1539 struct device *dev = gsi->dev; in gsi_ring_alloc()
1544 * be a power-of-2 number of pages, which satisfies the requirement. in gsi_ring_alloc()
1546 ring->virt = dma_alloc_coherent(dev, size, &addr, GFP_KERNEL); in gsi_ring_alloc()
1547 if (!ring->virt) in gsi_ring_alloc()
1548 return -ENOMEM; in gsi_ring_alloc()
1550 ring->addr = addr; in gsi_ring_alloc()
1551 ring->count = count; in gsi_ring_alloc()
1552 ring->index = 0; in gsi_ring_alloc()
1557 /* Free a previously-allocated ring */
1560 size_t size = ring->count * GSI_RING_ELEMENT_SIZE; in gsi_ring_free()
1562 dma_free_coherent(gsi->dev, size, ring->virt, ring->addr); in gsi_ring_free()
1570 if (gsi->event_bitmap == ~0U) { in gsi_evt_ring_id_alloc()
1571 dev_err(gsi->dev, "event rings exhausted\n"); in gsi_evt_ring_id_alloc()
1572 return -ENOSPC; in gsi_evt_ring_id_alloc()
1575 evt_ring_id = ffz(gsi->event_bitmap); in gsi_evt_ring_id_alloc()
1576 gsi->event_bitmap |= BIT(evt_ring_id); in gsi_evt_ring_id_alloc()
1581 /* Free a previously-allocated event ring id */
1584 gsi->event_bitmap &= ~BIT(evt_ring_id); in gsi_evt_ring_id_free()
1587 /* Ring a channel doorbell, reporting the first un-filled entry */
1590 struct gsi_ring *tre_ring = &channel->tre_ring; in gsi_channel_doorbell()
1592 struct gsi *gsi = channel->gsi; in gsi_channel_doorbell()
1593 const struct reg *reg; in gsi_channel_doorbell() local
1596 reg = gsi_reg(gsi, CH_C_DOORBELL_0); in gsi_channel_doorbell()
1598 val = gsi_ring_addr(tre_ring, tre_ring->index % tre_ring->count); in gsi_channel_doorbell()
1599 iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id)); in gsi_channel_doorbell()
1605 u32 evt_ring_id = channel->evt_ring_id; in gsi_channel_update()
1606 struct gsi *gsi = channel->gsi; in gsi_channel_update()
1610 const struct reg *reg; in gsi_channel_update() local
1614 evt_ring = &gsi->evt_ring[evt_ring_id]; in gsi_channel_update()
1615 ring = &evt_ring->ring; in gsi_channel_update()
1620 reg = gsi_reg(gsi, EV_CH_E_CNTXT_4); in gsi_channel_update()
1621 offset = reg_n_offset(reg, evt_ring_id); in gsi_channel_update()
1622 index = gsi_ring_index(ring, ioread32(gsi->virt + offset)); in gsi_channel_update()
1623 if (index == ring->index % ring->count) in gsi_channel_update()
1627 trans = gsi_event_trans(gsi, gsi_ring_virt(ring, index - 1)); in gsi_channel_update()
1640 * gsi_channel_poll_one() - Return a single completed transaction on a channel
1664 * gsi_channel_poll() - NAPI poll function for a channel
1691 gsi_irq_ieob_enable_one(channel->gsi, channel->evt_ring_id); in gsi_channel_poll()
1703 u32 event_bitmap = GENMASK(BITS_PER_LONG - 1, evt_ring_max); in gsi_event_bitmap_init()
1713 struct gsi_channel *channel = &gsi->channel[channel_id]; in gsi_channel_setup_one()
1714 u32 evt_ring_id = channel->evt_ring_id; in gsi_channel_setup_one()
1732 if (channel->toward_ipa) in gsi_channel_setup_one()
1733 netif_napi_add_tx(&gsi->dummy_dev, &channel->napi, in gsi_channel_setup_one()
1736 netif_napi_add(&gsi->dummy_dev, &channel->napi, in gsi_channel_setup_one()
1751 struct gsi_channel *channel = &gsi->channel[channel_id]; in gsi_channel_teardown_one()
1752 u32 evt_ring_id = channel->evt_ring_id; in gsi_channel_teardown_one()
1757 netif_napi_del(&channel->napi); in gsi_channel_teardown_one()
1772 const struct reg *reg; in gsi_generic_command() local
1786 reg = gsi_reg(gsi, CNTXT_GLOB_IRQ_EN); in gsi_generic_command()
1788 iowrite32(val, gsi->virt + reg_offset(reg)); in gsi_generic_command()
1791 reg = gsi_reg(gsi, CNTXT_SCRATCH_0); in gsi_generic_command()
1792 offset = reg_offset(reg); in gsi_generic_command()
1793 val = ioread32(gsi->virt + offset); in gsi_generic_command()
1795 val &= ~reg_fmask(reg, GENERIC_EE_RESULT); in gsi_generic_command()
1796 iowrite32(val, gsi->virt + offset); in gsi_generic_command()
1799 reg = gsi_reg(gsi, GENERIC_CMD); in gsi_generic_command()
1800 val = reg_encode(reg, GENERIC_OPCODE, opcode); in gsi_generic_command()
1801 val |= reg_encode(reg, GENERIC_CHID, channel_id); in gsi_generic_command()
1802 val |= reg_encode(reg, GENERIC_EE, GSI_EE_MODEM); in gsi_generic_command()
1803 if (gsi->version >= IPA_VERSION_4_11) in gsi_generic_command()
1804 val |= reg_encode(reg, GENERIC_PARAMS, params); in gsi_generic_command()
1806 timeout = !gsi_command(gsi, reg_offset(reg), val); in gsi_generic_command()
1809 reg = gsi_reg(gsi, CNTXT_GLOB_IRQ_EN); in gsi_generic_command()
1810 iowrite32(ERROR_INT, gsi->virt + reg_offset(reg)); in gsi_generic_command()
1813 return gsi->result; in gsi_generic_command()
1815 dev_err(gsi->dev, "GSI generic command %u to channel %u timed out\n", in gsi_generic_command()
1818 return -ETIMEDOUT; in gsi_generic_command()
1835 while (ret == -EAGAIN && retries--); in gsi_modem_channel_halt()
1838 dev_err(gsi->dev, "error %d halting modem channel %u\n", in gsi_modem_channel_halt()
1842 /* Enable or disable flow control for a modem GSI TX channel (IPA v4.2+) */
1852 /* Disabling flow control on IPA v4.11+ can return -EAGAIN if enable in gsi_modem_channel_flow_control()
1855 if (!enable && gsi->version >= IPA_VERSION_4_11) in gsi_modem_channel_flow_control()
1860 while (ret == -EAGAIN && retries--); in gsi_modem_channel_flow_control()
1863 dev_err(gsi->dev, in gsi_modem_channel_flow_control()
1877 mutex_lock(&gsi->mutex); in gsi_channel_setup()
1883 } while (++channel_id < gsi->channel_count); in gsi_channel_setup()
1887 struct gsi_channel *channel = &gsi->channel[channel_id++]; in gsi_channel_setup()
1892 ret = -EINVAL; in gsi_channel_setup()
1893 dev_err(gsi->dev, "channel %u not supported by hardware\n", in gsi_channel_setup()
1894 channel_id - 1); in gsi_channel_setup()
1895 channel_id = gsi->channel_count; in gsi_channel_setup()
1900 mask = gsi->modem_channel_bitmap; in gsi_channel_setup()
1912 mutex_unlock(&gsi->mutex); in gsi_channel_setup()
1918 mask ^= gsi->modem_channel_bitmap; in gsi_channel_setup()
1928 while (channel_id--) in gsi_channel_setup()
1931 mutex_unlock(&gsi->mutex); in gsi_channel_setup()
1941 u32 mask = gsi->modem_channel_bitmap; in gsi_channel_teardown()
1944 mutex_lock(&gsi->mutex); in gsi_channel_teardown()
1954 channel_id = gsi->channel_count - 1; in gsi_channel_teardown()
1957 while (channel_id--); in gsi_channel_teardown()
1959 mutex_unlock(&gsi->mutex); in gsi_channel_teardown()
1967 const struct reg *reg; in gsi_irq_setup() local
1971 reg = gsi_reg(gsi, CNTXT_INTSET); in gsi_irq_setup()
1972 iowrite32(reg_bit(reg, INTYPE), gsi->virt + reg_offset(reg)); in gsi_irq_setup()
1977 /* Clear all type-specific interrupt masks */ in gsi_irq_setup()
1978 reg = gsi_reg(gsi, CNTXT_SRC_CH_IRQ_MSK); in gsi_irq_setup()
1979 iowrite32(0, gsi->virt + reg_offset(reg)); in gsi_irq_setup()
1981 reg = gsi_reg(gsi, CNTXT_SRC_EV_CH_IRQ_MSK); in gsi_irq_setup()
1982 iowrite32(0, gsi->virt + reg_offset(reg)); in gsi_irq_setup()
1984 reg = gsi_reg(gsi, CNTXT_GLOB_IRQ_EN); in gsi_irq_setup()
1985 iowrite32(0, gsi->virt + reg_offset(reg)); in gsi_irq_setup()
1987 reg = gsi_reg(gsi, CNTXT_SRC_IEOB_IRQ_MSK); in gsi_irq_setup()
1988 iowrite32(0, gsi->virt + reg_offset(reg)); in gsi_irq_setup()
1990 /* The inter-EE interrupts are not supported for IPA v3.0-v3.1 */ in gsi_irq_setup()
1991 if (gsi->version > IPA_VERSION_3_1) { in gsi_irq_setup()
1992 reg = gsi_reg(gsi, INTER_EE_SRC_CH_IRQ_MSK); in gsi_irq_setup()
1993 iowrite32(0, gsi->virt + reg_offset(reg)); in gsi_irq_setup()
1995 reg = gsi_reg(gsi, INTER_EE_SRC_EV_CH_IRQ_MSK); in gsi_irq_setup()
1996 iowrite32(0, gsi->virt + reg_offset(reg)); in gsi_irq_setup()
1999 reg = gsi_reg(gsi, CNTXT_GSI_IRQ_EN); in gsi_irq_setup()
2000 iowrite32(0, gsi->virt + reg_offset(reg)); in gsi_irq_setup()
2002 ret = request_irq(gsi->irq, gsi_isr, 0, "gsi", gsi); in gsi_irq_setup()
2004 dev_err(gsi->dev, "error %d requesting \"gsi\" IRQ\n", ret); in gsi_irq_setup()
2011 free_irq(gsi->irq, gsi); in gsi_irq_teardown()
2017 struct device *dev = gsi->dev; in gsi_ring_setup()
2018 const struct reg *reg; in gsi_ring_setup() local
2022 if (gsi->version < IPA_VERSION_3_5_1) { in gsi_ring_setup()
2023 /* No HW_PARAM_2 register prior to IPA v3.5.1, assume the max */ in gsi_ring_setup()
2024 gsi->channel_count = GSI_CHANNEL_COUNT_MAX; in gsi_ring_setup()
2025 gsi->evt_ring_count = GSI_EVT_RING_COUNT_MAX; in gsi_ring_setup()
2030 reg = gsi_reg(gsi, HW_PARAM_2); in gsi_ring_setup()
2031 val = ioread32(gsi->virt + reg_offset(reg)); in gsi_ring_setup()
2033 count = reg_decode(reg, NUM_CH_PER_EE, val); in gsi_ring_setup()
2036 return -EINVAL; in gsi_ring_setup()
2043 gsi->channel_count = count; in gsi_ring_setup()
2045 if (gsi->version < IPA_VERSION_5_0) { in gsi_ring_setup()
2046 count = reg_decode(reg, NUM_EV_PER_EE, val); in gsi_ring_setup()
2048 reg = gsi_reg(gsi, HW_PARAM_4); in gsi_ring_setup()
2049 count = reg_decode(reg, EV_PER_EE, val); in gsi_ring_setup()
2053 return -EINVAL; in gsi_ring_setup()
2061 gsi->evt_ring_count = count; in gsi_ring_setup()
2069 const struct reg *reg; in gsi_setup() local
2074 reg = gsi_reg(gsi, GSI_STATUS); in gsi_setup()
2075 val = ioread32(gsi->virt + reg_offset(reg)); in gsi_setup()
2076 if (!(val & reg_bit(reg, ENABLED))) { in gsi_setup()
2077 dev_err(gsi->dev, "GSI has not been enabled\n"); in gsi_setup()
2078 return -EIO; in gsi_setup()
2090 reg = gsi_reg(gsi, ERROR_LOG); in gsi_setup()
2091 iowrite32(0, gsi->virt + reg_offset(reg)); in gsi_setup()
2115 struct gsi *gsi = channel->gsi; in gsi_channel_evt_ring_init()
2122 channel->evt_ring_id = ret; in gsi_channel_evt_ring_init()
2124 evt_ring = &gsi->evt_ring[channel->evt_ring_id]; in gsi_channel_evt_ring_init()
2125 evt_ring->channel = channel; in gsi_channel_evt_ring_init()
2127 ret = gsi_ring_alloc(gsi, &evt_ring->ring, channel->event_count); in gsi_channel_evt_ring_init()
2131 dev_err(gsi->dev, "error %d allocating channel %u event ring\n", in gsi_channel_evt_ring_init()
2134 gsi_evt_ring_id_free(gsi, channel->evt_ring_id); in gsi_channel_evt_ring_init()
2142 u32 evt_ring_id = channel->evt_ring_id; in gsi_channel_evt_ring_exit()
2143 struct gsi *gsi = channel->gsi; in gsi_channel_evt_ring_exit()
2146 evt_ring = &gsi->evt_ring[evt_ring_id]; in gsi_channel_evt_ring_exit()
2147 gsi_ring_free(gsi, &evt_ring->ring); in gsi_channel_evt_ring_exit()
2155 u32 channel_id = data->channel_id; in gsi_channel_data_valid()
2156 struct device *dev = gsi->dev; in gsi_channel_data_valid()
2165 if (data->ee_id != GSI_EE_AP && data->ee_id != GSI_EE_MODEM) { in gsi_channel_data_valid()
2166 dev_err(dev, "bad EE id %u; not AP or modem\n", data->ee_id); in gsi_channel_data_valid()
2170 if (command && !data->toward_ipa) { in gsi_channel_data_valid()
2175 channel_data = &data->channel; in gsi_channel_data_valid()
2177 if (!channel_data->tlv_count || in gsi_channel_data_valid()
2178 channel_data->tlv_count > GSI_TLV_MAX) { in gsi_channel_data_valid()
2180 channel_id, channel_data->tlv_count, GSI_TLV_MAX); in gsi_channel_data_valid()
2184 if (command && IPA_COMMAND_TRANS_TRE_MAX > channel_data->tlv_count) { in gsi_channel_data_valid()
2187 channel_data->tlv_count); in gsi_channel_data_valid()
2191 /* We have to allow at least one maximally-sized transaction to in gsi_channel_data_valid()
2196 if (channel_data->tre_count < 2 * channel_data->tlv_count - 1) { in gsi_channel_data_valid()
2198 channel_id, channel_data->tlv_count, in gsi_channel_data_valid()
2199 channel_data->tre_count); in gsi_channel_data_valid()
2203 if (!is_power_of_2(channel_data->tre_count)) { in gsi_channel_data_valid()
2205 channel_id, channel_data->tre_count); in gsi_channel_data_valid()
2209 if (!is_power_of_2(channel_data->event_count)) { in gsi_channel_data_valid()
2211 channel_id, channel_data->event_count); in gsi_channel_data_valid()
2228 return -EINVAL; in gsi_channel_init_one()
2231 if (data->channel.tre_count > data->channel.event_count) { in gsi_channel_init_one()
2232 tre_count = data->channel.event_count; in gsi_channel_init_one()
2233 dev_warn(gsi->dev, "channel %u limited to %u TREs\n", in gsi_channel_init_one()
2234 data->channel_id, tre_count); in gsi_channel_init_one()
2236 tre_count = data->channel.tre_count; in gsi_channel_init_one()
2239 channel = &gsi->channel[data->channel_id]; in gsi_channel_init_one()
2242 channel->gsi = gsi; in gsi_channel_init_one()
2243 channel->toward_ipa = data->toward_ipa; in gsi_channel_init_one()
2244 channel->command = command; in gsi_channel_init_one()
2245 channel->trans_tre_max = data->channel.tlv_count; in gsi_channel_init_one()
2246 channel->tre_count = tre_count; in gsi_channel_init_one()
2247 channel->event_count = data->channel.event_count; in gsi_channel_init_one()
2253 ret = gsi_ring_alloc(gsi, &channel->tre_ring, data->channel.tre_count); in gsi_channel_init_one()
2255 dev_err(gsi->dev, "error %d allocating channel %u ring\n", in gsi_channel_init_one()
2256 ret, data->channel_id); in gsi_channel_init_one()
2260 ret = gsi_channel_trans_init(gsi, data->channel_id); in gsi_channel_init_one()
2265 u32 tre_max = gsi_channel_tre_max(gsi, data->channel_id); in gsi_channel_init_one()
2274 gsi_ring_free(gsi, &channel->tre_ring); in gsi_channel_init_one()
2278 channel->gsi = NULL; /* Mark it not (fully) initialized */ in gsi_channel_init_one()
2289 if (channel->command) in gsi_channel_exit_one()
2292 gsi_ring_free(channel->gsi, &channel->tre_ring); in gsi_channel_exit_one()
2304 /* IPA v4.2 requires the AP to allocate channels for the modem */ in gsi_channel_init()
2305 modem_alloc = gsi->version == IPA_VERSION_4_2; in gsi_channel_init()
2307 gsi->event_bitmap = gsi_event_bitmap_init(GSI_EVT_RING_COUNT_MAX); in gsi_channel_init()
2308 gsi->ieob_enabled_bitmap = 0; in gsi_channel_init()
2320 gsi->modem_channel_bitmap |= in gsi_channel_init()
2333 while (i--) { in gsi_channel_init()
2337 gsi->modem_channel_bitmap &= ~BIT(data[i].channel_id); in gsi_channel_init()
2340 gsi_channel_exit_one(&gsi->channel[data->channel_id]); in gsi_channel_init()
2349 u32 channel_id = GSI_CHANNEL_COUNT_MAX - 1; in gsi_channel_exit()
2352 gsi_channel_exit_one(&gsi->channel[channel_id]); in gsi_channel_exit()
2353 while (channel_id--); in gsi_channel_exit()
2354 gsi->modem_channel_bitmap = 0; in gsi_channel_exit()
2366 gsi->dev = &pdev->dev; in gsi_init()
2367 gsi->version = version; in gsi_init()
2372 init_dummy_netdev(&gsi->dummy_dev); in gsi_init()
2373 init_completion(&gsi->completion); in gsi_init()
2387 mutex_init(&gsi->mutex); in gsi_init()
2400 mutex_destroy(&gsi->mutex); in gsi_exit()
2413 * would be (tre_count - 1).
2421 * a pool to avoid crossing that power-of-2 boundary, and this can
2427 struct gsi_channel *channel = &gsi->channel[channel_id]; in gsi_channel_tre_max()
2429 /* Hardware limit is channel->tre_count - 1 */ in gsi_channel_tre_max()
2430 return channel->tre_count - (channel->trans_tre_max - 1); in gsi_channel_tre_max()