Lines Matching +full:wait +full:- +full:on +full:- +full:write

1 /* SPDX-License-Identifier: GPL-2.0 */
6 /* Write Register 0 */
28 #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
37 /* Write Register 1 */
44 #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
45 #define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */
46 #define INT_ERR_Rx 0x18 /* Int on error only */
48 #define WT_RDY_RT 0x20 /* Wait/Ready on R/T */
49 #define WT_FN_RDYFN 0x40 /* Wait/FN/Ready FN */
50 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
52 /* Write Register #2 (Interrupt Vector) */
54 /* Write Register 3 */
67 /* Write Register 4 */
87 /* Write Register 5 */
91 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
100 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
102 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
104 /* Write Register 8 (transmit buffer) */
106 /* Write Register 9 (Master interrupt control) */
112 #define NORESET 0 /* No reset on write to R9 */
117 /* Write Register 10 (misc control bits) */
120 #define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */
121 #define MARKIDLE 8 /* Mark/flag on idle */
122 #define GAOP 0x10 /* Go active on poll */
129 /* Write Register 11 (Clock Mode control) */
145 /* Write Register 12 (lower byte of baud rate generator time constant) */
147 /* Write Register 13 (upper byte of baud rate generator time constant) */
149 /* Write Register 14 (Misc control bits) */
163 /* Write Register 15 (external/status interrupt control) */
199 /* Read Register 2 (channel b only) - Interrupt vector */
212 #define ONLOOP 2 /* On loop */
225 /* Write Register 7' (SDLC/HDLC Programmable Enhancements) */
230 #define RXFIFOH 0x08 /* Z85230: Int on RX FIFO half full */
233 #define TXFIFOE 0x20 /* Z85230: Int on TX FIFO completely empty */
236 /* Write Register 15 (external/status interrupt control) */