Lines Matching +full:sync +full:- +full:read

1 /* SPDX-License-Identifier: GPL-2.0 */
57 #define	SYNC_L_INH	0x2	/* Sync Character Load Inhibit */
72 #define	SYNC_ENAB	0	/* Sync Modes Enable */
77 #define	MONSYNC		0	/* 8 Bit Sync character */
78 #define	BISYNC		0x10	/* 16 bit sync character */
79 #define	SDLC		0x20	/* SDLC Mode (01111110 Sync Flag) */
80 #define	EXTSYNC		0x30	/* External Sync Mode */
91 #define	SDLC_CRC	0x4	/* SDLC/CRC-16 */
100 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
102 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
118 #define	BIT6	1	/* 6 bit/8bit sync */
166 #define	SYNCIE	0x10	/* Sync/hunt IE */
172 /* Read Register 0 */
177 #define	SYNC_HUNT	0x10	/* Sync/hunt */
182 /* Read Register 1 */
199 /* Read Register 2 (channel b only) - Interrupt vector */
201 /* Read Register 3 (interrupt pending register) ch a only */
209 /* Read Register 8 (receive data register) */
211 /* Read Register 10  (misc status bits) */
217 /* Read Register 12 (lower byte of baud rate generator constant) */
219 /* Read Register 13 (upper byte of baud rate generator constant) */
221 /* Read Register 15 (value of WR 15) */
234 #define EXTRDEN	0x40		/* Extended Read Enabled */
240 /* Read Register 6 (frame status FIFO) */
243 /* Read Register 7 (frame status FIFO) */