Lines Matching +full:rx +full:- +full:tx +full:- +full:swap
1 // SPDX-License-Identifier: GPL-2.0-only
24 * 0 => MSI-X
30 /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
34 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
62 netif_warn(efx, probe, efx->net_dev, in count_online_cores()
70 cpumask_of_pcibus(efx->pci_dev->bus)); in count_online_cores()
98 netif_cond_dbg(efx, probe, efx->net_dev, !efx_siena_rss_cpus, in efx_wanted_parallelism()
100 "Reducing number of rx queues from %u to %u.\n", in efx_wanted_parallelism()
109 if (efx->type->sriov_wanted) { in efx_wanted_parallelism()
110 if (efx->type->sriov_wanted(efx) && efx_vf_size(efx) > 1 && in efx_wanted_parallelism()
112 netif_warn(efx, probe, efx->net_dev, in efx_wanted_parallelism()
114 "VF support. Increase vf-msix-limit to use more " in efx_wanted_parallelism()
141 * we allocate a TX queue per CPU. We share event queues across in efx_allocate_msix_channels()
142 * multiple tx queues, assuming tx and ev queues are both in efx_allocate_msix_channels()
150 vec_count = pci_msix_vec_count(efx->pci_dev); in efx_allocate_msix_channels()
157 * We need a channel per event queue, plus a VI per tx queue. in efx_allocate_msix_channels()
161 efx->xdp_txq_queues_mode = EFX_XDP_TX_QUEUES_BORROWED; in efx_allocate_msix_channels()
162 netif_warn(efx, drv, efx->net_dev, in efx_allocate_msix_channels()
165 netif_warn(efx, drv, efx->net_dev, in efx_allocate_msix_channels()
167 } else if (n_channels + n_xdp_tx > efx->max_vis) { in efx_allocate_msix_channels()
168 efx->xdp_txq_queues_mode = EFX_XDP_TX_QUEUES_BORROWED; in efx_allocate_msix_channels()
169 netif_warn(efx, drv, efx->net_dev, in efx_allocate_msix_channels()
170 "Insufficient resources for %d XDP TX queues (%d other channels, max VIs %d)\n", in efx_allocate_msix_channels()
171 n_xdp_tx, n_channels, efx->max_vis); in efx_allocate_msix_channels()
172 netif_warn(efx, drv, efx->net_dev, in efx_allocate_msix_channels()
175 efx->xdp_txq_queues_mode = EFX_XDP_TX_QUEUES_SHARED; in efx_allocate_msix_channels()
176 netif_warn(efx, drv, efx->net_dev, in efx_allocate_msix_channels()
180 n_xdp_ev = max_channels - n_channels; in efx_allocate_msix_channels()
181 netif_warn(efx, drv, efx->net_dev, in efx_allocate_msix_channels()
185 efx->xdp_txq_queues_mode = EFX_XDP_TX_QUEUES_DEDICATED; in efx_allocate_msix_channels()
188 if (efx->xdp_txq_queues_mode != EFX_XDP_TX_QUEUES_BORROWED) { in efx_allocate_msix_channels()
189 efx->n_xdp_channels = n_xdp_ev; in efx_allocate_msix_channels()
190 efx->xdp_tx_per_channel = tx_per_ev; in efx_allocate_msix_channels()
191 efx->xdp_tx_queue_count = n_xdp_tx; in efx_allocate_msix_channels()
193 netif_dbg(efx, drv, efx->net_dev, in efx_allocate_msix_channels()
194 "Allocating %d TX and %d event queues for XDP\n", in efx_allocate_msix_channels()
197 efx->n_xdp_channels = 0; in efx_allocate_msix_channels()
198 efx->xdp_tx_per_channel = 0; in efx_allocate_msix_channels()
199 efx->xdp_tx_queue_count = n_xdp_tx; in efx_allocate_msix_channels()
203 netif_err(efx, drv, efx->net_dev, in efx_allocate_msix_channels()
204 "WARNING: Insufficient MSI-X vectors available (%d < %u).\n", in efx_allocate_msix_channels()
206 netif_err(efx, drv, efx->net_dev, in efx_allocate_msix_channels()
213 efx->n_channels = n_channels; in efx_allocate_msix_channels()
215 /* Ignore XDP tx channels when creating rx channels. */ in efx_allocate_msix_channels()
216 n_channels -= efx->n_xdp_channels; in efx_allocate_msix_channels()
219 efx->n_tx_channels = in efx_allocate_msix_channels()
221 efx->max_tx_channels); in efx_allocate_msix_channels()
222 efx->tx_channel_offset = in efx_allocate_msix_channels()
223 n_channels - efx->n_tx_channels; in efx_allocate_msix_channels()
224 efx->n_rx_channels = in efx_allocate_msix_channels()
225 max(n_channels - in efx_allocate_msix_channels()
226 efx->n_tx_channels, 1U); in efx_allocate_msix_channels()
228 efx->n_tx_channels = min(n_channels, efx->max_tx_channels); in efx_allocate_msix_channels()
229 efx->tx_channel_offset = 0; in efx_allocate_msix_channels()
230 efx->n_rx_channels = n_channels; in efx_allocate_msix_channels()
233 efx->n_rx_channels = min(efx->n_rx_channels, parallelism); in efx_allocate_msix_channels()
234 efx->n_tx_channels = min(efx->n_tx_channels, parallelism); in efx_allocate_msix_channels()
236 efx->xdp_channel_offset = n_channels; in efx_allocate_msix_channels()
238 netif_dbg(efx, drv, efx->net_dev, in efx_allocate_msix_channels()
239 "Allocating %u RX channels\n", in efx_allocate_msix_channels()
240 efx->n_rx_channels); in efx_allocate_msix_channels()
242 return efx->n_channels; in efx_allocate_msix_channels()
246 * the resulting numbers of channels and RX queues.
256 if (efx->extra_channel_type[i]) in efx_siena_probe_interrupts()
259 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { in efx_siena_probe_interrupts()
264 rc = efx_allocate_msix_channels(efx, efx->max_channels, in efx_siena_probe_interrupts()
270 rc = pci_enable_msix_range(efx->pci_dev, xentries, 1, in efx_siena_probe_interrupts()
275 netif_err(efx, drv, efx->net_dev, in efx_siena_probe_interrupts()
276 "could not enable MSI-X\n"); in efx_siena_probe_interrupts()
277 if (efx->type->min_interrupt_mode >= EFX_INT_MODE_MSI) in efx_siena_probe_interrupts()
278 efx->interrupt_mode = EFX_INT_MODE_MSI; in efx_siena_probe_interrupts()
282 netif_err(efx, drv, efx->net_dev, in efx_siena_probe_interrupts()
283 "WARNING: Insufficient MSI-X vectors" in efx_siena_probe_interrupts()
285 netif_err(efx, drv, efx->net_dev, in efx_siena_probe_interrupts()
291 for (i = 0; i < efx->n_channels; i++) in efx_siena_probe_interrupts()
292 efx_get_channel(efx, i)->irq = in efx_siena_probe_interrupts()
298 if (efx->interrupt_mode == EFX_INT_MODE_MSI) { in efx_siena_probe_interrupts()
299 efx->n_channels = 1; in efx_siena_probe_interrupts()
300 efx->n_rx_channels = 1; in efx_siena_probe_interrupts()
301 efx->n_tx_channels = 1; in efx_siena_probe_interrupts()
302 efx->tx_channel_offset = 0; in efx_siena_probe_interrupts()
303 efx->n_xdp_channels = 0; in efx_siena_probe_interrupts()
304 efx->xdp_channel_offset = efx->n_channels; in efx_siena_probe_interrupts()
305 efx->xdp_txq_queues_mode = EFX_XDP_TX_QUEUES_BORROWED; in efx_siena_probe_interrupts()
306 rc = pci_enable_msi(efx->pci_dev); in efx_siena_probe_interrupts()
308 efx_get_channel(efx, 0)->irq = efx->pci_dev->irq; in efx_siena_probe_interrupts()
310 netif_err(efx, drv, efx->net_dev, in efx_siena_probe_interrupts()
312 if (efx->type->min_interrupt_mode >= EFX_INT_MODE_LEGACY) in efx_siena_probe_interrupts()
313 efx->interrupt_mode = EFX_INT_MODE_LEGACY; in efx_siena_probe_interrupts()
320 if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { in efx_siena_probe_interrupts()
321 efx->n_channels = 1 + (efx_siena_separate_tx_channels ? 1 : 0); in efx_siena_probe_interrupts()
322 efx->n_rx_channels = 1; in efx_siena_probe_interrupts()
323 efx->n_tx_channels = 1; in efx_siena_probe_interrupts()
324 efx->tx_channel_offset = efx_siena_separate_tx_channels ? 1 : 0; in efx_siena_probe_interrupts()
325 efx->n_xdp_channels = 0; in efx_siena_probe_interrupts()
326 efx->xdp_channel_offset = efx->n_channels; in efx_siena_probe_interrupts()
327 efx->xdp_txq_queues_mode = EFX_XDP_TX_QUEUES_BORROWED; in efx_siena_probe_interrupts()
328 efx->legacy_irq = efx->pci_dev->irq; in efx_siena_probe_interrupts()
332 efx->n_extra_tx_channels = 0; in efx_siena_probe_interrupts()
333 j = efx->xdp_channel_offset; in efx_siena_probe_interrupts()
335 if (!efx->extra_channel_type[i]) in efx_siena_probe_interrupts()
337 if (j <= efx->tx_channel_offset + efx->n_tx_channels) { in efx_siena_probe_interrupts()
338 efx->extra_channel_type[i]->handle_no_channel(efx); in efx_siena_probe_interrupts()
340 --j; in efx_siena_probe_interrupts()
341 efx_get_channel(efx, j)->type = in efx_siena_probe_interrupts()
342 efx->extra_channel_type[i]; in efx_siena_probe_interrupts()
344 efx->n_extra_tx_channels++; in efx_siena_probe_interrupts()
348 rss_spread = efx->n_rx_channels; in efx_siena_probe_interrupts()
351 if (efx->type->sriov_wanted) { in efx_siena_probe_interrupts()
352 efx->rss_spread = ((rss_spread > 1 || in efx_siena_probe_interrupts()
353 !efx->type->sriov_wanted(efx)) ? in efx_siena_probe_interrupts()
358 efx->rss_spread = rss_spread; in efx_siena_probe_interrupts()
366 const struct cpumask *numa_mask = cpumask_of_pcibus(efx->pci_dev->bus); in efx_siena_set_interrupt_affinity()
374 cpu = -1; in efx_siena_set_interrupt_affinity()
379 irq_set_affinity_hint(channel->irq, cpumask_of(cpu)); in efx_siena_set_interrupt_affinity()
388 irq_set_affinity_hint(channel->irq, NULL); in efx_siena_clear_interrupt_affinity()
406 /* Remove MSI/MSI-X interrupts */ in efx_siena_remove_interrupts()
408 channel->irq = 0; in efx_siena_remove_interrupts()
409 pci_disable_msi(efx->pci_dev); in efx_siena_remove_interrupts()
410 pci_disable_msix(efx->pci_dev); in efx_siena_remove_interrupts()
413 efx->legacy_irq = 0; in efx_siena_remove_interrupts()
427 struct efx_nic *efx = channel->efx; in efx_probe_eventq()
430 netif_dbg(efx, probe, efx->net_dev, in efx_probe_eventq()
431 "chan %d create event queue\n", channel->channel); in efx_probe_eventq()
433 /* Build an event queue with room for one event per tx and rx buffer, in efx_probe_eventq()
436 entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128); in efx_probe_eventq()
438 channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1; in efx_probe_eventq()
446 struct efx_nic *efx = channel->efx; in efx_init_eventq()
449 EFX_WARN_ON_PARANOID(channel->eventq_init); in efx_init_eventq()
451 netif_dbg(efx, drv, efx->net_dev, in efx_init_eventq()
452 "chan %d init event queue\n", channel->channel); in efx_init_eventq()
456 efx->type->push_irq_moderation(channel); in efx_init_eventq()
457 channel->eventq_read_ptr = 0; in efx_init_eventq()
458 channel->eventq_init = true; in efx_init_eventq()
466 netif_dbg(channel->efx, ifup, channel->efx->net_dev, in efx_siena_start_eventq()
467 "chan %d start event queue\n", channel->channel); in efx_siena_start_eventq()
470 channel->enabled = true; in efx_siena_start_eventq()
473 napi_enable(&channel->napi_str); in efx_siena_start_eventq()
480 if (!channel->enabled) in efx_siena_stop_eventq()
483 napi_disable(&channel->napi_str); in efx_siena_stop_eventq()
484 channel->enabled = false; in efx_siena_stop_eventq()
489 if (!channel->eventq_init) in efx_fini_eventq()
492 netif_dbg(channel->efx, drv, channel->efx->net_dev, in efx_fini_eventq()
493 "chan %d fini event queue\n", channel->channel); in efx_fini_eventq()
496 channel->eventq_init = false; in efx_fini_eventq()
501 netif_dbg(channel->efx, drv, channel->efx->net_dev, in efx_remove_eventq()
502 "chan %d remove event queue\n", channel->channel); in efx_remove_eventq()
521 time = jiffies - channel->rfs_last_expiry; in efx_filter_rfs_expire()
522 quota = channel->rfs_filter_count * time / (30 * HZ); in efx_filter_rfs_expire()
524 min(channel->rfs_filter_count, quota))) in efx_filter_rfs_expire()
525 channel->rfs_last_expiry += time; in efx_filter_rfs_expire()
543 channel->efx = efx; in efx_alloc_channel()
544 channel->channel = i; in efx_alloc_channel()
545 channel->type = &efx_default_channel_type; in efx_alloc_channel()
548 tx_queue = &channel->tx_queue[j]; in efx_alloc_channel()
549 tx_queue->efx = efx; in efx_alloc_channel()
550 tx_queue->queue = -1; in efx_alloc_channel()
551 tx_queue->label = j; in efx_alloc_channel()
552 tx_queue->channel = channel; in efx_alloc_channel()
556 INIT_DELAYED_WORK(&channel->filter_work, efx_filter_rfs_expire); in efx_alloc_channel()
559 rx_queue = &channel->rx_queue; in efx_alloc_channel()
560 rx_queue->efx = efx; in efx_alloc_channel()
561 timer_setup(&rx_queue->slow_fill, efx_siena_rx_slow_fill, 0); in efx_alloc_channel()
571 efx->channel[i] = efx_alloc_channel(efx, i); in efx_siena_init_channels()
572 if (!efx->channel[i]) in efx_siena_init_channels()
573 return -ENOMEM; in efx_siena_init_channels()
574 efx->msi_context[i].efx = efx; in efx_siena_init_channels()
575 efx->msi_context[i].index = i; in efx_siena_init_channels()
579 efx->interrupt_mode = min(efx->type->min_interrupt_mode, in efx_siena_init_channels()
582 efx->max_channels = EFX_MAX_CHANNELS; in efx_siena_init_channels()
583 efx->max_tx_channels = EFX_MAX_CHANNELS; in efx_siena_init_channels()
593 if (efx->channel[i]) { in efx_siena_fini_channels()
594 kfree(efx->channel[i]); in efx_siena_fini_channels()
595 efx->channel[i] = NULL; in efx_siena_fini_channels()
616 channel->napi_dev = NULL; in efx_copy_channel()
617 INIT_HLIST_NODE(&channel->napi_str.napi_hash_node); in efx_copy_channel()
618 channel->napi_str.napi_id = 0; in efx_copy_channel()
619 channel->napi_str.state = 0; in efx_copy_channel()
620 memset(&channel->eventq, 0, sizeof(channel->eventq)); in efx_copy_channel()
623 tx_queue = &channel->tx_queue[j]; in efx_copy_channel()
624 if (tx_queue->channel) in efx_copy_channel()
625 tx_queue->channel = channel; in efx_copy_channel()
626 tx_queue->buffer = NULL; in efx_copy_channel()
627 tx_queue->cb_page = NULL; in efx_copy_channel()
628 memset(&tx_queue->txd, 0, sizeof(tx_queue->txd)); in efx_copy_channel()
631 rx_queue = &channel->rx_queue; in efx_copy_channel()
632 rx_queue->buffer = NULL; in efx_copy_channel()
633 memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd)); in efx_copy_channel()
634 timer_setup(&rx_queue->slow_fill, efx_siena_rx_slow_fill, 0); in efx_copy_channel()
636 INIT_DELAYED_WORK(&channel->filter_work, efx_filter_rfs_expire); in efx_copy_channel()
648 netif_dbg(channel->efx, probe, channel->efx->net_dev, in efx_probe_channel()
649 "creating channel %d\n", channel->channel); in efx_probe_channel()
651 rc = channel->type->pre_probe(channel); in efx_probe_channel()
671 channel->rx_list = NULL; in efx_probe_channel()
683 struct efx_nic *efx = channel->efx; in efx_get_channel_name()
687 number = channel->channel; in efx_get_channel_name()
689 if (number >= efx->xdp_channel_offset && in efx_get_channel_name()
690 !WARN_ON_ONCE(!efx->n_xdp_channels)) { in efx_get_channel_name()
691 type = "-xdp"; in efx_get_channel_name()
692 number -= efx->xdp_channel_offset; in efx_get_channel_name()
693 } else if (efx->tx_channel_offset == 0) { in efx_get_channel_name()
695 } else if (number < efx->tx_channel_offset) { in efx_get_channel_name()
696 type = "-rx"; in efx_get_channel_name()
698 type = "-tx"; in efx_get_channel_name()
699 number -= efx->tx_channel_offset; in efx_get_channel_name()
701 snprintf(buf, len, "%s%s-%d", efx->name, type, number); in efx_get_channel_name()
709 channel->type->get_name(channel, in efx_siena_set_channel_names()
710 efx->msi_context[channel->channel].name, in efx_siena_set_channel_names()
711 sizeof(efx->msi_context[0].name)); in efx_siena_set_channel_names()
720 efx->next_buffer_table = 0; in efx_siena_probe_channels()
730 netif_err(efx, probe, efx->net_dev, in efx_siena_probe_channels()
732 channel->channel); in efx_siena_probe_channels()
750 netif_dbg(channel->efx, drv, channel->efx->net_dev, in efx_siena_remove_channel()
751 "destroy chan %d\n", channel->channel); in efx_siena_remove_channel()
758 channel->type->post_remove(channel); in efx_siena_remove_channel()
768 kfree(efx->xdp_tx_queues); in efx_siena_remove_channels()
774 if (xdp_queue_number >= efx->xdp_tx_queue_count) in efx_set_xdp_tx_queue()
775 return -EINVAL; in efx_set_xdp_tx_queue()
777 netif_dbg(efx, drv, efx->net_dev, in efx_set_xdp_tx_queue()
779 tx_queue->channel->channel, tx_queue->label, in efx_set_xdp_tx_queue()
780 xdp_queue_number, tx_queue->queue); in efx_set_xdp_tx_queue()
781 efx->xdp_tx_queues[xdp_queue_number] = tx_queue; in efx_set_xdp_tx_queue()
793 /* We need to mark which channels really have RX and TX in efx_set_xdp_channels()
794 * queues, and adjust the TX queue numbers if we have separate in efx_set_xdp_channels()
795 * RX-only and TX-only channels. in efx_set_xdp_channels()
798 if (channel->channel < efx->tx_channel_offset) in efx_set_xdp_channels()
803 tx_queue->queue = next_queue++; in efx_set_xdp_channels()
811 tx_queue->queue = next_queue++; in efx_set_xdp_channels()
812 netif_dbg(efx, drv, efx->net_dev, in efx_set_xdp_channels()
814 channel->channel, tx_queue->label, in efx_set_xdp_channels()
815 tx_queue->queue); in efx_set_xdp_channels()
823 if (efx->xdp_txq_queues_mode == in efx_set_xdp_channels()
825 tx_queue = &channel->tx_queue[0]; in efx_set_xdp_channels()
833 WARN_ON(efx->xdp_txq_queues_mode == EFX_XDP_TX_QUEUES_DEDICATED && in efx_set_xdp_channels()
834 xdp_queue_number != efx->xdp_tx_queue_count); in efx_set_xdp_channels()
835 WARN_ON(efx->xdp_txq_queues_mode != EFX_XDP_TX_QUEUES_DEDICATED && in efx_set_xdp_channels()
836 xdp_queue_number > efx->xdp_tx_queue_count); in efx_set_xdp_channels()
838 /* If we have more CPUs than assigned XDP TX queues, assign the already in efx_set_xdp_channels()
842 while (xdp_queue_number < efx->xdp_tx_queue_count) { in efx_set_xdp_channels()
843 tx_queue = efx->xdp_tx_queues[next_queue++]; in efx_set_xdp_channels()
874 if (channel->type->copy) in efx_siena_realloc_channels()
877 channel->eventq.index + in efx_siena_realloc_channels()
878 channel->eventq.entries); in efx_siena_realloc_channels()
881 rx_queue->rxd.index + in efx_siena_realloc_channels()
882 rx_queue->rxd.entries); in efx_siena_realloc_channels()
885 tx_queue->txd.index + in efx_siena_realloc_channels()
886 tx_queue->txd.entries); in efx_siena_realloc_channels()
895 for (i = 0; i < efx->n_channels; i++) { in efx_siena_realloc_channels()
896 channel = efx->channel[i]; in efx_siena_realloc_channels()
897 if (channel->type->copy) in efx_siena_realloc_channels()
898 channel = channel->type->copy(channel); in efx_siena_realloc_channels()
900 rc = -ENOMEM; in efx_siena_realloc_channels()
906 /* Swap entry counts and channel pointers */ in efx_siena_realloc_channels()
907 old_rxq_entries = efx->rxq_entries; in efx_siena_realloc_channels()
908 old_txq_entries = efx->txq_entries; in efx_siena_realloc_channels()
909 efx->rxq_entries = rxq_entries; in efx_siena_realloc_channels()
910 efx->txq_entries = txq_entries; in efx_siena_realloc_channels()
911 for (i = 0; i < efx->n_channels; i++) in efx_siena_realloc_channels()
912 swap(efx->channel[i], other_channel[i]); in efx_siena_realloc_channels()
915 efx->next_buffer_table = next_buffer_table; in efx_siena_realloc_channels()
917 for (i = 0; i < efx->n_channels; i++) { in efx_siena_realloc_channels()
918 channel = efx->channel[i]; in efx_siena_realloc_channels()
919 if (!channel->type->copy) in efx_siena_realloc_channels()
924 efx_init_napi_channel(efx->channel[i]); in efx_siena_realloc_channels()
930 for (i = 0; i < efx->n_channels; i++) { in efx_siena_realloc_channels()
932 if (channel && channel->type->copy) { in efx_siena_realloc_channels()
942 netif_err(efx, drv, efx->net_dev, in efx_siena_realloc_channels()
952 /* Swap back */ in efx_siena_realloc_channels()
953 efx->rxq_entries = old_rxq_entries; in efx_siena_realloc_channels()
954 efx->txq_entries = old_txq_entries; in efx_siena_realloc_channels()
955 for (i = 0; i < efx->n_channels; i++) in efx_siena_realloc_channels()
956 swap(efx->channel[i], other_channel[i]); in efx_siena_realloc_channels()
965 if (efx->xdp_tx_queue_count) { in efx_siena_set_channels()
966 EFX_WARN_ON_PARANOID(efx->xdp_tx_queues); in efx_siena_set_channels()
968 /* Allocate array for XDP TX queue lookup. */ in efx_siena_set_channels()
969 efx->xdp_tx_queues = kcalloc(efx->xdp_tx_queue_count, in efx_siena_set_channels()
970 sizeof(*efx->xdp_tx_queues), in efx_siena_set_channels()
972 if (!efx->xdp_tx_queues) in efx_siena_set_channels()
973 return -ENOMEM; in efx_siena_set_channels()
977 if (channel->channel < efx->n_rx_channels) in efx_siena_set_channels()
978 channel->rx_queue.core_index = channel->channel; in efx_siena_set_channels()
980 channel->rx_queue.core_index = -1; in efx_siena_set_channels()
985 rc = netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels); in efx_siena_set_channels()
988 return netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels); in efx_siena_set_channels()
993 return channel->channel - channel->efx->tx_channel_offset < in efx_default_channel_want_txqs()
994 channel->efx->n_tx_channels; in efx_default_channel_want_txqs()
1006 BUG_ON(efx->state == STATE_DISABLED); in efx_soft_enable_interrupts()
1008 efx->irq_soft_enabled = true; in efx_soft_enable_interrupts()
1012 if (!channel->type->keep_eventq) { in efx_soft_enable_interrupts()
1029 if (!channel->type->keep_eventq) in efx_soft_enable_interrupts()
1040 if (efx->state == STATE_DISABLED) in efx_soft_disable_interrupts()
1045 efx->irq_soft_enabled = false; in efx_soft_disable_interrupts()
1048 if (efx->legacy_irq) in efx_soft_disable_interrupts()
1049 synchronize_irq(efx->legacy_irq); in efx_soft_disable_interrupts()
1052 if (channel->irq) in efx_soft_disable_interrupts()
1053 synchronize_irq(channel->irq); in efx_soft_disable_interrupts()
1056 if (!channel->type->keep_eventq) in efx_soft_disable_interrupts()
1070 BUG_ON(efx->state == STATE_DISABLED); in efx_siena_enable_interrupts()
1072 if (efx->eeh_disabled_legacy_irq) { in efx_siena_enable_interrupts()
1073 enable_irq(efx->legacy_irq); in efx_siena_enable_interrupts()
1074 efx->eeh_disabled_legacy_irq = false; in efx_siena_enable_interrupts()
1077 efx->type->irq_enable_master(efx); in efx_siena_enable_interrupts()
1080 if (channel->type->keep_eventq) { in efx_siena_enable_interrupts()
1098 if (channel->type->keep_eventq) in efx_siena_enable_interrupts()
1102 efx->type->irq_disable_non_ev(efx); in efx_siena_enable_interrupts()
1114 if (channel->type->keep_eventq) in efx_siena_disable_interrupts()
1118 efx->type->irq_disable_non_ev(efx); in efx_siena_disable_interrupts()
1130 atomic_inc(&efx->active_queues); in efx_siena_start_channels()
1135 atomic_inc(&efx->active_queues); in efx_siena_start_channels()
1141 WARN_ON(channel->rx_pkt_n_frags); in efx_siena_start_channels()
1152 /* Stop RX refill */ in efx_siena_stop_channels()
1155 rx_queue->refill_enabled = false; in efx_siena_stop_channels()
1159 /* RX packet processing is pipelined, so wait for the in efx_siena_stop_channels()
1161 * might be kept active by non-data events, so don't in efx_siena_stop_channels()
1171 if (efx->type->fini_dmaq) in efx_siena_stop_channels()
1172 rc = efx->type->fini_dmaq(efx); in efx_siena_stop_channels()
1175 netif_err(efx, drv, efx->net_dev, "failed to flush queues\n"); in efx_siena_stop_channels()
1177 netif_dbg(efx, drv, efx->net_dev, in efx_siena_stop_channels()
1208 if (unlikely(!channel->enabled)) in efx_process_channel()
1212 EFX_WARN_ON_PARANOID(channel->rx_list != NULL); in efx_process_channel()
1214 channel->rx_list = &rx_list; in efx_process_channel()
1217 tx_queue->pkts_compl = 0; in efx_process_channel()
1218 tx_queue->bytes_compl = 0; in efx_process_channel()
1232 if (tx_queue->bytes_compl) { in efx_process_channel()
1233 netdev_tx_completed_queue(tx_queue->core_txq, in efx_process_channel()
1234 tx_queue->pkts_compl, in efx_process_channel()
1235 tx_queue->bytes_compl); in efx_process_channel()
1240 netif_receive_skb_list(channel->rx_list); in efx_process_channel()
1241 channel->rx_list = NULL; in efx_process_channel()
1248 int step = efx->irq_mod_step_us; in efx_update_irq_mod()
1250 if (channel->irq_mod_score < irq_adapt_low_thresh) { in efx_update_irq_mod()
1251 if (channel->irq_moderation_us > step) { in efx_update_irq_mod()
1252 channel->irq_moderation_us -= step; in efx_update_irq_mod()
1253 efx->type->push_irq_moderation(channel); in efx_update_irq_mod()
1255 } else if (channel->irq_mod_score > irq_adapt_high_thresh) { in efx_update_irq_mod()
1256 if (channel->irq_moderation_us < in efx_update_irq_mod()
1257 efx->irq_rx_moderation_us) { in efx_update_irq_mod()
1258 channel->irq_moderation_us += step; in efx_update_irq_mod()
1259 efx->type->push_irq_moderation(channel); in efx_update_irq_mod()
1263 channel->irq_count = 0; in efx_update_irq_mod()
1264 channel->irq_mod_score = 0; in efx_update_irq_mod()
1276 struct efx_nic *efx = channel->efx; in efx_poll()
1282 netif_vdbg(efx, intr, efx->net_dev, in efx_poll()
1284 channel->channel, raw_smp_processor_id()); in efx_poll()
1292 efx->irq_rx_adaptive && in efx_poll()
1293 unlikely(++channel->irq_count == 1000)) { in efx_poll()
1299 time = jiffies - channel->rfs_last_expiry; in efx_poll()
1301 if (channel->rfs_filter_count * time >= 600 * HZ) in efx_poll()
1302 mod_delayed_work(system_wq, &channel->filter_work, 0); in efx_poll()
1319 struct efx_nic *efx = channel->efx; in efx_init_napi_channel()
1321 channel->napi_dev = efx->net_dev; in efx_init_napi_channel()
1322 netif_napi_add(channel->napi_dev, &channel->napi_str, efx_poll); in efx_init_napi_channel()
1335 if (channel->napi_dev) in efx_fini_napi_channel()
1336 netif_napi_del(&channel->napi_str); in efx_fini_napi_channel()
1338 channel->napi_dev = NULL; in efx_fini_napi_channel()