Lines Matching +full:0 +full:x10100
20 QLCNIC_HW_H0_CH_HUB_ADR = 0x05,
21 QLCNIC_HW_H1_CH_HUB_ADR = 0x0E,
22 QLCNIC_HW_H2_CH_HUB_ADR = 0x03,
23 QLCNIC_HW_H3_CH_HUB_ADR = 0x01,
24 QLCNIC_HW_H4_CH_HUB_ADR = 0x06,
25 QLCNIC_HW_H5_CH_HUB_ADR = 0x07,
26 QLCNIC_HW_H6_CH_HUB_ADR = 0x08
29 /* Hub 0 */
31 QLCNIC_HW_MN_CRB_AGT_ADR = 0x15,
32 QLCNIC_HW_MS_CRB_AGT_ADR = 0x25
37 QLCNIC_HW_PS_CRB_AGT_ADR = 0x73,
38 QLCNIC_HW_SS_CRB_AGT_ADR = 0x20,
39 QLCNIC_HW_RPMX3_CRB_AGT_ADR = 0x0b,
40 QLCNIC_HW_QMS_CRB_AGT_ADR = 0x00,
41 QLCNIC_HW_SQGS0_CRB_AGT_ADR = 0x01,
42 QLCNIC_HW_SQGS1_CRB_AGT_ADR = 0x02,
43 QLCNIC_HW_SQGS2_CRB_AGT_ADR = 0x03,
44 QLCNIC_HW_SQGS3_CRB_AGT_ADR = 0x04,
45 QLCNIC_HW_C2C0_CRB_AGT_ADR = 0x58,
46 QLCNIC_HW_C2C1_CRB_AGT_ADR = 0x59,
47 QLCNIC_HW_C2C2_CRB_AGT_ADR = 0x5a,
48 QLCNIC_HW_RPMX2_CRB_AGT_ADR = 0x0a,
49 QLCNIC_HW_RPMX4_CRB_AGT_ADR = 0x0c,
50 QLCNIC_HW_RPMX7_CRB_AGT_ADR = 0x0f,
51 QLCNIC_HW_RPMX9_CRB_AGT_ADR = 0x12,
52 QLCNIC_HW_SMB_CRB_AGT_ADR = 0x18
57 QLCNIC_HW_NIU_CRB_AGT_ADR = 0x31,
58 QLCNIC_HW_I2C0_CRB_AGT_ADR = 0x19,
59 QLCNIC_HW_I2C1_CRB_AGT_ADR = 0x29,
61 QLCNIC_HW_SN_CRB_AGT_ADR = 0x10,
62 QLCNIC_HW_I2Q_CRB_AGT_ADR = 0x20,
63 QLCNIC_HW_LPC_CRB_AGT_ADR = 0x22,
64 QLCNIC_HW_ROMUSB_CRB_AGT_ADR = 0x21,
65 QLCNIC_HW_QM_CRB_AGT_ADR = 0x66,
66 QLCNIC_HW_SQG0_CRB_AGT_ADR = 0x60,
67 QLCNIC_HW_SQG1_CRB_AGT_ADR = 0x61,
68 QLCNIC_HW_SQG2_CRB_AGT_ADR = 0x62,
69 QLCNIC_HW_SQG3_CRB_AGT_ADR = 0x63,
70 QLCNIC_HW_RPMX1_CRB_AGT_ADR = 0x09,
71 QLCNIC_HW_RPMX5_CRB_AGT_ADR = 0x0d,
72 QLCNIC_HW_RPMX6_CRB_AGT_ADR = 0x0e,
73 QLCNIC_HW_RPMX8_CRB_AGT_ADR = 0x11
78 QLCNIC_HW_PH_CRB_AGT_ADR = 0x1A,
79 QLCNIC_HW_SRE_CRB_AGT_ADR = 0x50,
80 QLCNIC_HW_EG_CRB_AGT_ADR = 0x51,
81 QLCNIC_HW_RPMX0_CRB_AGT_ADR = 0x08
86 QLCNIC_HW_PEGN0_CRB_AGT_ADR = 0x40,
102 QLCNIC_HW_PEGS0_CRB_AGT_ADR = 0x40,
113 QLCNIC_HW_CAS0_CRB_AGT_ADR = 0x46,
114 QLCNIC_HW_CAS1_CRB_AGT_ADR = 0x47,
115 QLCNIC_HW_CAS2_CRB_AGT_ADR = 0x48,
116 QLCNIC_HW_CAS3_CRB_AGT_ADR = 0x49,
117 QLCNIC_HW_NCM_CRB_AGT_ADR = 0x16,
118 QLCNIC_HW_TMR_CRB_AGT_ADR = 0x17,
119 QLCNIC_HW_XDMA_CRB_AGT_ADR = 0x05,
120 QLCNIC_HW_OCM0_CRB_AGT_ADR = 0x06,
121 QLCNIC_HW_OCM1_CRB_AGT_ADR = 0x07
125 #define QLCNIC_HW_EFC_RPMX0_CRB_AGT_ADR 0x67
129 QLCNIC_HW_PX_MAP_CRB_PH = 0,
195 #define BIT_0 0x1
196 #define BIT_1 0x2
197 #define BIT_2 0x4
198 #define BIT_3 0x8
199 #define BIT_4 0x10
200 #define BIT_5 0x20
201 #define BIT_6 0x40
202 #define BIT_7 0x80
203 #define BIT_8 0x100
204 #define BIT_9 0x200
205 #define BIT_10 0x400
206 #define BIT_11 0x800
207 #define BIT_12 0x1000
208 #define BIT_13 0x2000
209 #define BIT_14 0x4000
210 #define BIT_15 0x8000
211 #define BIT_16 0x10000
212 #define BIT_17 0x20000
213 #define BIT_18 0x40000
214 #define BIT_19 0x80000
215 #define BIT_20 0x100000
216 #define BIT_21 0x200000
217 #define BIT_22 0x400000
218 #define BIT_23 0x800000
219 #define BIT_24 0x1000000
220 #define BIT_25 0x2000000
221 #define BIT_26 0x4000000
222 #define BIT_27 0x8000000
223 #define BIT_28 0x10000000
224 #define BIT_29 0x20000000
225 #define BIT_30 0x40000000
226 #define BIT_31 0x80000000
367 #define QLCNIC_SRE_MISC (QLCNIC_CRB_SRE + 0x0002c)
369 #define QLCNIC_I2Q_CLR_PCI_HI (QLCNIC_CRB_I2Q + 0x00034)
371 #define ROMUSB_GLB (QLCNIC_CRB_ROMUSB + 0x00000)
372 #define ROMUSB_ROM (QLCNIC_CRB_ROMUSB + 0x10000)
374 #define QLCNIC_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004)
375 #define QLCNIC_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008)
376 #define QLCNIC_ROMUSB_GLB_PAD_GPIO_I (ROMUSB_GLB + 0x000c)
377 #define QLCNIC_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038)
378 #define QLCNIC_ROMUSB_GLB_TEST_MUX_SEL (ROMUSB_GLB + 0x0044)
379 #define QLCNIC_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c)
380 #define QLCNIC_ROMUSB_GLB_CHIP_CLK_CTRL (ROMUSB_GLB + 0x00A8)
382 #define QLCNIC_ROMUSB_GPIO(n) (ROMUSB_GLB + 0x60 + (4 * (n)))
384 #define QLCNIC_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004)
385 #define QLCNIC_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008)
386 #define QLCNIC_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c)
387 #define QLCNIC_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010)
388 #define QLCNIC_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014)
389 #define QLCNIC_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018)
400 #define QLCNIC_PCI_CRB_WINDOWSIZE 0x00100000
450 #define QLCNIC_PCI_OCM0_2M (0x000c0000UL)
451 #define QLCNIC_PCI_CRBSPACE (0x06000000UL)
452 #define QLCNIC_PCI_CAMQM (0x04800000UL)
453 #define QLCNIC_PCI_CAMQM_END (0x04800800UL)
454 #define QLCNIC_PCI_CAMQM_2M_BASE (0x000ff800UL)
458 #define QLCNIC_ADDR_DDR_NET (0x0000000000000000ULL)
459 #define QLCNIC_ADDR_DDR_NET_MAX (0x000000000fffffffULL)
460 #define QLCNIC_ADDR_OCM0 (0x0000000200000000ULL)
461 #define QLCNIC_ADDR_OCM0_MAX (0x00000002000fffffULL)
462 #define QLCNIC_ADDR_OCM1 (0x0000000200400000ULL)
463 #define QLCNIC_ADDR_OCM1_MAX (0x00000002004fffffULL)
464 #define QLCNIC_ADDR_QDR_NET (0x0000000300000000ULL)
465 #define QLCNIC_ADDR_QDR_NET_MAX (0x0000000307ffffffULL)
470 #define QLCNIC_MIU_CONTROL (0x000)
480 #define QLCNIC_NIU_MODE (QLCNIC_CRB_NIU + 0x00000)
481 #define QLCNIC_NIU_GB_PAUSE_CTL (QLCNIC_CRB_NIU + 0x0030c)
482 #define QLCNIC_NIU_XG_PAUSE_CTL (QLCNIC_CRB_NIU + 0x00098)
485 (QLCNIC_CRB_NIU + 0x30000 + (I)*0x10000)
487 (QLCNIC_CRB_NIU + 0x30004 + (I)*0x10000)
490 #define TEST_AGT_CTRL (0x00)
498 #define XG_LINK_UP 0x10
499 #define XG_LINK_DOWN 0x20
501 #define XG_LINK_UP_P3P 0x01
502 #define XG_LINK_DOWN_P3P 0x02
503 #define XG_LINK_STATE_P3P_MASK 0xf
508 #define P3P_LINK_SPEED_MASK 0xff
512 (((reg) >> (8 * ((pcifn) & 0x3))) & P3P_LINK_SPEED_MASK)
514 #define QLCNIC_CAM_RAM_BASE (QLCNIC_CRB_CAM + 0x02000)
516 #define QLCNIC_ROM_LOCK_ID (QLCNIC_CAM_RAM(0x100))
517 #define QLCNIC_PHY_LOCK_ID (QLCNIC_CAM_RAM(0x120))
518 #define QLCNIC_CRB_WIN_LOCK_ID (QLCNIC_CAM_RAM(0x124))
520 #define NIC_CRB_BASE (QLCNIC_CAM_RAM(0x200))
521 #define NIC_CRB_BASE_2 (QLCNIC_CAM_RAM(0x700))
526 #define QLCNIC_CDRP_ARG(i) (QLCNIC_REG(0x18 + ((i) * 4)))
528 #define QLCNIC_CDRP_CRB_OFFSET (QLCNIC_REG(0x18))
529 #define QLCNIC_SIGN_CRB_OFFSET (QLCNIC_REG(0x28))
531 #define CRB_XG_STATE_P3P (QLCNIC_REG(0x98))
532 #define CRB_PF_LINK_SPEED_1 (QLCNIC_REG(0xe8))
533 #define CRB_DRIVER_VERSION (QLCNIC_REG(0x2a0))
535 #define CRB_FW_CAPABILITIES_2 (QLCNIC_CAM_RAM(0x12c))
546 #define qlcnic_get_temp_state(x) ((x) & 0xffff)
553 QLCNIC_TEMP_NORMAL = 0x1, /* Normal operating range */
560 #define PHY_LOCK_DRIVER 0x44524956
562 #define PCIX_INT_VECTOR (0x10100)
563 #define PCIX_INT_MASK (0x10104)
565 #define PCIX_OCM_WINDOW (0x10800)
566 #define PCIX_OCM_WINDOW_REG(func) (PCIX_OCM_WINDOW + 0x4 * (func))
568 #define PCIX_TARGET_STATUS (0x10118)
569 #define PCIX_TARGET_STATUS_F1 (0x10160)
570 #define PCIX_TARGET_STATUS_F2 (0x10164)
571 #define PCIX_TARGET_STATUS_F3 (0x10168)
572 #define PCIX_TARGET_STATUS_F4 (0x10360)
573 #define PCIX_TARGET_STATUS_F5 (0x10364)
574 #define PCIX_TARGET_STATUS_F6 (0x10368)
575 #define PCIX_TARGET_STATUS_F7 (0x1036c)
577 #define PCIX_TARGET_MASK (0x10128)
578 #define PCIX_TARGET_MASK_F1 (0x10170)
579 #define PCIX_TARGET_MASK_F2 (0x10174)
580 #define PCIX_TARGET_MASK_F3 (0x10178)
581 #define PCIX_TARGET_MASK_F4 (0x10370)
582 #define PCIX_TARGET_MASK_F5 (0x10374)
583 #define PCIX_TARGET_MASK_F6 (0x10378)
584 #define PCIX_TARGET_MASK_F7 (0x1037c)
586 #define PCIX_MSI_F(i) (0x13000+((i)*4))
592 #define PCIE_SEM0_LOCK (0x1c000)
593 #define PCIE_SEM0_UNLOCK (0x1c004)
597 #define PCIE_SETUP_FUNCTION (0x12040)
598 #define PCIE_SETUP_FUNCTION2 (0x12048)
599 #define PCIE_MISCCFG_RC (0x1206c)
600 #define PCIE_TGT_SPLIT_CHICKEN (0x12080)
601 #define PCIE_CHICKEN3 (0x120c8)
604 #define PCIE_MAX_MASTER_SPLIT (0x14048)
606 #define QLCNIC_PORT_MODE_NONE 0
613 #define QLCNIC_PORT_MODE_ADDR (QLCNIC_CAM_RAM(0x24))
614 #define QLCNIC_WOL_PORT_MODE (QLCNIC_CAM_RAM(0x198))
616 #define QLCNIC_WOL_CONFIG_NV (QLCNIC_CAM_RAM(0x184))
617 #define QLCNIC_WOL_CONFIG (QLCNIC_CAM_RAM(0x188))
619 #define QLCNIC_PEG_TUNE_MN_PRESENT 0x1
620 #define QLCNIC_PEG_TUNE_CAPABILITY (QLCNIC_CAM_RAM(0x02c))
622 #define QLCNIC_DMA_WATCHDOG_CTRL (QLCNIC_CAM_RAM(0x14))
623 #define QLCNIC_ROM_DEV_INIT_TIMEOUT (0x3e885c)
624 #define QLCNIC_ROM_DRV_RESET_TIMEOUT (0x3e8860)
627 #define QLCNIC_DEV_COLD 0x1
628 #define QLCNIC_DEV_INITIALIZING 0x2
629 #define QLCNIC_DEV_READY 0x3
630 #define QLCNIC_DEV_NEED_RESET 0x4
631 #define QLCNIC_DEV_NEED_QUISCENT 0x5
632 #define QLCNIC_DEV_FAILED 0x6
633 #define QLCNIC_DEV_QUISCENT 0x7
635 #define QLCNIC_DEV_BADBAD 0xbad0bad0
637 #define QLCNIC_DEV_NPAR_NON_OPER 0 /* NON Operational */
647 #define QLC_DEV_GET_DRV(VAL, FN) (0xf & ((VAL) >> (FN * 4)))
654 #define QLCNIC_RCODE_DRIVER_INFO 0x20000000
657 #define QLCNIC_FWERROR_PEGNUM(code) ((code) & 0xff)
658 #define QLCNIC_FWERROR_CODE(code) ((code >> 8) & 0x1fffff)
659 #define QLCNIC_FWERROR_FAN_FAILURE 0x16
678 #define ISR_LEGACY_INT_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)
683 #define PCIX_INT_VECTOR_BIT_F0 0x0080
684 #define PCIX_INT_VECTOR_BIT_F1 0x0100
685 #define PCIX_INT_VECTOR_BIT_F2 0x0200
686 #define PCIX_INT_VECTOR_BIT_F3 0x0400
687 #define PCIX_INT_VECTOR_BIT_F4 0x0800
688 #define PCIX_INT_VECTOR_BIT_F5 0x1000
689 #define PCIX_INT_VECTOR_BIT_F6 0x2000
690 #define PCIX_INT_VECTOR_BIT_F7 0x4000
699 #define QLCNIC_MSIX_BASE 0x132110
702 #define FLASH_ROM_WINDOW 0x42110030
703 #define FLASH_ROM_DATA 0x42150000
705 #define QLCNIC_FW_DUMP_REG1 0x00130060
706 #define QLCNIC_FW_DUMP_REG2 0x001e0000
707 #define QLCNIC_FLASH_SEM2_LK 0x0013C010
708 #define QLCNIC_FLASH_SEM2_ULK 0x0013C014
709 #define QLCNIC_FLASH_LOCK_ID 0x001B2100
713 QLCNIC_MGMT_FUNC = 0,
722 QLCNIC_PORT_DEFAULTS = 0,
727 #define QLC_DEV_DRV_DEFAULT 0x11111111
738 #define QLCNIC_MS_CTRL 0x41000090
739 #define QLCNIC_MS_ADDR_LO 0x41000094
740 #define QLCNIC_MS_ADDR_HI 0x41000098
741 #define QLCNIC_MS_WRTDATA_LO 0x410000A0
742 #define QLCNIC_MS_WRTDATA_HI 0x410000A4
743 #define QLCNIC_MS_WRTDATA_ULO 0x410000B0
744 #define QLCNIC_MS_WRTDATA_UHI 0x410000B4
745 #define QLCNIC_MS_RDDATA_LO 0x410000A8
746 #define QLCNIC_MS_RDDATA_HI 0x410000AC
747 #define QLCNIC_MS_RDDATA_ULO 0x410000B8
748 #define QLCNIC_MS_RDDATA_UHI 0x410000BC
799 #define _qlcnic_crb_get_bit(var, bit) ((var >> bit) & 0x1)
802 * NIU GB MAC Config Register 0 (applies to GB0, GB1, GB2, GB3)
804 * Bit 0 : enable_tx => 1:enable frame xmit, 0:disable
806 * Bit 2 : enable_rx => 1:enable frame recv, 0:disable
808 * Bit 4 : tx_flowctl => 1:enable pause frame generation, 0:disable
809 * Bit 5 : rx_flowctl => 1:act on recv'd pause frames, 0:ignore
810 * Bit 8 : loopback => 1:loop MAC xmits to MAC recvs, 0:normal
811 * Bit 16: tx_reset_pb => 1:reset frame xmit protocol blk, 0:no-op
812 * Bit 17: rx_reset_pb => 1:reset frame recv protocol blk, 0:no-op
813 * Bit 18: tx_reset_mac => 1:reset data/ctl multiplexer blk, 0:no-op
814 * Bit 19: rx_reset_mac => 1:reset ctl frames & timers blk, 0:no-op
815 * Bit 31: soft_reset => 1:reset the MAC and the SERDES, 0:no-op
829 ((config_word) |= 1 << 0)
838 _qlcnic_crb_get_bit((config_word), 0)
847 ((config_word) &= ~(1 << 0))
858 * Bit 0 : xg0_mask => 1:disable tx pause frames
860 * Bit 2 : xg0_on_off => 1:request is pause on, 0:off
863 * Bit 5 : xg1_on_off => 1:request is pause on, 0:off
867 ((config_word) |= 1 << 0)
872 _qlcnic_crb_get_bit((config_word), 0)
877 ((config_word) &= ~(1 << 0))
884 * Bit 0 : xg0_mask => 1:disable tx pause frames
886 * Bit 2 : xg0_on_off => 1:request is pause on, 0:off
889 * Bit 5 : xg1_on_off => 1:request is pause on, 0:off
901 * Bit 0 : jabber => 1:jabber detected, 0:not
902 * Bit 1 : polarity => 1:polarity reversed, 0:normal
903 * Bit 2 : recvpause => 1:receive pause enabled, 0:disabled
904 * Bit 3 : xmitpause => 1:transmit pause enabled, 0:disabled
905 * Bit 4 : energydetect => 1:sleep, 0:active
906 * Bit 5 : downshift => 1:downshift, 0:no downshift
907 * Bit 6 : crossover => 1:MDIX (crossover), 0:MDI (no crossover)
909 * 0:<50m, 1:50-80m, 2:80-110m, 3:110-140m, 4:>140m
910 * Bit 10 : link => 1:link up, 0:link down
911 * Bit 11 : resolved => 1:speed and duplex resolved, 0:not yet
912 * Bit 12 : pagercvd => 1:page received, 0:page not received
913 * Bit 13 : duplex => 1:full duplex, 0:half duplex
914 * Bits 14-15 : speed => 0:10Mb/s, 1:100Mb/s, 2:1000Mb/s, 3:rsvd
917 #define qlcnic_get_phy_speed(config_word) (((config_word) >> 14) & 0x03)
920 ((config_word) |= ((val & 0x03) << 14))
931 #define QLCNIC_NIU_NON_PROMISC_MODE 0