Lines Matching +full:0 +full:xff0f0000
15 #define ID_REV (0x00)
16 #define ID_REV_ID_MASK_ (0xFFFF0000)
17 #define ID_REV_ID_LAN7430_ (0x74300000)
18 #define ID_REV_ID_LAN7431_ (0x74310000)
19 #define ID_REV_ID_LAN743X_ (0x74300000)
20 #define ID_REV_ID_A011_ (0xA0110000) // PCI11010
21 #define ID_REV_ID_A041_ (0xA0410000) // PCI11414
22 #define ID_REV_ID_A0X1_ (0xA0010000)
24 ((((id_rev) & 0xFFF00000) == ID_REV_ID_LAN743X_) || \
25 (((id_rev) & 0xFF0F0000) == ID_REV_ID_A0X1_))
26 #define ID_REV_CHIP_REV_MASK_ (0x0000FFFF)
27 #define ID_REV_CHIP_REV_A0_ (0x00000000)
28 #define ID_REV_CHIP_REV_B0_ (0x00000010)
30 #define FPGA_REV (0x04)
31 #define FPGA_REV_GET_MINOR_(fpga_rev) (((fpga_rev) >> 8) & 0x000000FF)
32 #define FPGA_REV_GET_MAJOR_(fpga_rev) ((fpga_rev) & 0x000000FF)
35 #define STRAP_READ (0x0C)
43 #define STRAP_READ_ADV_PM_DISABLE_ BIT(0)
45 #define HW_CFG (0x010)
51 #define HW_CFG_RELOAD_TYPE_ALL_ (0x00000FC0)
55 #define PMT_CTL (0x014)
67 #define PMT_CTL_WUPS_MASK_ (0x00000003)
69 #define DP_SEL (0x024)
71 #define DP_SEL_MASK_ (0x0000001F)
72 #define DP_SEL_RFE_RAM (0x00000001)
77 #define DP_CMD (0x028)
78 #define DP_CMD_WRITE_ (0x00000001)
80 #define DP_ADDR (0x02C)
82 #define DP_DATA_0 (0x030)
84 #define E2P_CMD (0x040)
86 #define E2P_CMD_EPC_CMD_WRITE_ (0x30000000)
87 #define E2P_CMD_EPC_CMD_EWEN_ (0x20000000)
88 #define E2P_CMD_EPC_CMD_READ_ (0x00000000)
90 #define E2P_CMD_EPC_ADDR_MASK_ (0x000001FF)
92 #define E2P_DATA (0x044)
95 #define ETH_CTRL_REG_ADDR_BASE (0x0000)
96 #define ETH_SYS_REG_ADDR_BASE (0x4000)
97 #define CONFIG_REG_ADDR_BASE (0x0000)
98 #define ETH_EEPROM_REG_ADDR_BASE (0x0E00)
99 #define ETH_OTP_REG_ADDR_BASE (0x1000)
100 #define GEN_SYS_CONFIG_LOAD_STARTED_REG (0x0078)
105 #define SYS_LOCK_REG (0x00A0)
112 #define SYS_LOCK_REG_USB_SS_LOCK_ BIT(0)
118 #define HS_E2P_CMD (HS_EEPROM_REG_ADDR_BASE + 0x0000)
121 #define HS_E2P_CMD_EPC_CMD_READ_ (0x0)
123 #define HS_E2P_CMD_EPC_ADDR_MASK_ GENMASK(15, 0)
124 #define HS_E2P_DATA (HS_EEPROM_REG_ADDR_BASE + 0x0004)
125 #define HS_E2P_DATA_MASK_ GENMASK(7, 0)
126 #define HS_E2P_CFG (HS_EEPROM_REG_ADDR_BASE + 0x0008)
130 #define HS_E2P_CFG_TEST_EEPR_TO_BYP_ BIT(0)
131 #define HS_E2P_PAD_CTL (HS_EEPROM_REG_ADDR_BASE + 0x000C)
133 #define GPIO_CFG0 (0x050)
135 #define GPIO_CFG0_GPIO_DATA_BIT_(bit) BIT(0 + (bit))
137 #define GPIO_CFG1 (0x054)
139 #define GPIO_CFG1_GPIOBUF_BIT_(bit) BIT(0 + (bit))
141 #define GPIO_CFG2 (0x058)
142 #define GPIO_CFG2_1588_POL_BIT_(bit) BIT(0 + (bit))
144 #define GPIO_CFG3 (0x05C)
146 #define GPIO_CFG3_1588_OE_BIT_(bit) BIT(0 + (bit))
148 #define FCT_RX_CTL (0xAC)
153 #define FCT_TX_CTL (0xC4)
158 #define FCT_FLOW(rx_channel) (0xE0 + ((rx_channel) << 2))
159 #define FCT_FLOW_CTL_OFF_THRESHOLD_ (0x00007F00)
163 #define FCT_FLOW_CTL_ON_THRESHOLD_ (0x0000007F)
165 ((value << 0) & FCT_FLOW_CTL_ON_THRESHOLD_)
167 #define MAC_CR (0x100)
176 #define MAC_CR_RST_ BIT(0)
178 #define MAC_RX (0x104)
180 #define MAC_RX_MAX_SIZE_MASK_ (0x3FFF0000)
182 #define MAC_RX_RXEN_ BIT(0)
184 #define MAC_TX (0x108)
186 #define MAC_TX_TXEN_ BIT(0)
188 #define MAC_FLOW (0x10C)
191 #define MAC_FLOW_CR_FCPT_MASK_ (0x0000FFFF)
193 #define MAC_RX_ADDRH (0x118)
195 #define MAC_RX_ADDRL (0x11C)
197 #define MAC_MII_ACC (0x120)
199 #define MAC_MII_ACC_MDC_CYCLE_MASK_ (0x00070000)
200 #define MAC_MII_ACC_MDC_CYCLE_2_5MHZ_ (0)
206 #define MAC_MII_ACC_PHY_ADDR_MASK_ (0x0000F800)
208 #define MAC_MII_ACC_MIIRINDA_MASK_ (0x000007C0)
209 #define MAC_MII_ACC_MII_READ_ (0x00000000)
210 #define MAC_MII_ACC_MII_WRITE_ (0x00000002)
211 #define MAC_MII_ACC_MII_BUSY_ BIT(0)
214 #define MAC_MII_ACC_MIIMMD_MASK_ (0x000007C0)
216 #define MAC_MII_ACC_MIICMD_MASK_ (0x00000006)
217 #define MAC_MII_ACC_MIICMD_ADDR_ (0x00000000)
218 #define MAC_MII_ACC_MIICMD_WRITE_ (0x00000002)
219 #define MAC_MII_ACC_MIICMD_READ_ (0x00000004)
220 #define MAC_MII_ACC_MIICMD_READ_INC_ (0x00000006)
222 #define MAC_MII_DATA (0x124)
224 #define MAC_EEE_TX_LPI_REQ_DLY_CNT (0x130)
226 #define MAC_WUCSR (0x140)
232 #define MAC_WUCSR_BCST_EN_ BIT(0)
234 #define MAC_WK_SRC (0x144)
235 #define MAC_MP_SO_HI (0x148)
236 #define MAC_MP_SO_LO (0x14C)
238 #define MAC_WUF_CFG0 (0x150)
243 #define MAC_WUF_CFG_TYPE_MCAST_ (0x02000000)
244 #define MAC_WUF_CFG_TYPE_ALL_ (0x01000000)
246 #define MAC_WUF_CFG_CRC16_MASK_ (0x0000FFFF)
248 #define MAC_WUF_MASK0_0 (0x200)
249 #define MAC_WUF_MASK0_1 (0x204)
250 #define MAC_WUF_MASK0_2 (0x208)
251 #define MAC_WUF_MASK0_3 (0x20C)
256 #define MAC_WUF_MASK0(index) (MAC_WUF_MASK0_BEGIN + (0x10 * (index)))
257 #define MAC_WUF_MASK1(index) (MAC_WUF_MASK1_BEGIN + (0x10 * (index)))
258 #define MAC_WUF_MASK2(index) (MAC_WUF_MASK2_BEGIN + (0x10 * (index)))
259 #define MAC_WUF_MASK3(index) (MAC_WUF_MASK3_BEGIN + (0x10 * (index)))
261 /* offset 0x400 - 0x500, x may range from 0 to 32, for a total of 33 entries */
262 #define RFE_ADDR_FILT_HI(x) (0x400 + (8 * (x)))
265 /* offset 0x404 - 0x504, x may range from 0 to 32, for a total of 33 entries */
266 #define RFE_ADDR_FILT_LO(x) (0x404 + (8 * (x)))
268 #define RFE_CTL (0x508)
277 #define RFE_RSS_CFG (0x554)
287 #define RFE_RSS_CFG_VALID_HASH_BITS_ (0x000000E0)
290 #define RFE_RSS_CFG_RSS_ENABLE_ BIT(0)
292 #define RFE_HASH_KEY(index) (0x558 + (index << 2))
294 #define RFE_INDX(index) (0x580 + (index << 2))
296 #define MAC_WUCSR2 (0x600)
298 #define SGMII_ACC (0x720)
304 #define SGMII_ACC_SGMII_ADDR_SHIFT_ (0)
305 #define SGMII_ACC_SGMII_ADDR_MASK_ GENMASK(15, 0)
306 #define SGMII_DATA (0x724)
307 #define SGMII_DATA_SHIFT_ (0)
308 #define SGMII_DATA_MASK_ GENMASK(15, 0)
309 #define SGMII_CTL (0x728)
315 #define SR_VSMMD_PCS_ID1 0x0004
316 #define SR_VSMMD_PCS_ID2 0x0005
317 #define SR_VSMMD_STS 0x0008
318 #define SR_VSMMD_CTRL 0x0009
320 #define VR_MII_DIG_CTRL1 0x8000
331 #define VR_MII_DIG_CTRL1_PHY_MODE_CTRL_ BIT(0)
332 #define VR_MII_AN_CTRL 0x8001
336 #define VR_MII_AN_CTRL_1000BASE_X_ (0)
341 #define VR_MII_AN_CTRL_MII_AN_INTR_EN_ BIT(0)
342 #define VR_MII_AN_INTR_STS 0x8002
347 #define VR_MII_AN_INTR_STS_10_MBPS_ (0)
349 #define VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR_ BIT(0)
351 #define VR_MII_LINK_TIMER_CTRL 0x800A
352 #define VR_MII_DIG_STS 0x8010
355 #define VR_MII_GEN2_4_MPLL_CTRL0 0x8078
358 #define VR_MII_GEN2_4_MPLL_CTRL1 0x8079
359 #define VR_MII_MPLL_CTRL1_MPLL_MULTIPLIER_ GENMASK(6, 0)
366 #define VR_MII_GEN2_4_MISC_CTRL1 0x809A
369 #define VR_MII_CTRL1_TX_RATE_0_MASK_ GENMASK(1, 0)
370 #define VR_MII_MPLL_BAUD_CLK (0)
374 #define INT_STS (0x780)
376 #define INT_BIT_ALL_RX_ (0x0F000000)
378 #define INT_BIT_ALL_TX_ (0x000F0000)
382 #define INT_BIT_MAS_ BIT(0)
384 #define INT_SET (0x784)
386 #define INT_EN_SET (0x788)
388 #define INT_EN_CLR (0x78C)
390 #define INT_STS_R2C (0x790)
392 #define INT_VEC_EN_SET (0x794)
393 #define INT_VEC_EN_CLR (0x798)
394 #define INT_VEC_EN_AUTO_CLR (0x79C)
395 #define INT_VEC_EN_(vector_index) BIT(0 + vector_index)
397 #define INT_VEC_MAP0 (0x7A0)
401 #define INT_VEC_MAP1 (0x7A4)
405 #define INT_VEC_MAP2 (0x7A8)
407 #define INT_MOD_MAP0 (0x7B0)
409 #define INT_MOD_MAP1 (0x7B4)
411 #define INT_MOD_MAP2 (0x7B8)
413 #define INT_MOD_CFG0 (0x7C0)
414 #define INT_MOD_CFG1 (0x7C4)
415 #define INT_MOD_CFG2 (0x7C8)
416 #define INT_MOD_CFG3 (0x7CC)
417 #define INT_MOD_CFG4 (0x7D0)
418 #define INT_MOD_CFG5 (0x7D4)
419 #define INT_MOD_CFG6 (0x7D8)
420 #define INT_MOD_CFG7 (0x7DC)
421 #define INT_MOD_CFG8 (0x7E0)
422 #define INT_MOD_CFG9 (0x7E4)
424 #define PTP_CMD_CTL (0x0A00)
432 #define PTP_CMD_CTL_PTP_RESET_ BIT(0)
433 #define PTP_GENERAL_CONFIG (0x0A04)
435 (0x7 << (1 + ((channel) << 2)))
436 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_100NS_ (0)
444 (((value) & 0x7) << (1 + ((channel) << 2)))
447 #define HS_PTP_GENERAL_CONFIG (0x0A04)
449 (0xf << (4 + ((channel) << 2)))
450 #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_100NS_ (0)
467 (((value) & 0xf) << (4 + ((channel) << 2)))
471 #define PTP_INT_STS (0x0A08)
484 #define PTP_INT_TIMER_INT_A_ BIT(0)
485 #define PTP_INT_EN_SET (0x0A0C)
489 #define PTP_INT_EN_CLR (0x0A10)
495 #define PTP_INT_BIT_TIMER_A_ BIT(0)
497 #define PTP_CLOCK_SEC (0x0A14)
498 #define PTP_CLOCK_NS (0x0A18)
499 #define PTP_CLOCK_SUBNS (0x0A1C)
500 #define PTP_CLOCK_RATE_ADJ (0x0A20)
502 #define PTP_CLOCK_STEP_ADJ (0x0A2C)
504 #define PTP_CLOCK_STEP_ADJ_VALUE_MASK_ (0x3FFFFFFF)
505 #define PTP_CLOCK_TARGET_SEC_X(channel) (0x0A30 + ((channel) << 4))
506 #define PTP_CLOCK_TARGET_NS_X(channel) (0x0A34 + ((channel) << 4))
507 #define PTP_CLOCK_TARGET_RELOAD_SEC_X(channel) (0x0A38 + ((channel) << 4))
508 #define PTP_CLOCK_TARGET_RELOAD_NS_X(channel) (0x0A3C + ((channel) << 4))
509 #define PTP_LTC_SET_SEC_HI (0x0A50)
510 #define PTP_LTC_SET_SEC_HI_SEC_47_32_MASK_ GENMASK(15, 0)
511 #define PTP_VERSION (0x0A54)
515 #define PTP_VERSION_RX_LO_MASK_ GENMASK(7, 0)
516 #define PTP_IO_SEL (0x0A58)
519 #define PTP_LATENCY (0x0A5C)
522 (((u32)(rx_latency)) & 0x0000FFFF)
523 #define PTP_CAP_INFO (0x0A60)
524 #define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x00000070) >> 4)
525 #define PTP_RX_TS_CFG (0x0A68)
526 #define PTP_RX_TS_CFG_EVENT_MSGS_ GENMASK(3, 0)
528 #define PTP_TX_MOD (0x0AA4)
529 #define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ (0x10000000)
531 #define PTP_TX_MOD2 (0x0AA8)
532 #define PTP_TX_MOD2_TX_PTP_CLR_UDPV4_CHKSUM_ (0x00000001)
534 #define PTP_TX_EGRESS_SEC (0x0AAC)
535 #define PTP_TX_EGRESS_NS (0x0AB0)
536 #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_MASK_ (0xC0000000)
537 #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_AUTO_ (0x00000000)
538 #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_SW_ (0x40000000)
539 #define PTP_TX_EGRESS_NS_TS_NS_MASK_ (0x3FFFFFFF)
541 #define PTP_TX_MSG_HEADER (0x0AB4)
542 #define PTP_TX_MSG_HEADER_MSG_TYPE_ (0x000F0000)
543 #define PTP_TX_MSG_HEADER_MSG_TYPE_SYNC_ (0x00000000)
545 #define PTP_TX_CAP_INFO (0x0AB8)
546 #define PTP_TX_CAP_INFO_TX_CH_MASK_ GENMASK(1, 0)
547 #define PTP_TX_DOMAIN (0x0ABC)
550 #define PTP_TX_DOMAIN_RANGE_MASK_ GENMASK(7, 0)
551 #define PTP_TX_SDOID (0x0AC0)
554 #define PTP_TX_SDOID_11_0_MASK_ GENMASK(7, 0)
555 #define PTP_IO_CAP_CONFIG (0x0AC4)
559 #define PTP_IO_CAP_CONFIG_RE_CAP_EN_(channel) BIT(0 + (channel))
560 #define PTP_IO_RE_LTC_SEC_CAP_X (0x0AC8)
561 #define PTP_IO_RE_LTC_NS_CAP_X (0x0ACC)
562 #define PTP_IO_FE_LTC_SEC_CAP_X (0x0AD0)
563 #define PTP_IO_FE_LTC_NS_CAP_X (0x0AD4)
564 #define PTP_IO_EVENT_OUTPUT_CFG (0x0AD8)
566 #define PTP_IO_EVENT_OUTPUT_CFG_EN_(channel) BIT(0 + (channel))
567 #define PTP_IO_PIN_CFG (0x0ADC)
568 #define PTP_IO_PIN_CFG_OBUF_TYPE_(channel) BIT(0 + (channel))
569 #define PTP_LTC_RD_SEC_HI (0x0AF0)
570 #define PTP_LTC_RD_SEC_HI_SEC_47_32_MASK_ GENMASK(15, 0)
571 #define PTP_LTC_RD_SEC_LO (0x0AF4)
572 #define PTP_LTC_RD_NS (0x0AF8)
573 #define PTP_LTC_RD_NS_29_0_MASK_ GENMASK(29, 0)
574 #define PTP_LTC_RD_SUBNS (0x0AFC)
575 #define PTP_RX_USER_MAC_HI (0x0B00)
576 #define PTP_RX_USER_MAC_HI_47_32_MASK_ GENMASK(15, 0)
577 #define PTP_RX_USER_MAC_LO (0x0B04)
578 #define PTP_RX_USER_IP_ADDR_0 (0x0B20)
579 #define PTP_RX_USER_IP_ADDR_1 (0x0B24)
580 #define PTP_RX_USER_IP_ADDR_2 (0x0B28)
581 #define PTP_RX_USER_IP_ADDR_3 (0x0B2C)
582 #define PTP_RX_USER_IP_MASK_0 (0x0B30)
583 #define PTP_RX_USER_IP_MASK_1 (0x0B34)
584 #define PTP_RX_USER_IP_MASK_2 (0x0B38)
585 #define PTP_RX_USER_IP_MASK_3 (0x0B3C)
586 #define PTP_TX_USER_MAC_HI (0x0B40)
587 #define PTP_TX_USER_MAC_HI_47_32_MASK_ GENMASK(15, 0)
588 #define PTP_TX_USER_MAC_LO (0x0B44)
589 #define PTP_TX_USER_IP_ADDR_0 (0x0B60)
590 #define PTP_TX_USER_IP_ADDR_1 (0x0B64)
591 #define PTP_TX_USER_IP_ADDR_2 (0x0B68)
592 #define PTP_TX_USER_IP_ADDR_3 (0x0B6C)
593 #define PTP_TX_USER_IP_MASK_0 (0x0B70)
594 #define PTP_TX_USER_IP_MASK_1 (0x0B74)
595 #define PTP_TX_USER_IP_MASK_2 (0x0B78)
596 #define PTP_TX_USER_IP_MASK_3 (0x0B7C)
598 #define DMAC_CFG (0xC00)
600 #define DMAC_CFG_CH_ARB_SEL_RX_HIGH_ (0x00000000)
601 #define DMAC_CFG_MAX_READ_REQ_MASK_ (0x00000070)
604 #define DMAC_CFG_MAX_DSPACE_16_ (0x00000000)
605 #define DMAC_CFG_MAX_DSPACE_32_ (0x00000001)
607 #define DMAC_CFG_MAX_DSPACE_128_ (0x00000003)
609 #define DMAC_COAL_CFG (0xC04)
610 #define DMAC_COAL_CFG_TIMER_LIMIT_MASK_ (0xFFF00000)
617 #define DMAC_COAL_CFG_TX_THRES_MASK_ (0x0000FF00)
620 #define DMAC_COAL_CFG_RX_THRES_MASK_ (0x000000FF)
624 #define DMAC_OBFF_CFG (0xC08)
625 #define DMAC_OBFF_TX_THRES_MASK_ (0x0000FF00)
628 #define DMAC_OBFF_RX_THRES_MASK_ (0x000000FF)
632 #define DMAC_CMD (0xC0C)
639 #define DMAC_CMD_STOP_R_(channel) BIT(0 + (channel))
641 #define DMAC_INT_STS (0xC10)
642 #define DMAC_INT_EN_SET (0xC14)
643 #define DMAC_INT_EN_CLR (0xC18)
645 #define DMAC_INT_BIT_TX_IOC_(channel) BIT(0 + (channel))
647 #define RX_CFG_A(channel) (0xC40 + ((channel) << 6))
649 #define RX_CFG_A_RX_WB_THRES_MASK_ (0x1F000000)
652 #define RX_CFG_A_RX_PF_THRES_MASK_ (0x001F0000)
655 #define RX_CFG_A_RX_PF_PRI_THRES_MASK_ (0x00001F00)
660 #define RX_CFG_B(channel) (0xC44 + ((channel) << 6))
663 #define RX_CFG_B_TS_NONE_ 0
664 #define RX_CFG_B_TS_MASK_ (0xCFFFFFFF)
665 #define RX_CFG_B_RX_PAD_MASK_ (0x03000000)
666 #define RX_CFG_B_RX_PAD_0_ (0x00000000)
667 #define RX_CFG_B_RX_PAD_2_ (0x02000000)
668 #define RX_CFG_B_RDMABL_512_ (0x00040000)
669 #define RX_CFG_B_RX_RING_LEN_MASK_ (0x0000FFFF)
671 #define RX_BASE_ADDRH(channel) (0xC48 + ((channel) << 6))
673 #define RX_BASE_ADDRL(channel) (0xC4C + ((channel) << 6))
675 #define RX_HEAD_WRITEBACK_ADDRH(channel) (0xC50 + ((channel) << 6))
677 #define RX_HEAD_WRITEBACK_ADDRL(channel) (0xC54 + ((channel) << 6))
679 #define RX_HEAD(channel) (0xC58 + ((channel) << 6))
681 #define RX_TAIL(channel) (0xC5C + ((channel) << 6))
685 #define RX_CFG_C(channel) (0xC64 + ((channel) << 6))
689 #define RX_CFG_C_RX_INT_STS_R2C_MODE_MASK_ (0x00000007)
691 #define TX_CFG_A(channel) (0xD40 + ((channel) << 6))
693 #define TX_CFG_A_TX_TMR_HPWB_SEL_IOC_ (0x10000000)
694 #define TX_CFG_A_TX_PF_THRES_MASK_ (0x001F0000)
697 #define TX_CFG_A_TX_PF_PRI_THRES_MASK_ (0x00001F00)
701 #define TX_CFG_A_TX_HP_WB_THRES_MASK_ (0x0000000F)
705 #define TX_CFG_B(channel) (0xD44 + ((channel) << 6))
706 #define TX_CFG_B_TDMABL_512_ (0x00040000)
707 #define TX_CFG_B_TX_RING_LEN_MASK_ (0x0000FFFF)
709 #define TX_BASE_ADDRH(channel) (0xD48 + ((channel) << 6))
711 #define TX_BASE_ADDRL(channel) (0xD4C + ((channel) << 6))
713 #define TX_HEAD_WRITEBACK_ADDRH(channel) (0xD50 + ((channel) << 6))
715 #define TX_HEAD_WRITEBACK_ADDRL(channel) (0xD54 + ((channel) << 6))
717 #define TX_HEAD(channel) (0xD58 + ((channel) << 6))
719 #define TX_TAIL(channel) (0xD5C + ((channel) << 6))
724 #define TX_CFG_C(channel) (0xD64 + ((channel) << 6))
729 #define TX_CFG_C_TX_INT_STS_R2C_MODE_MASK_ (0x00000007)
731 #define OTP_PWR_DN (0x1000)
732 #define OTP_PWR_DN_PWRDN_N_ BIT(0)
734 #define OTP_ADDR_HIGH (0x1004)
735 #define OTP_ADDR_LOW (0x1008)
737 #define OTP_PRGM_DATA (0x1010)
739 #define OTP_PRGM_MODE (0x1014)
740 #define OTP_PRGM_MODE_BYTE_ BIT(0)
742 #define OTP_READ_DATA (0x1018)
744 #define OTP_FUNC_CMD (0x1020)
745 #define OTP_FUNC_CMD_READ_ BIT(0)
747 #define OTP_TST_CMD (0x1024)
750 #define OTP_CMD_GO (0x1028)
751 #define OTP_CMD_GO_GO_ BIT(0)
753 #define OTP_STATUS (0x1030)
754 #define OTP_STATUS_BUSY_ BIT(0)
759 #define HS_OTP_PWR_DN (HS_OTP_BLOCK_BASE + 0x0)
760 #define HS_OTP_ADDR_HIGH (HS_OTP_BLOCK_BASE + 0x4)
761 #define HS_OTP_ADDR_LOW (HS_OTP_BLOCK_BASE + 0x8)
762 #define HS_OTP_PRGM_DATA (HS_OTP_BLOCK_BASE + 0x10)
763 #define HS_OTP_PRGM_MODE (HS_OTP_BLOCK_BASE + 0x14)
764 #define HS_OTP_READ_DATA (HS_OTP_BLOCK_BASE + 0x18)
765 #define HS_OTP_FUNC_CMD (HS_OTP_BLOCK_BASE + 0x20)
766 #define HS_OTP_TST_CMD (HS_OTP_BLOCK_BASE + 0x24)
767 #define HS_OTP_CMD_GO (HS_OTP_BLOCK_BASE + 0x28)
768 #define HS_OTP_STATUS (HS_OTP_BLOCK_BASE + 0x30)
771 #define STAT_RX_FCS_ERRORS (0x1200)
772 #define STAT_RX_ALIGNMENT_ERRORS (0x1204)
773 #define STAT_RX_FRAGMENT_ERRORS (0x1208)
774 #define STAT_RX_JABBER_ERRORS (0x120C)
775 #define STAT_RX_UNDERSIZE_FRAME_ERRORS (0x1210)
776 #define STAT_RX_OVERSIZE_FRAME_ERRORS (0x1214)
777 #define STAT_RX_DROPPED_FRAMES (0x1218)
778 #define STAT_RX_UNICAST_BYTE_COUNT (0x121C)
779 #define STAT_RX_BROADCAST_BYTE_COUNT (0x1220)
780 #define STAT_RX_MULTICAST_BYTE_COUNT (0x1224)
781 #define STAT_RX_UNICAST_FRAMES (0x1228)
782 #define STAT_RX_BROADCAST_FRAMES (0x122C)
783 #define STAT_RX_MULTICAST_FRAMES (0x1230)
784 #define STAT_RX_PAUSE_FRAMES (0x1234)
785 #define STAT_RX_64_BYTE_FRAMES (0x1238)
786 #define STAT_RX_65_127_BYTE_FRAMES (0x123C)
787 #define STAT_RX_128_255_BYTE_FRAMES (0x1240)
788 #define STAT_RX_256_511_BYTES_FRAMES (0x1244)
789 #define STAT_RX_512_1023_BYTE_FRAMES (0x1248)
790 #define STAT_RX_1024_1518_BYTE_FRAMES (0x124C)
791 #define STAT_RX_GREATER_1518_BYTE_FRAMES (0x1250)
792 #define STAT_RX_TOTAL_FRAMES (0x1254)
793 #define STAT_EEE_RX_LPI_TRANSITIONS (0x1258)
794 #define STAT_EEE_RX_LPI_TIME (0x125C)
795 #define STAT_RX_COUNTER_ROLLOVER_STATUS (0x127C)
797 #define STAT_TX_FCS_ERRORS (0x1280)
798 #define STAT_TX_EXCESS_DEFERRAL_ERRORS (0x1284)
799 #define STAT_TX_CARRIER_ERRORS (0x1288)
800 #define STAT_TX_BAD_BYTE_COUNT (0x128C)
801 #define STAT_TX_SINGLE_COLLISIONS (0x1290)
802 #define STAT_TX_MULTIPLE_COLLISIONS (0x1294)
803 #define STAT_TX_EXCESSIVE_COLLISION (0x1298)
804 #define STAT_TX_LATE_COLLISIONS (0x129C)
805 #define STAT_TX_UNICAST_BYTE_COUNT (0x12A0)
806 #define STAT_TX_BROADCAST_BYTE_COUNT (0x12A4)
807 #define STAT_TX_MULTICAST_BYTE_COUNT (0x12A8)
808 #define STAT_TX_UNICAST_FRAMES (0x12AC)
809 #define STAT_TX_BROADCAST_FRAMES (0x12B0)
810 #define STAT_TX_MULTICAST_FRAMES (0x12B4)
811 #define STAT_TX_PAUSE_FRAMES (0x12B8)
812 #define STAT_TX_64_BYTE_FRAMES (0x12BC)
813 #define STAT_TX_65_127_BYTE_FRAMES (0x12C0)
814 #define STAT_TX_128_255_BYTE_FRAMES (0x12C4)
815 #define STAT_TX_256_511_BYTES_FRAMES (0x12C8)
816 #define STAT_TX_512_1023_BYTE_FRAMES (0x12CC)
817 #define STAT_TX_1024_1518_BYTE_FRAMES (0x12D0)
818 #define STAT_TX_GREATER_1518_BYTE_FRAMES (0x12D4)
819 #define STAT_TX_TOTAL_FRAMES (0x12D8)
820 #define STAT_EEE_TX_LPI_TRANSITIONS (0x12DC)
821 #define STAT_EEE_TX_LPI_TIME (0x12E0)
822 #define STAT_TX_COUNTER_ROLLOVER_STATUS (0x12FC)
849 #define PCI_DEVICE_ID_SMSC_LAN7430 (0x7430)
850 #define PCI_DEVICE_ID_SMSC_LAN7431 (0x7431)
851 #define PCI_DEVICE_ID_SMSC_A011 (0xA011)
852 #define PCI_DEVICE_ID_SMSC_A041 (0xA041)
854 #define PCI_CONFIG_LENGTH (0x1000)
857 #define CSR_LENGTH (0x2000)
859 #define LAN743X_CSR_FLAG_IS_A0 BIT(0)
873 #define LAN743X_VECTOR_FLAG_IRQ_SHARED BIT(0)
928 #define GPIO_QUEUE_STARTED (0)
933 #define TX_FRAME_FLAG_IN_PROGRESS BIT(0)
935 #define TX_TS_FLAG_TIMESTAMPING_ENABLED BIT(0)
1004 POWER_DOWN = 0,
1050 #define LAN743X_ADAPTER_FLAG_OTP BIT(0)
1058 #define INTR_FLAG_IRQ_REQUESTED(vector_index) BIT(0 + vector_index)
1063 #define MAC_MII_WRITE 0
1065 #define PHY_FLAG_OPENED BIT(0)
1069 #define DMA_ADDR_HIGH32(dma_addr) ((u32)(((dma_addr) >> 32) & 0xFFFFFFFF))
1071 #define DMA_ADDR_HIGH32(dma_addr) ((u32)(0))
1073 #define DMA_ADDR_LOW32(dma_addr) ((u32)((dma_addr) & 0xFFFFFFFF))
1081 (((start_bit) ? 2 : 0) | ((stop_bit) ? 1 : 0))
1082 #define DMAC_CHANNEL_STATE_INITIAL DMAC_CHANNEL_STATE_SET(0, 0)
1083 #define DMAC_CHANNEL_STATE_STARTED DMAC_CHANNEL_STATE_SET(1, 0)
1085 #define DMAC_CHANNEL_STATE_STOPPED DMAC_CHANNEL_STATE_SET(0, 1)
1088 #define TX_DESC_DATA0_DTYPE_MASK_ (0xC0000000)
1089 #define TX_DESC_DATA0_DTYPE_DATA_ (0x00000000)
1090 #define TX_DESC_DATA0_DTYPE_EXT_ (0x40000000)
1091 #define TX_DESC_DATA0_FS_ (0x20000000)
1092 #define TX_DESC_DATA0_LS_ (0x10000000)
1093 #define TX_DESC_DATA0_EXT_ (0x08000000)
1094 #define TX_DESC_DATA0_IOC_ (0x04000000)
1095 #define TX_DESC_DATA0_ICE_ (0x00400000)
1096 #define TX_DESC_DATA0_IPE_ (0x00200000)
1097 #define TX_DESC_DATA0_TPE_ (0x00100000)
1098 #define TX_DESC_DATA0_FCS_ (0x00020000)
1099 #define TX_DESC_DATA0_TSE_ (0x00010000)
1100 #define TX_DESC_DATA0_BUF_LENGTH_MASK_ (0x0000FFFF)
1101 #define TX_DESC_DATA0_EXT_LSO_ (0x00200000)
1102 #define TX_DESC_DATA0_EXT_PAY_LENGTH_MASK_ (0x000FFFFF)
1103 #define TX_DESC_DATA3_FRAME_LENGTH_MSS_MASK_ (0x3FFF0000)
1112 #define TX_BUFFER_INFO_FLAG_ACTIVE BIT(0)
1126 #define RX_DESC_DATA0_OWN_ (0x00008000)
1128 #define RX_DESC_DATA0_FS_ (0x80000000)
1129 #define RX_DESC_DATA0_LS_ (0x40000000)
1130 #define RX_DESC_DATA0_FRAME_LENGTH_MASK_ (0x3FFF0000)
1133 #define RX_DESC_DATA0_EXT_ (0x00004000)
1134 #define RX_DESC_DATA0_BUF_LENGTH_MASK_ (0x00003FFF)
1135 #define RX_DESC_DATA1_STATUS_ICE_ (0x00020000)
1136 #define RX_DESC_DATA1_STATUS_TCE_ (0x00010000)
1137 #define RX_DESC_DATA1_STATUS_ICSM_ (0x00000001)
1138 #define RX_DESC_DATA2_TS_NS_MASK_ (0x3FFFFFFF)
1140 #if ((NET_IP_ALIGN != 0) && (NET_IP_ALIGN != 2))
1141 #error NET_IP_ALIGN must be 0 or 2
1153 #define RX_BUFFER_INFO_FLAG_ACTIVE BIT(0)
1164 #define RX_PROCESS_RESULT_NOTHING_TO_DO (0)