Lines Matching +full:ethernet +full:- +full:pse
1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
24 #include <linux/pcs/pcs-mtk-lynxi.h>
34 static int mtk_msg_level = -1;
36 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
285 __raw_writel(val, eth->base + reg); in mtk_w32()
290 return __raw_readl(eth->base + reg); in mtk_r32()
316 dev_err(eth->dev, "mdio: MDIO timeout\n"); in mtk_mdio_busy_wait()
317 return -ETIMEDOUT; in mtk_mdio_busy_wait()
440 struct mtk_eth *eth = bus->priv; in mtk_mdio_write_c22()
448 struct mtk_eth *eth = bus->priv; in mtk_mdio_write_c45()
455 struct mtk_eth *eth = bus->priv; in mtk_mdio_read_c22()
463 struct mtk_eth *eth = bus->priv; in mtk_mdio_read_c45()
476 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, in mt7621_gmac0_rgmii_adjust()
489 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], 500000000); in mtk_gmac0_rgmii_adjust()
491 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); in mtk_gmac0_rgmii_adjust()
495 dev_err(eth->dev, "Missing PLL configuration, ethernet may not work\n"); in mtk_gmac0_rgmii_adjust()
516 struct mtk_eth *eth = mac->hw; in mtk_mac_select_pcs()
521 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? in mtk_mac_select_pcs()
522 0 : mac->id; in mtk_mac_select_pcs()
524 return eth->sgmii_pcs[sid]; in mtk_mac_select_pcs()
535 struct mtk_eth *eth = mac->hw; in mtk_mac_config()
540 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && in mtk_mac_config()
541 mac->interface != state->interface) { in mtk_mac_config()
543 switch (state->interface) { in mtk_mac_config()
550 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) { in mtk_mac_config()
551 err = mtk_gmac_rgmii_path_setup(eth, mac->id); in mtk_mac_config()
559 err = mtk_gmac_sgmii_path_setup(eth, mac->id); in mtk_mac_config()
564 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) { in mtk_mac_config()
565 err = mtk_gmac_gephy_path_setup(eth, mac->id); in mtk_mac_config()
577 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII && in mtk_mac_config()
578 !phy_interface_mode_is_8023z(state->interface) && in mtk_mac_config()
579 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) { in mtk_mac_config()
580 if (MTK_HAS_CAPS(mac->hw->soc->caps, in mtk_mac_config()
582 if (mt7621_gmac0_rgmii_adjust(mac->hw, in mtk_mac_config()
583 state->interface)) in mtk_mac_config()
586 mtk_gmac0_rgmii_adjust(mac->hw, in mtk_mac_config()
587 state->interface); in mtk_mac_config()
591 mtk_w32(mac->hw, in mtk_mac_config()
596 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL, in mtk_mac_config()
598 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL); in mtk_mac_config()
602 switch (state->interface) { in mtk_mac_config()
613 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); in mtk_mac_config()
614 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); in mtk_mac_config()
615 val |= SYSCFG0_GE_MODE(ge_mode, mac->id); in mtk_mac_config()
616 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); in mtk_mac_config()
618 mac->interface = state->interface; in mtk_mac_config()
622 if (state->interface == PHY_INTERFACE_MODE_SGMII || in mtk_mac_config()
623 phy_interface_mode_is_8023z(state->interface)) { in mtk_mac_config()
627 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); in mtk_mac_config()
629 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, in mtk_mac_config()
634 mac->syscfg0 = val; in mtk_mac_config()
636 dev_err(eth->dev, in mtk_mac_config()
637 "In-band mode not supported in non SGMII mode!\n"); in mtk_mac_config()
643 mac->interface == PHY_INTERFACE_MODE_INTERNAL) { in mtk_mac_config()
644 mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id)); in mtk_mac_config()
645 mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id)); in mtk_mac_config()
653 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__, in mtk_mac_config()
654 mac->id, phy_modes(state->interface)); in mtk_mac_config()
658 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__, in mtk_mac_config()
659 mac->id, phy_modes(state->interface), err); in mtk_mac_config()
667 struct mtk_eth *eth = mac->hw; in mtk_mac_finish()
673 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, in mtk_mac_finish()
674 SYSCFG0_SGMII_MASK, mac->syscfg0); in mtk_mac_finish()
677 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); in mtk_mac_finish()
685 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); in mtk_mac_finish()
695 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); in mtk_mac_link_down()
698 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); in mtk_mac_link_down()
704 const struct mtk_soc_data *soc = eth->soc; in mtk_set_queue_speed()
707 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) in mtk_set_queue_speed()
767 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); in mtk_set_queue_speed()
779 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); in mtk_mac_link_up()
785 mac->speed = speed; in mtk_mac_link_up()
800 /* Configure pause modes - phylink will avoid these for half duplex */ in mtk_mac_link_up()
807 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); in mtk_mac_link_up()
825 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); in mtk_mdio_init()
827 dev_err(eth->dev, "no %s child node found", "mdio-bus"); in mtk_mdio_init()
828 return -ENODEV; in mtk_mdio_init()
832 ret = -ENODEV; in mtk_mdio_init()
836 eth->mii_bus = devm_mdiobus_alloc(eth->dev); in mtk_mdio_init()
837 if (!eth->mii_bus) { in mtk_mdio_init()
838 ret = -ENOMEM; in mtk_mdio_init()
842 eth->mii_bus->name = "mdio"; in mtk_mdio_init()
843 eth->mii_bus->read = mtk_mdio_read_c22; in mtk_mdio_init()
844 eth->mii_bus->write = mtk_mdio_write_c22; in mtk_mdio_init()
845 eth->mii_bus->read_c45 = mtk_mdio_read_c45; in mtk_mdio_init()
846 eth->mii_bus->write_c45 = mtk_mdio_write_c45; in mtk_mdio_init()
847 eth->mii_bus->priv = eth; in mtk_mdio_init()
848 eth->mii_bus->parent = eth->dev; in mtk_mdio_init()
850 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); in mtk_mdio_init()
852 if (!of_property_read_u32(mii_np, "clock-frequency", &val)) { in mtk_mdio_init()
854 dev_err(eth->dev, "MDIO clock frequency out of range"); in mtk_mdio_init()
855 ret = -EINVAL; in mtk_mdio_init()
872 dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider); in mtk_mdio_init()
874 ret = of_mdiobus_register(eth->mii_bus, mii_np); in mtk_mdio_init()
883 if (!eth->mii_bus) in mtk_mdio_cleanup()
886 mdiobus_unregister(eth->mii_bus); in mtk_mdio_cleanup()
894 spin_lock_irqsave(ð->tx_irq_lock, flags); in mtk_tx_irq_disable()
895 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); in mtk_tx_irq_disable()
896 mtk_w32(eth, val & ~mask, eth->soc->reg_map->tx_irq_mask); in mtk_tx_irq_disable()
897 spin_unlock_irqrestore(ð->tx_irq_lock, flags); in mtk_tx_irq_disable()
905 spin_lock_irqsave(ð->tx_irq_lock, flags); in mtk_tx_irq_enable()
906 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); in mtk_tx_irq_enable()
907 mtk_w32(eth, val | mask, eth->soc->reg_map->tx_irq_mask); in mtk_tx_irq_enable()
908 spin_unlock_irqrestore(ð->tx_irq_lock, flags); in mtk_tx_irq_enable()
916 spin_lock_irqsave(ð->rx_irq_lock, flags); in mtk_rx_irq_disable()
917 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); in mtk_rx_irq_disable()
918 mtk_w32(eth, val & ~mask, eth->soc->reg_map->pdma.irq_mask); in mtk_rx_irq_disable()
919 spin_unlock_irqrestore(ð->rx_irq_lock, flags); in mtk_rx_irq_disable()
927 spin_lock_irqsave(ð->rx_irq_lock, flags); in mtk_rx_irq_enable()
928 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); in mtk_rx_irq_enable()
929 mtk_w32(eth, val | mask, eth->soc->reg_map->pdma.irq_mask); in mtk_rx_irq_enable()
930 spin_unlock_irqrestore(ð->rx_irq_lock, flags); in mtk_rx_irq_enable()
937 struct mtk_eth *eth = mac->hw; in mtk_set_mac_address()
938 const char *macaddr = dev->dev_addr; in mtk_set_mac_address()
943 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) in mtk_set_mac_address()
944 return -EBUSY; in mtk_set_mac_address()
946 spin_lock_bh(&mac->hw->page_lock); in mtk_set_mac_address()
947 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { in mtk_set_mac_address()
948 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], in mtk_set_mac_address()
950 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | in mtk_set_mac_address()
954 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], in mtk_set_mac_address()
955 MTK_GDMA_MAC_ADRH(mac->id)); in mtk_set_mac_address()
956 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | in mtk_set_mac_address()
958 MTK_GDMA_MAC_ADRL(mac->id)); in mtk_set_mac_address()
960 spin_unlock_bh(&mac->hw->page_lock); in mtk_set_mac_address()
967 struct mtk_hw_stats *hw_stats = mac->hw_stats; in mtk_stats_update_mac()
968 struct mtk_eth *eth = mac->hw; in mtk_stats_update_mac()
970 u64_stats_update_begin(&hw_stats->syncp); in mtk_stats_update_mac()
972 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { in mtk_stats_update_mac()
973 hw_stats->tx_packets += mtk_r32(mac->hw, MT7628_SDM_TPCNT); in mtk_stats_update_mac()
974 hw_stats->tx_bytes += mtk_r32(mac->hw, MT7628_SDM_TBCNT); in mtk_stats_update_mac()
975 hw_stats->rx_packets += mtk_r32(mac->hw, MT7628_SDM_RPCNT); in mtk_stats_update_mac()
976 hw_stats->rx_bytes += mtk_r32(mac->hw, MT7628_SDM_RBCNT); in mtk_stats_update_mac()
977 hw_stats->rx_checksum_errors += in mtk_stats_update_mac()
978 mtk_r32(mac->hw, MT7628_SDM_CS_ERR); in mtk_stats_update_mac()
980 const struct mtk_reg_map *reg_map = eth->soc->reg_map; in mtk_stats_update_mac()
981 unsigned int offs = hw_stats->reg_offset; in mtk_stats_update_mac()
984 hw_stats->rx_bytes += mtk_r32(mac->hw, reg_map->gdm1_cnt + offs); in mtk_stats_update_mac()
985 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x4 + offs); in mtk_stats_update_mac()
987 hw_stats->rx_bytes += (stats << 32); in mtk_stats_update_mac()
988 hw_stats->rx_packets += in mtk_stats_update_mac()
989 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x8 + offs); in mtk_stats_update_mac()
990 hw_stats->rx_overflow += in mtk_stats_update_mac()
991 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x10 + offs); in mtk_stats_update_mac()
992 hw_stats->rx_fcs_errors += in mtk_stats_update_mac()
993 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x14 + offs); in mtk_stats_update_mac()
994 hw_stats->rx_short_errors += in mtk_stats_update_mac()
995 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x18 + offs); in mtk_stats_update_mac()
996 hw_stats->rx_long_errors += in mtk_stats_update_mac()
997 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x1c + offs); in mtk_stats_update_mac()
998 hw_stats->rx_checksum_errors += in mtk_stats_update_mac()
999 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs); in mtk_stats_update_mac()
1000 hw_stats->rx_flow_control_packets += in mtk_stats_update_mac()
1001 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs); in mtk_stats_update_mac()
1004 hw_stats->tx_skip += in mtk_stats_update_mac()
1005 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x50 + offs); in mtk_stats_update_mac()
1006 hw_stats->tx_collisions += in mtk_stats_update_mac()
1007 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x54 + offs); in mtk_stats_update_mac()
1008 hw_stats->tx_bytes += in mtk_stats_update_mac()
1009 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x40 + offs); in mtk_stats_update_mac()
1010 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x44 + offs); in mtk_stats_update_mac()
1012 hw_stats->tx_bytes += (stats << 32); in mtk_stats_update_mac()
1013 hw_stats->tx_packets += in mtk_stats_update_mac()
1014 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x48 + offs); in mtk_stats_update_mac()
1016 hw_stats->tx_skip += in mtk_stats_update_mac()
1017 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs); in mtk_stats_update_mac()
1018 hw_stats->tx_collisions += in mtk_stats_update_mac()
1019 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs); in mtk_stats_update_mac()
1020 hw_stats->tx_bytes += in mtk_stats_update_mac()
1021 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs); in mtk_stats_update_mac()
1022 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs); in mtk_stats_update_mac()
1024 hw_stats->tx_bytes += (stats << 32); in mtk_stats_update_mac()
1025 hw_stats->tx_packets += in mtk_stats_update_mac()
1026 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs); in mtk_stats_update_mac()
1030 u64_stats_update_end(&hw_stats->syncp); in mtk_stats_update_mac()
1038 if (!eth->mac[i] || !eth->mac[i]->hw_stats) in mtk_stats_update()
1040 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { in mtk_stats_update()
1041 mtk_stats_update_mac(eth->mac[i]); in mtk_stats_update()
1042 spin_unlock(ð->mac[i]->hw_stats->stats_lock); in mtk_stats_update()
1051 struct mtk_hw_stats *hw_stats = mac->hw_stats; in mtk_get_stats64()
1055 if (spin_trylock_bh(&hw_stats->stats_lock)) { in mtk_get_stats64()
1057 spin_unlock_bh(&hw_stats->stats_lock); in mtk_get_stats64()
1062 start = u64_stats_fetch_begin(&hw_stats->syncp); in mtk_get_stats64()
1063 storage->rx_packets = hw_stats->rx_packets; in mtk_get_stats64()
1064 storage->tx_packets = hw_stats->tx_packets; in mtk_get_stats64()
1065 storage->rx_bytes = hw_stats->rx_bytes; in mtk_get_stats64()
1066 storage->tx_bytes = hw_stats->tx_bytes; in mtk_get_stats64()
1067 storage->collisions = hw_stats->tx_collisions; in mtk_get_stats64()
1068 storage->rx_length_errors = hw_stats->rx_short_errors + in mtk_get_stats64()
1069 hw_stats->rx_long_errors; in mtk_get_stats64()
1070 storage->rx_over_errors = hw_stats->rx_overflow; in mtk_get_stats64()
1071 storage->rx_crc_errors = hw_stats->rx_fcs_errors; in mtk_get_stats64()
1072 storage->rx_errors = hw_stats->rx_checksum_errors; in mtk_get_stats64()
1073 storage->tx_aborted_errors = hw_stats->tx_skip; in mtk_get_stats64()
1074 } while (u64_stats_fetch_retry(&hw_stats->syncp, start)); in mtk_get_stats64()
1076 storage->tx_errors = dev->stats.tx_errors; in mtk_get_stats64()
1077 storage->rx_dropped = dev->stats.rx_dropped; in mtk_get_stats64()
1078 storage->tx_dropped = dev->stats.tx_dropped; in mtk_get_stats64()
1085 mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; in mtk_max_frag_size()
1093 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - in mtk_max_buf_size()
1104 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); in mtk_rx_get_desc()
1105 if (!(rxd->rxd2 & RX_DMA_DONE)) in mtk_rx_get_desc()
1108 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); in mtk_rx_get_desc()
1109 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); in mtk_rx_get_desc()
1110 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); in mtk_rx_get_desc()
1112 rxd->rxd5 = READ_ONCE(dma_rxd->rxd5); in mtk_rx_get_desc()
1113 rxd->rxd6 = READ_ONCE(dma_rxd->rxd6); in mtk_rx_get_desc()
1133 const struct mtk_soc_data *soc = eth->soc; in mtk_init_fq_dma()
1139 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) in mtk_init_fq_dma()
1140 eth->scratch_ring = eth->sram_base; in mtk_init_fq_dma()
1142 eth->scratch_ring = dma_alloc_coherent(eth->dma_dev, in mtk_init_fq_dma()
1143 cnt * soc->txrx.txd_size, in mtk_init_fq_dma()
1144 ð->phy_scratch_ring, in mtk_init_fq_dma()
1146 if (unlikely(!eth->scratch_ring)) in mtk_init_fq_dma()
1147 return -ENOMEM; in mtk_init_fq_dma()
1149 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, GFP_KERNEL); in mtk_init_fq_dma()
1150 if (unlikely(!eth->scratch_head)) in mtk_init_fq_dma()
1151 return -ENOMEM; in mtk_init_fq_dma()
1153 dma_addr = dma_map_single(eth->dma_dev, in mtk_init_fq_dma()
1154 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, in mtk_init_fq_dma()
1156 if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) in mtk_init_fq_dma()
1157 return -ENOMEM; in mtk_init_fq_dma()
1159 phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1); in mtk_init_fq_dma()
1165 txd = eth->scratch_ring + i * soc->txrx.txd_size; in mtk_init_fq_dma()
1166 txd->txd1 = addr; in mtk_init_fq_dma()
1167 if (i < cnt - 1) in mtk_init_fq_dma()
1168 txd->txd2 = eth->phy_scratch_ring + in mtk_init_fq_dma()
1169 (i + 1) * soc->txrx.txd_size; in mtk_init_fq_dma()
1171 txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE); in mtk_init_fq_dma()
1172 if (MTK_HAS_CAPS(soc->caps, MTK_36BIT_DMA)) in mtk_init_fq_dma()
1173 txd->txd3 |= TX_DMA_PREP_ADDR64(addr); in mtk_init_fq_dma()
1174 txd->txd4 = 0; in mtk_init_fq_dma()
1176 txd->txd5 = 0; in mtk_init_fq_dma()
1177 txd->txd6 = 0; in mtk_init_fq_dma()
1178 txd->txd7 = 0; in mtk_init_fq_dma()
1179 txd->txd8 = 0; in mtk_init_fq_dma()
1183 mtk_w32(eth, eth->phy_scratch_ring, soc->reg_map->qdma.fq_head); in mtk_init_fq_dma()
1184 mtk_w32(eth, phy_ring_tail, soc->reg_map->qdma.fq_tail); in mtk_init_fq_dma()
1185 mtk_w32(eth, (cnt << 16) | cnt, soc->reg_map->qdma.fq_count); in mtk_init_fq_dma()
1186 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, soc->reg_map->qdma.fq_blen); in mtk_init_fq_dma()
1193 return ring->dma + (desc - ring->phys); in mtk_qdma_phys_to_virt()
1199 int idx = (txd - ring->dma) / txd_size; in mtk_desc_to_tx_buf()
1201 return &ring->buf[idx]; in mtk_desc_to_tx_buf()
1207 return ring->dma_pdma - (struct mtk_tx_dma *)ring->dma + dma; in qdma_to_pdma()
1212 return (dma - ring->dma) / txd_size; in txd_to_idx()
1218 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { in mtk_tx_unmap()
1219 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { in mtk_tx_unmap()
1220 dma_unmap_single(eth->dma_dev, in mtk_tx_unmap()
1224 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { in mtk_tx_unmap()
1225 dma_unmap_page(eth->dma_dev, in mtk_tx_unmap()
1232 dma_unmap_page(eth->dma_dev, in mtk_tx_unmap()
1239 dma_unmap_page(eth->dma_dev, in mtk_tx_unmap()
1246 if (tx_buf->data && tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { in mtk_tx_unmap()
1247 if (tx_buf->type == MTK_TYPE_SKB) { in mtk_tx_unmap()
1248 struct sk_buff *skb = tx_buf->data; in mtk_tx_unmap()
1255 struct xdp_frame *xdpf = tx_buf->data; in mtk_tx_unmap()
1257 if (napi && tx_buf->type == MTK_TYPE_XDP_TX) in mtk_tx_unmap()
1265 tx_buf->flags = 0; in mtk_tx_unmap()
1266 tx_buf->data = NULL; in mtk_tx_unmap()
1273 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { in setup_tx_buf()
1278 txd->txd3 = mapped_addr; in setup_tx_buf()
1279 txd->txd2 |= TX_DMA_PLEN1(size); in setup_tx_buf()
1283 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; in setup_tx_buf()
1284 txd->txd1 = mapped_addr; in setup_tx_buf()
1285 txd->txd2 = TX_DMA_PLEN0(size); in setup_tx_buf()
1296 struct mtk_eth *eth = mac->hw; in mtk_tx_set_dma_desc_v1()
1300 WRITE_ONCE(desc->txd1, info->addr); in mtk_tx_set_dma_desc_v1()
1302 data = TX_DMA_SWC | TX_DMA_PLEN0(info->size) | in mtk_tx_set_dma_desc_v1()
1303 FIELD_PREP(TX_DMA_PQID, info->qid); in mtk_tx_set_dma_desc_v1()
1304 if (info->last) in mtk_tx_set_dma_desc_v1()
1306 WRITE_ONCE(desc->txd3, data); in mtk_tx_set_dma_desc_v1()
1308 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT; /* forward port */ in mtk_tx_set_dma_desc_v1()
1309 if (info->first) { in mtk_tx_set_dma_desc_v1()
1310 if (info->gso) in mtk_tx_set_dma_desc_v1()
1313 if (info->csum) in mtk_tx_set_dma_desc_v1()
1316 if (info->vlan) in mtk_tx_set_dma_desc_v1()
1317 data |= TX_DMA_INS_VLAN | info->vlan_tci; in mtk_tx_set_dma_desc_v1()
1319 WRITE_ONCE(desc->txd4, data); in mtk_tx_set_dma_desc_v1()
1327 struct mtk_eth *eth = mac->hw; in mtk_tx_set_dma_desc_v2()
1330 WRITE_ONCE(desc->txd1, info->addr); in mtk_tx_set_dma_desc_v2()
1332 data = TX_DMA_PLEN0(info->size); in mtk_tx_set_dma_desc_v2()
1333 if (info->last) in mtk_tx_set_dma_desc_v2()
1336 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) in mtk_tx_set_dma_desc_v2()
1337 data |= TX_DMA_PREP_ADDR64(info->addr); in mtk_tx_set_dma_desc_v2()
1339 WRITE_ONCE(desc->txd3, data); in mtk_tx_set_dma_desc_v2()
1342 switch (mac->id) { in mtk_tx_set_dma_desc_v2()
1354 data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); in mtk_tx_set_dma_desc_v2()
1355 WRITE_ONCE(desc->txd4, data); in mtk_tx_set_dma_desc_v2()
1358 if (info->first) { in mtk_tx_set_dma_desc_v2()
1359 if (info->gso) in mtk_tx_set_dma_desc_v2()
1362 if (info->csum) in mtk_tx_set_dma_desc_v2()
1367 WRITE_ONCE(desc->txd5, data); in mtk_tx_set_dma_desc_v2()
1370 if (info->first && info->vlan) in mtk_tx_set_dma_desc_v2()
1371 data |= TX_DMA_INS_VLAN_V2 | info->vlan_tci; in mtk_tx_set_dma_desc_v2()
1372 WRITE_ONCE(desc->txd6, data); in mtk_tx_set_dma_desc_v2()
1374 WRITE_ONCE(desc->txd7, 0); in mtk_tx_set_dma_desc_v2()
1375 WRITE_ONCE(desc->txd8, 0); in mtk_tx_set_dma_desc_v2()
1382 struct mtk_eth *eth = mac->hw; in mtk_tx_set_dma_desc()
1396 .csum = skb->ip_summed == CHECKSUM_PARTIAL, in mtk_tx_map()
1405 struct mtk_eth *eth = mac->hw; in mtk_tx_map()
1406 const struct mtk_soc_data *soc = eth->soc; in mtk_tx_map()
1415 itxd = ring->next_free; in mtk_tx_map()
1417 if (itxd == ring->last_free) in mtk_tx_map()
1418 return -ENOMEM; in mtk_tx_map()
1420 itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size); in mtk_tx_map()
1423 txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size, in mtk_tx_map()
1425 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) in mtk_tx_map()
1426 return -ENOMEM; in mtk_tx_map()
1430 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; in mtk_tx_map()
1431 itx_buf->mac_id = mac->id; in mtk_tx_map()
1439 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { in mtk_tx_map()
1440 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; in mtk_tx_map()
1447 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || in mtk_tx_map()
1449 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); in mtk_tx_map()
1451 if (txd == ring->last_free) in mtk_tx_map()
1461 soc->txrx.dma_max_len); in mtk_tx_map()
1463 txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 && in mtk_tx_map()
1464 !(frag_size - txd_info.size); in mtk_tx_map()
1465 txd_info.addr = skb_frag_dma_map(eth->dma_dev, frag, in mtk_tx_map()
1468 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) in mtk_tx_map()
1474 soc->txrx.txd_size); in mtk_tx_map()
1477 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; in mtk_tx_map()
1478 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; in mtk_tx_map()
1479 tx_buf->mac_id = mac->id; in mtk_tx_map()
1484 frag_size -= txd_info.size; in mtk_tx_map()
1490 itx_buf->type = MTK_TYPE_SKB; in mtk_tx_map()
1491 itx_buf->data = skb; in mtk_tx_map()
1493 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { in mtk_tx_map()
1495 txd_pdma->txd2 |= TX_DMA_LS0; in mtk_tx_map()
1497 txd_pdma->txd2 |= TX_DMA_LS1; in mtk_tx_map()
1500 netdev_tx_sent_queue(txq, skb->len); in mtk_tx_map()
1503 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); in mtk_tx_map()
1504 atomic_sub(n_desc, &ring->free_count); in mtk_tx_map()
1511 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { in mtk_tx_map()
1513 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); in mtk_tx_map()
1517 next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->txrx.txd_size), in mtk_tx_map()
1518 ring->dma_size); in mtk_tx_map()
1526 tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size); in mtk_tx_map()
1531 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; in mtk_tx_map()
1532 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) in mtk_tx_map()
1533 itxd_pdma->txd2 = TX_DMA_DESP2_DEF; in mtk_tx_map()
1535 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); in mtk_tx_map()
1539 return -ENOMEM; in mtk_tx_map()
1548 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { in mtk_cal_txd_req()
1549 frag = &skb_shinfo(skb)->frags[i]; in mtk_cal_txd_req()
1551 eth->soc->txrx.dma_max_len); in mtk_cal_txd_req()
1554 nfrags += skb_shinfo(skb)->nr_frags; in mtk_cal_txd_req()
1565 if (!eth->netdev[i]) in mtk_queue_stopped()
1567 if (netif_queue_stopped(eth->netdev[i])) in mtk_queue_stopped()
1579 if (!eth->netdev[i]) in mtk_wake_queue()
1581 netif_tx_wake_all_queues(eth->netdev[i]); in mtk_wake_queue()
1588 struct mtk_eth *eth = mac->hw; in mtk_start_xmit()
1589 struct mtk_tx_ring *ring = ð->tx_ring; in mtk_start_xmit()
1590 struct net_device_stats *stats = &dev->stats; in mtk_start_xmit()
1598 spin_lock(ð->page_lock); in mtk_start_xmit()
1600 if (unlikely(test_bit(MTK_RESETTING, ð->state))) in mtk_start_xmit()
1604 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { in mtk_start_xmit()
1608 spin_unlock(ð->page_lock); in mtk_start_xmit()
1620 if (skb_shinfo(skb)->gso_type & in mtk_start_xmit()
1623 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); in mtk_start_xmit()
1630 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) in mtk_start_xmit()
1633 spin_unlock(ð->page_lock); in mtk_start_xmit()
1638 spin_unlock(ð->page_lock); in mtk_start_xmit()
1639 stats->tx_dropped++; in mtk_start_xmit()
1650 if (!eth->hwlro) in mtk_get_rx_ring()
1651 return ð->rx_ring[0]; in mtk_get_rx_ring()
1656 ring = ð->rx_ring[i]; in mtk_get_rx_ring()
1657 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); in mtk_get_rx_ring()
1658 rxd = ring->dma + idx * eth->soc->txrx.rxd_size; in mtk_get_rx_ring()
1659 if (rxd->rxd2 & RX_DMA_DONE) { in mtk_get_rx_ring()
1660 ring->calc_idx_update = true; in mtk_get_rx_ring()
1673 if (!eth->hwlro) { in mtk_update_rx_cpu_idx()
1674 ring = ð->rx_ring[0]; in mtk_update_rx_cpu_idx()
1675 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); in mtk_update_rx_cpu_idx()
1678 ring = ð->rx_ring[i]; in mtk_update_rx_cpu_idx()
1679 if (ring->calc_idx_update) { in mtk_update_rx_cpu_idx()
1680 ring->calc_idx_update = false; in mtk_update_rx_cpu_idx()
1681 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); in mtk_update_rx_cpu_idx()
1701 .dev = eth->dma_dev, in mtk_create_page_pool()
1708 pp_params.dma_dir = rcu_access_pointer(eth->prog) ? DMA_BIDIRECTIONAL in mtk_create_page_pool()
1714 err = __xdp_rxq_info_reg(xdp_q, ð->dummy_dev, id, in mtk_create_page_pool()
1715 eth->rx_napi.napi_id, PAGE_SIZE); in mtk_create_page_pool()
1748 if (ring->page_pool) in mtk_rx_put_buff()
1749 page_pool_put_full_page(ring->page_pool, in mtk_rx_put_buff()
1760 struct mtk_tx_ring *ring = ð->tx_ring; in mtk_xdp_frame_map()
1765 txd_info->addr = dma_map_single(eth->dma_dev, data, in mtk_xdp_frame_map()
1766 txd_info->size, DMA_TO_DEVICE); in mtk_xdp_frame_map()
1767 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info->addr))) in mtk_xdp_frame_map()
1768 return -ENOMEM; in mtk_xdp_frame_map()
1770 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0; in mtk_xdp_frame_map()
1774 txd_info->addr = page_pool_get_dma_addr(page) + in mtk_xdp_frame_map()
1776 dma_sync_single_for_device(eth->dma_dev, txd_info->addr, in mtk_xdp_frame_map()
1777 txd_info->size, DMA_BIDIRECTIONAL); in mtk_xdp_frame_map()
1781 tx_buf->mac_id = mac->id; in mtk_xdp_frame_map()
1782 tx_buf->type = dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX; in mtk_xdp_frame_map()
1783 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; in mtk_xdp_frame_map()
1786 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info->addr, txd_info->size, in mtk_xdp_frame_map()
1796 const struct mtk_soc_data *soc = eth->soc; in mtk_xdp_submit_frame()
1797 struct mtk_tx_ring *ring = ð->tx_ring; in mtk_xdp_submit_frame()
1800 .size = xdpf->len, in mtk_xdp_submit_frame()
1803 .qid = mac->id, in mtk_xdp_submit_frame()
1808 void *data = xdpf->data; in mtk_xdp_submit_frame()
1810 if (unlikely(test_bit(MTK_RESETTING, ð->state))) in mtk_xdp_submit_frame()
1811 return -EBUSY; in mtk_xdp_submit_frame()
1813 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; in mtk_xdp_submit_frame()
1814 if (unlikely(atomic_read(&ring->free_count) <= 1 + nr_frags)) in mtk_xdp_submit_frame()
1815 return -EBUSY; in mtk_xdp_submit_frame()
1817 spin_lock(ð->page_lock); in mtk_xdp_submit_frame()
1819 txd = ring->next_free; in mtk_xdp_submit_frame()
1820 if (txd == ring->last_free) { in mtk_xdp_submit_frame()
1821 spin_unlock(ð->page_lock); in mtk_xdp_submit_frame()
1822 return -ENOMEM; in mtk_xdp_submit_frame()
1826 tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->txrx.txd_size); in mtk_xdp_submit_frame()
1832 data, xdpf->headroom, index, dma_map); in mtk_xdp_submit_frame()
1839 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || (index & 0x1)) { in mtk_xdp_submit_frame()
1840 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); in mtk_xdp_submit_frame()
1841 if (txd == ring->last_free) in mtk_xdp_submit_frame()
1845 soc->txrx.txd_size); in mtk_xdp_submit_frame()
1851 txd_info.size = skb_frag_size(&sinfo->frags[index]); in mtk_xdp_submit_frame()
1853 txd_info.qid = mac->id; in mtk_xdp_submit_frame()
1854 data = skb_frag_address(&sinfo->frags[index]); in mtk_xdp_submit_frame()
1859 htx_buf->data = xdpf; in mtk_xdp_submit_frame()
1861 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { in mtk_xdp_submit_frame()
1865 txd_pdma->txd2 |= TX_DMA_LS0; in mtk_xdp_submit_frame()
1867 txd_pdma->txd2 |= TX_DMA_LS1; in mtk_xdp_submit_frame()
1870 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); in mtk_xdp_submit_frame()
1871 atomic_sub(n_desc, &ring->free_count); in mtk_xdp_submit_frame()
1878 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { in mtk_xdp_submit_frame()
1879 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); in mtk_xdp_submit_frame()
1883 idx = txd_to_idx(ring, txd, soc->txrx.txd_size); in mtk_xdp_submit_frame()
1884 mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size), in mtk_xdp_submit_frame()
1888 spin_unlock(ð->page_lock); in mtk_xdp_submit_frame()
1894 tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->txrx.txd_size); in mtk_xdp_submit_frame()
1897 htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; in mtk_xdp_submit_frame()
1898 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { in mtk_xdp_submit_frame()
1901 txd_pdma->txd2 = TX_DMA_DESP2_DEF; in mtk_xdp_submit_frame()
1904 htxd = mtk_qdma_phys_to_virt(ring, htxd->txd2); in mtk_xdp_submit_frame()
1907 spin_unlock(ð->page_lock); in mtk_xdp_submit_frame()
1916 struct mtk_hw_stats *hw_stats = mac->hw_stats; in mtk_xdp_xmit()
1917 struct mtk_eth *eth = mac->hw; in mtk_xdp_xmit()
1921 return -EINVAL; in mtk_xdp_xmit()
1929 u64_stats_update_begin(&hw_stats->syncp); in mtk_xdp_xmit()
1930 hw_stats->xdp_stats.tx_xdp_xmit += nxmit; in mtk_xdp_xmit()
1931 hw_stats->xdp_stats.tx_xdp_xmit_errors += num_frame - nxmit; in mtk_xdp_xmit()
1932 u64_stats_update_end(&hw_stats->syncp); in mtk_xdp_xmit()
1941 struct mtk_hw_stats *hw_stats = mac->hw_stats; in mtk_xdp_run()
1942 u64 *count = &hw_stats->xdp_stats.rx_xdp_drop; in mtk_xdp_run()
1948 prog = rcu_dereference(eth->prog); in mtk_xdp_run()
1955 count = &hw_stats->xdp_stats.rx_xdp_pass; in mtk_xdp_run()
1963 count = &hw_stats->xdp_stats.rx_xdp_redirect; in mtk_xdp_run()
1969 count = &hw_stats->xdp_stats.rx_xdp_tx_errors; in mtk_xdp_run()
1974 count = &hw_stats->xdp_stats.rx_xdp_tx; in mtk_xdp_run()
1987 page_pool_put_full_page(ring->page_pool, in mtk_xdp_run()
1988 virt_to_head_page(xdp->data), true); in mtk_xdp_run()
1991 u64_stats_update_begin(&hw_stats->syncp); in mtk_xdp_run()
1993 u64_stats_update_end(&hw_stats->syncp); in mtk_xdp_run()
2024 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); in mtk_poll_rx()
2025 rxd = ring->dma + idx * eth->soc->txrx.rxd_size; in mtk_poll_rx()
2026 data = ring->data[idx]; in mtk_poll_rx()
2038 mac = val - 1; in mtk_poll_rx()
2046 } else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && in mtk_poll_rx()
2048 mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1; in mtk_poll_rx()
2052 !eth->netdev[mac])) in mtk_poll_rx()
2055 netdev = eth->netdev[mac]; in mtk_poll_rx()
2057 if (unlikely(test_bit(MTK_RESETTING, ð->state))) in mtk_poll_rx()
2063 if (ring->page_pool) { in mtk_poll_rx()
2068 new_data = mtk_page_pool_get_buff(ring->page_pool, in mtk_poll_rx()
2072 netdev->stats.rx_dropped++; in mtk_poll_rx()
2076 dma_sync_single_for_cpu(eth->dma_dev, in mtk_poll_rx()
2078 pktlen, page_pool_get_dma_dir(ring->page_pool)); in mtk_poll_rx()
2080 xdp_init_buff(&xdp, PAGE_SIZE, &ring->xdp_q); in mtk_poll_rx()
2094 page_pool_put_full_page(ring->page_pool, in mtk_poll_rx()
2096 netdev->stats.rx_dropped++; in mtk_poll_rx()
2100 skb_reserve(skb, xdp.data - xdp.data_hard_start); in mtk_poll_rx()
2101 skb_put(skb, xdp.data_end - xdp.data); in mtk_poll_rx()
2104 if (ring->frag_size <= PAGE_SIZE) in mtk_poll_rx()
2105 new_data = napi_alloc_frag(ring->frag_size); in mtk_poll_rx()
2110 netdev->stats.rx_dropped++; in mtk_poll_rx()
2114 dma_addr = dma_map_single(eth->dma_dev, in mtk_poll_rx()
2115 new_data + NET_SKB_PAD + eth->ip_align, in mtk_poll_rx()
2116 ring->buf_size, DMA_FROM_DEVICE); in mtk_poll_rx()
2117 if (unlikely(dma_mapping_error(eth->dma_dev, in mtk_poll_rx()
2120 netdev->stats.rx_dropped++; in mtk_poll_rx()
2124 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) in mtk_poll_rx()
2127 dma_unmap_single(eth->dma_dev, ((u64)trxd.rxd1 | addr64), in mtk_poll_rx()
2128 ring->buf_size, DMA_FROM_DEVICE); in mtk_poll_rx()
2130 skb = build_skb(data, ring->frag_size); in mtk_poll_rx()
2132 netdev->stats.rx_dropped++; in mtk_poll_rx()
2141 skb->dev = netdev; in mtk_poll_rx()
2142 bytes += skb->len; in mtk_poll_rx()
2160 if (*rxdcsum & eth->soc->txrx.rx_dma_l4_valid) in mtk_poll_rx()
2161 skb->ip_summed = CHECKSUM_UNNECESSARY; in mtk_poll_rx()
2164 skb->protocol = eth_type_trans(skb, netdev); in mtk_poll_rx()
2173 if (port < ARRAY_SIZE(eth->dsa_meta) && in mtk_poll_rx()
2174 eth->dsa_meta[port]) in mtk_poll_rx()
2175 skb_dst_set_noref(skb, ð->dsa_meta[port]->dst); in mtk_poll_rx()
2179 mtk_ppe_check_skb(eth->ppe[0], skb, hash); in mtk_poll_rx()
2185 ring->data[idx] = new_data; in mtk_poll_rx()
2186 rxd->rxd1 = (unsigned int)dma_addr; in mtk_poll_rx()
2188 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) in mtk_poll_rx()
2189 rxd->rxd2 = RX_DMA_LSO; in mtk_poll_rx()
2191 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); in mtk_poll_rx()
2193 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA) && in mtk_poll_rx()
2195 rxd->rxd2 |= RX_DMA_PREP_ADDR64(dma_addr); in mtk_poll_rx()
2197 ring->calc_idx = idx; in mtk_poll_rx()
2210 eth->rx_packets += done; in mtk_poll_rx()
2211 eth->rx_bytes += bytes; in mtk_poll_rx()
2212 dim_update_sample(eth->rx_events, eth->rx_packets, eth->rx_bytes, in mtk_poll_rx()
2214 net_dim(ð->rx_dim, dim_sample); in mtk_poll_rx()
2235 unsigned int bytes = skb->len; in mtk_poll_tx_done()
2237 state->total++; in mtk_poll_tx_done()
2238 eth->tx_packets++; in mtk_poll_tx_done()
2239 eth->tx_bytes += bytes; in mtk_poll_tx_done()
2241 dev = eth->netdev[mac]; in mtk_poll_tx_done()
2246 if (state->txq == txq) { in mtk_poll_tx_done()
2247 state->done++; in mtk_poll_tx_done()
2248 state->bytes += bytes; in mtk_poll_tx_done()
2252 if (state->txq) in mtk_poll_tx_done()
2253 netdev_tx_completed_queue(state->txq, state->done, state->bytes); in mtk_poll_tx_done()
2255 state->txq = txq; in mtk_poll_tx_done()
2256 state->done = 1; in mtk_poll_tx_done()
2257 state->bytes = bytes; in mtk_poll_tx_done()
2263 const struct mtk_reg_map *reg_map = eth->soc->reg_map; in mtk_poll_tx_qdma()
2264 struct mtk_tx_ring *ring = ð->tx_ring; in mtk_poll_tx_qdma()
2270 cpu = ring->last_free_ptr; in mtk_poll_tx_qdma()
2271 dma = mtk_r32(eth, reg_map->qdma.drx_ptr); in mtk_poll_tx_qdma()
2277 u32 next_cpu = desc->txd2; in mtk_poll_tx_qdma()
2279 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); in mtk_poll_tx_qdma()
2280 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) in mtk_poll_tx_qdma()
2284 eth->soc->txrx.txd_size); in mtk_poll_tx_qdma()
2285 if (!tx_buf->data) in mtk_poll_tx_qdma()
2288 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { in mtk_poll_tx_qdma()
2289 if (tx_buf->type == MTK_TYPE_SKB) in mtk_poll_tx_qdma()
2290 mtk_poll_tx_done(eth, state, tx_buf->mac_id, in mtk_poll_tx_qdma()
2291 tx_buf->data); in mtk_poll_tx_qdma()
2293 budget--; in mtk_poll_tx_qdma()
2297 ring->last_free = desc; in mtk_poll_tx_qdma()
2298 atomic_inc(&ring->free_count); in mtk_poll_tx_qdma()
2304 ring->last_free_ptr = cpu; in mtk_poll_tx_qdma()
2305 mtk_w32(eth, cpu, reg_map->qdma.crx_ptr); in mtk_poll_tx_qdma()
2313 struct mtk_tx_ring *ring = ð->tx_ring; in mtk_poll_tx_pdma()
2319 cpu = ring->cpu_idx; in mtk_poll_tx_pdma()
2324 tx_buf = &ring->buf[cpu]; in mtk_poll_tx_pdma()
2325 if (!tx_buf->data) in mtk_poll_tx_pdma()
2328 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { in mtk_poll_tx_pdma()
2329 if (tx_buf->type == MTK_TYPE_SKB) in mtk_poll_tx_pdma()
2330 mtk_poll_tx_done(eth, state, 0, tx_buf->data); in mtk_poll_tx_pdma()
2331 budget--; in mtk_poll_tx_pdma()
2335 desc = ring->dma + cpu * eth->soc->txrx.txd_size; in mtk_poll_tx_pdma()
2336 ring->last_free = desc; in mtk_poll_tx_pdma()
2337 atomic_inc(&ring->free_count); in mtk_poll_tx_pdma()
2339 cpu = NEXT_DESP_IDX(cpu, ring->dma_size); in mtk_poll_tx_pdma()
2343 ring->cpu_idx = cpu; in mtk_poll_tx_pdma()
2350 struct mtk_tx_ring *ring = ð->tx_ring; in mtk_poll_tx()
2354 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) in mtk_poll_tx()
2362 dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes, in mtk_poll_tx()
2364 net_dim(ð->tx_dim, dim_sample); in mtk_poll_tx()
2367 (atomic_read(&ring->free_count) > ring->thresh)) in mtk_poll_tx()
2387 const struct mtk_reg_map *reg_map = eth->soc->reg_map; in mtk_napi_tx()
2390 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) in mtk_napi_tx()
2392 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->tx_irq_status); in mtk_napi_tx()
2396 dev_info(eth->dev, in mtk_napi_tx()
2398 mtk_r32(eth, reg_map->tx_irq_status), in mtk_napi_tx()
2399 mtk_r32(eth, reg_map->tx_irq_mask)); in mtk_napi_tx()
2405 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) in mtk_napi_tx()
2417 const struct mtk_reg_map *reg_map = eth->soc->reg_map; in mtk_napi_rx()
2425 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, in mtk_napi_rx()
2426 reg_map->pdma.irq_status); in mtk_napi_rx()
2427 rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth); in mtk_napi_rx()
2431 dev_info(eth->dev, in mtk_napi_rx()
2433 mtk_r32(eth, reg_map->pdma.irq_status), in mtk_napi_rx()
2434 mtk_r32(eth, reg_map->pdma.irq_mask)); in mtk_napi_rx()
2440 } while (mtk_r32(eth, reg_map->pdma.irq_status) & in mtk_napi_rx()
2441 eth->soc->txrx.rx_irq_done_mask); in mtk_napi_rx()
2444 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); in mtk_napi_rx()
2451 const struct mtk_soc_data *soc = eth->soc; in mtk_tx_alloc()
2452 struct mtk_tx_ring *ring = ð->tx_ring; in mtk_tx_alloc()
2453 int i, sz = soc->txrx.txd_size; in mtk_tx_alloc()
2458 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) in mtk_tx_alloc()
2463 ring->buf = kcalloc(ring_size, sizeof(*ring->buf), in mtk_tx_alloc()
2465 if (!ring->buf) in mtk_tx_alloc()
2468 if (MTK_HAS_CAPS(soc->caps, MTK_SRAM)) { in mtk_tx_alloc()
2469 ring->dma = eth->sram_base + ring_size * sz; in mtk_tx_alloc()
2470 ring->phys = eth->phy_scratch_ring + ring_size * (dma_addr_t)sz; in mtk_tx_alloc()
2472 ring->dma = dma_alloc_coherent(eth->dma_dev, ring_size * sz, in mtk_tx_alloc()
2473 &ring->phys, GFP_KERNEL); in mtk_tx_alloc()
2476 if (!ring->dma) in mtk_tx_alloc()
2481 u32 next_ptr = ring->phys + next * sz; in mtk_tx_alloc()
2483 txd = ring->dma + i * sz; in mtk_tx_alloc()
2484 txd->txd2 = next_ptr; in mtk_tx_alloc()
2485 txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; in mtk_tx_alloc()
2486 txd->txd4 = 0; in mtk_tx_alloc()
2488 txd->txd5 = 0; in mtk_tx_alloc()
2489 txd->txd6 = 0; in mtk_tx_alloc()
2490 txd->txd7 = 0; in mtk_tx_alloc()
2491 txd->txd8 = 0; in mtk_tx_alloc()
2495 /* On MT7688 (PDMA only) this driver uses the ring->dma structs in mtk_tx_alloc()
2497 * descriptors in ring->dma_pdma. in mtk_tx_alloc()
2499 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { in mtk_tx_alloc()
2500 ring->dma_pdma = dma_alloc_coherent(eth->dma_dev, ring_size * sz, in mtk_tx_alloc()
2501 &ring->phys_pdma, GFP_KERNEL); in mtk_tx_alloc()
2502 if (!ring->dma_pdma) in mtk_tx_alloc()
2506 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF; in mtk_tx_alloc()
2507 ring->dma_pdma[i].txd4 = 0; in mtk_tx_alloc()
2511 ring->dma_size = ring_size; in mtk_tx_alloc()
2512 atomic_set(&ring->free_count, ring_size - 2); in mtk_tx_alloc()
2513 ring->next_free = ring->dma; in mtk_tx_alloc()
2514 ring->last_free = (void *)txd; in mtk_tx_alloc()
2515 ring->last_free_ptr = (u32)(ring->phys + ((ring_size - 1) * sz)); in mtk_tx_alloc()
2516 ring->thresh = MAX_SKB_FRAGS; in mtk_tx_alloc()
2523 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { in mtk_tx_alloc()
2524 mtk_w32(eth, ring->phys, soc->reg_map->qdma.ctx_ptr); in mtk_tx_alloc()
2525 mtk_w32(eth, ring->phys, soc->reg_map->qdma.dtx_ptr); in mtk_tx_alloc()
2527 ring->phys + ((ring_size - 1) * sz), in mtk_tx_alloc()
2528 soc->reg_map->qdma.crx_ptr); in mtk_tx_alloc()
2529 mtk_w32(eth, ring->last_free_ptr, soc->reg_map->qdma.drx_ptr); in mtk_tx_alloc()
2533 mtk_w32(eth, val, soc->reg_map->qdma.qtx_cfg + ofs); in mtk_tx_alloc()
2542 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); in mtk_tx_alloc()
2546 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate); in mtk_tx_alloc()
2548 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4); in mtk_tx_alloc()
2550 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0); in mtk_tx_alloc()
2553 mtk_w32(eth, MT7628_PST_DTX_IDX0, soc->reg_map->pdma.rst_idx); in mtk_tx_alloc()
2559 return -ENOMEM; in mtk_tx_alloc()
2564 const struct mtk_soc_data *soc = eth->soc; in mtk_tx_clean()
2565 struct mtk_tx_ring *ring = ð->tx_ring; in mtk_tx_clean()
2568 if (ring->buf) { in mtk_tx_clean()
2569 for (i = 0; i < ring->dma_size; i++) in mtk_tx_clean()
2570 mtk_tx_unmap(eth, &ring->buf[i], NULL, false); in mtk_tx_clean()
2571 kfree(ring->buf); in mtk_tx_clean()
2572 ring->buf = NULL; in mtk_tx_clean()
2574 if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && ring->dma) { in mtk_tx_clean()
2575 dma_free_coherent(eth->dma_dev, in mtk_tx_clean()
2576 ring->dma_size * soc->txrx.txd_size, in mtk_tx_clean()
2577 ring->dma, ring->phys); in mtk_tx_clean()
2578 ring->dma = NULL; in mtk_tx_clean()
2581 if (ring->dma_pdma) { in mtk_tx_clean()
2582 dma_free_coherent(eth->dma_dev, in mtk_tx_clean()
2583 ring->dma_size * soc->txrx.txd_size, in mtk_tx_clean()
2584 ring->dma_pdma, ring->phys_pdma); in mtk_tx_clean()
2585 ring->dma_pdma = NULL; in mtk_tx_clean()
2591 const struct mtk_reg_map *reg_map = eth->soc->reg_map; in mtk_rx_alloc()
2596 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) in mtk_rx_alloc()
2603 return -EINVAL; in mtk_rx_alloc()
2604 ring = ð->rx_ring_qdma; in mtk_rx_alloc()
2606 ring = ð->rx_ring[ring_no]; in mtk_rx_alloc()
2617 ring->frag_size = mtk_max_frag_size(rx_data_len); in mtk_rx_alloc()
2618 ring->buf_size = mtk_max_buf_size(ring->frag_size); in mtk_rx_alloc()
2619 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), in mtk_rx_alloc()
2621 if (!ring->data) in mtk_rx_alloc()
2622 return -ENOMEM; in mtk_rx_alloc()
2627 pp = mtk_create_page_pool(eth, &ring->xdp_q, ring_no, in mtk_rx_alloc()
2632 ring->page_pool = pp; in mtk_rx_alloc()
2635 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM) || in mtk_rx_alloc()
2637 ring->dma = dma_alloc_coherent(eth->dma_dev, in mtk_rx_alloc()
2638 rx_dma_size * eth->soc->txrx.rxd_size, in mtk_rx_alloc()
2639 &ring->phys, GFP_KERNEL); in mtk_rx_alloc()
2641 struct mtk_tx_ring *tx_ring = ð->tx_ring; in mtk_rx_alloc()
2643 ring->dma = tx_ring->dma + tx_ring_size * in mtk_rx_alloc()
2644 eth->soc->txrx.txd_size * (ring_no + 1); in mtk_rx_alloc()
2645 ring->phys = tx_ring->phys + tx_ring_size * in mtk_rx_alloc()
2646 eth->soc->txrx.txd_size * (ring_no + 1); in mtk_rx_alloc()
2649 if (!ring->dma) in mtk_rx_alloc()
2650 return -ENOMEM; in mtk_rx_alloc()
2657 rxd = ring->dma + i * eth->soc->txrx.rxd_size; in mtk_rx_alloc()
2658 if (ring->page_pool) { in mtk_rx_alloc()
2659 data = mtk_page_pool_get_buff(ring->page_pool, in mtk_rx_alloc()
2662 return -ENOMEM; in mtk_rx_alloc()
2664 if (ring->frag_size <= PAGE_SIZE) in mtk_rx_alloc()
2665 data = netdev_alloc_frag(ring->frag_size); in mtk_rx_alloc()
2670 return -ENOMEM; in mtk_rx_alloc()
2672 dma_addr = dma_map_single(eth->dma_dev, in mtk_rx_alloc()
2673 data + NET_SKB_PAD + eth->ip_align, in mtk_rx_alloc()
2674 ring->buf_size, DMA_FROM_DEVICE); in mtk_rx_alloc()
2675 if (unlikely(dma_mapping_error(eth->dma_dev, in mtk_rx_alloc()
2678 return -ENOMEM; in mtk_rx_alloc()
2681 rxd->rxd1 = (unsigned int)dma_addr; in mtk_rx_alloc()
2682 ring->data[i] = data; in mtk_rx_alloc()
2684 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) in mtk_rx_alloc()
2685 rxd->rxd2 = RX_DMA_LSO; in mtk_rx_alloc()
2687 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); in mtk_rx_alloc()
2689 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) in mtk_rx_alloc()
2690 rxd->rxd2 |= RX_DMA_PREP_ADDR64(dma_addr); in mtk_rx_alloc()
2692 rxd->rxd3 = 0; in mtk_rx_alloc()
2693 rxd->rxd4 = 0; in mtk_rx_alloc()
2695 rxd->rxd5 = 0; in mtk_rx_alloc()
2696 rxd->rxd6 = 0; in mtk_rx_alloc()
2697 rxd->rxd7 = 0; in mtk_rx_alloc()
2698 rxd->rxd8 = 0; in mtk_rx_alloc()
2702 ring->dma_size = rx_dma_size; in mtk_rx_alloc()
2703 ring->calc_idx_update = false; in mtk_rx_alloc()
2704 ring->calc_idx = rx_dma_size - 1; in mtk_rx_alloc()
2706 ring->crx_idx_reg = reg_map->qdma.qcrx_ptr + in mtk_rx_alloc()
2709 ring->crx_idx_reg = reg_map->pdma.pcrx_ptr + in mtk_rx_alloc()
2717 mtk_w32(eth, ring->phys, in mtk_rx_alloc()
2718 reg_map->qdma.rx_ptr + ring_no * MTK_QRX_OFFSET); in mtk_rx_alloc()
2720 reg_map->qdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); in mtk_rx_alloc()
2722 reg_map->qdma.rst_idx); in mtk_rx_alloc()
2724 mtk_w32(eth, ring->phys, in mtk_rx_alloc()
2725 reg_map->pdma.rx_ptr + ring_no * MTK_QRX_OFFSET); in mtk_rx_alloc()
2727 reg_map->pdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); in mtk_rx_alloc()
2729 reg_map->pdma.rst_idx); in mtk_rx_alloc()
2731 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); in mtk_rx_alloc()
2741 if (ring->data && ring->dma) { in mtk_rx_clean()
2742 for (i = 0; i < ring->dma_size; i++) { in mtk_rx_clean()
2745 if (!ring->data[i]) in mtk_rx_clean()
2748 rxd = ring->dma + i * eth->soc->txrx.rxd_size; in mtk_rx_clean()
2749 if (!rxd->rxd1) in mtk_rx_clean()
2752 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) in mtk_rx_clean()
2753 addr64 = RX_DMA_GET_ADDR64(rxd->rxd2); in mtk_rx_clean()
2755 dma_unmap_single(eth->dma_dev, ((u64)rxd->rxd1 | addr64), in mtk_rx_clean()
2756 ring->buf_size, DMA_FROM_DEVICE); in mtk_rx_clean()
2757 mtk_rx_put_buff(ring, ring->data[i], false); in mtk_rx_clean()
2759 kfree(ring->data); in mtk_rx_clean()
2760 ring->data = NULL; in mtk_rx_clean()
2763 if (!in_sram && ring->dma) { in mtk_rx_clean()
2764 dma_free_coherent(eth->dma_dev, in mtk_rx_clean()
2765 ring->dma_size * eth->soc->txrx.rxd_size, in mtk_rx_clean()
2766 ring->dma, ring->phys); in mtk_rx_clean()
2767 ring->dma = NULL; in mtk_rx_clean()
2770 if (ring->page_pool) { in mtk_rx_clean()
2771 if (xdp_rxq_info_is_reg(&ring->xdp_q)) in mtk_rx_clean()
2772 xdp_rxq_info_unreg(&ring->xdp_q); in mtk_rx_clean()
2773 page_pool_destroy(ring->page_pool); in mtk_rx_clean()
2774 ring->page_pool = NULL; in mtk_rx_clean()
2784 /* set LRO rings to auto-learn modes */ in mtk_hwlro_rx_init()
2816 /* auto-learn score delta setting */ in mtk_hwlro_rx_init()
2897 if (mac->hwlro_ip[i]) in mtk_hwlro_get_ip_cnt()
2908 (struct ethtool_rx_flow_spec *)&cmd->fs; in mtk_hwlro_add_ipaddr()
2910 struct mtk_eth *eth = mac->hw; in mtk_hwlro_add_ipaddr()
2913 if ((fsp->flow_type != TCP_V4_FLOW) || in mtk_hwlro_add_ipaddr()
2914 (!fsp->h_u.tcp_ip4_spec.ip4dst) || in mtk_hwlro_add_ipaddr()
2915 (fsp->location > 1)) in mtk_hwlro_add_ipaddr()
2916 return -EINVAL; in mtk_hwlro_add_ipaddr()
2918 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); in mtk_hwlro_add_ipaddr()
2919 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; in mtk_hwlro_add_ipaddr()
2921 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); in mtk_hwlro_add_ipaddr()
2923 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); in mtk_hwlro_add_ipaddr()
2932 (struct ethtool_rx_flow_spec *)&cmd->fs; in mtk_hwlro_del_ipaddr()
2934 struct mtk_eth *eth = mac->hw; in mtk_hwlro_del_ipaddr()
2937 if (fsp->location > 1) in mtk_hwlro_del_ipaddr()
2938 return -EINVAL; in mtk_hwlro_del_ipaddr()
2940 mac->hwlro_ip[fsp->location] = 0; in mtk_hwlro_del_ipaddr()
2941 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; in mtk_hwlro_del_ipaddr()
2943 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); in mtk_hwlro_del_ipaddr()
2953 struct mtk_eth *eth = mac->hw; in mtk_hwlro_netdev_disable()
2957 mac->hwlro_ip[i] = 0; in mtk_hwlro_netdev_disable()
2958 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; in mtk_hwlro_netdev_disable()
2963 mac->hwlro_ip_cnt = 0; in mtk_hwlro_netdev_disable()
2971 (struct ethtool_rx_flow_spec *)&cmd->fs; in mtk_hwlro_get_fdir_entry()
2973 if (fsp->location >= ARRAY_SIZE(mac->hwlro_ip)) in mtk_hwlro_get_fdir_entry()
2974 return -EINVAL; in mtk_hwlro_get_fdir_entry()
2977 fsp->flow_type = TCP_V4_FLOW; in mtk_hwlro_get_fdir_entry()
2978 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); in mtk_hwlro_get_fdir_entry()
2979 fsp->m_u.tcp_ip4_spec.ip4dst = 0; in mtk_hwlro_get_fdir_entry()
2981 fsp->h_u.tcp_ip4_spec.ip4src = 0; in mtk_hwlro_get_fdir_entry()
2982 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; in mtk_hwlro_get_fdir_entry()
2983 fsp->h_u.tcp_ip4_spec.psrc = 0; in mtk_hwlro_get_fdir_entry()
2984 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; in mtk_hwlro_get_fdir_entry()
2985 fsp->h_u.tcp_ip4_spec.pdst = 0; in mtk_hwlro_get_fdir_entry()
2986 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; in mtk_hwlro_get_fdir_entry()
2987 fsp->h_u.tcp_ip4_spec.tos = 0; in mtk_hwlro_get_fdir_entry()
2988 fsp->m_u.tcp_ip4_spec.tos = 0xff; in mtk_hwlro_get_fdir_entry()
3002 if (cnt == cmd->rule_cnt) in mtk_hwlro_get_fdir_all()
3003 return -EMSGSIZE; in mtk_hwlro_get_fdir_all()
3005 if (mac->hwlro_ip[i]) { in mtk_hwlro_get_fdir_all()
3011 cmd->rule_cnt = cnt; in mtk_hwlro_get_fdir_all()
3035 netdev_features_t diff = dev->features ^ features; in mtk_set_features()
3050 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) in mtk_dma_busy_wait()
3051 reg = eth->soc->reg_map->qdma.glo_cfg; in mtk_dma_busy_wait()
3053 reg = eth->soc->reg_map->pdma.glo_cfg; in mtk_dma_busy_wait()
3055 ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val, in mtk_dma_busy_wait()
3059 dev_err(eth->dev, "DMA init timeout\n"); in mtk_dma_busy_wait()
3070 return -EBUSY; in mtk_dma_init()
3072 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { in mtk_dma_init()
3085 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { in mtk_dma_init()
3095 if (eth->hwlro) { in mtk_dma_init()
3106 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { in mtk_dma_init()
3111 FC_THRES_MIN, eth->soc->reg_map->qdma.fc_th); in mtk_dma_init()
3112 mtk_w32(eth, 0x0, eth->soc->reg_map->qdma.hred); in mtk_dma_init()
3120 const struct mtk_soc_data *soc = eth->soc; in mtk_dma_free()
3124 if (eth->netdev[i]) in mtk_dma_free()
3125 netdev_reset_queue(eth->netdev[i]); in mtk_dma_free()
3126 if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) { in mtk_dma_free()
3127 dma_free_coherent(eth->dma_dev, in mtk_dma_free()
3128 MTK_QDMA_RING_SIZE * soc->txrx.txd_size, in mtk_dma_free()
3129 eth->scratch_ring, eth->phy_scratch_ring); in mtk_dma_free()
3130 eth->scratch_ring = NULL; in mtk_dma_free()
3131 eth->phy_scratch_ring = 0; in mtk_dma_free()
3134 mtk_rx_clean(eth, ð->rx_ring[0], MTK_HAS_CAPS(soc->caps, MTK_SRAM)); in mtk_dma_free()
3135 mtk_rx_clean(eth, ð->rx_ring_qdma, false); in mtk_dma_free()
3137 if (eth->hwlro) { in mtk_dma_free()
3140 mtk_rx_clean(eth, ð->rx_ring[i], false); in mtk_dma_free()
3143 kfree(eth->scratch_head); in mtk_dma_free()
3158 struct mtk_eth *eth = mac->hw; in mtk_tx_timeout()
3160 if (test_bit(MTK_RESETTING, ð->state)) in mtk_tx_timeout()
3166 eth->netdev[mac->id]->stats.tx_errors++; in mtk_tx_timeout()
3169 schedule_work(ð->pending_work); in mtk_tx_timeout()
3176 eth->rx_events++; in mtk_handle_irq_rx()
3177 if (likely(napi_schedule_prep(ð->rx_napi))) { in mtk_handle_irq_rx()
3178 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); in mtk_handle_irq_rx()
3179 __napi_schedule(ð->rx_napi); in mtk_handle_irq_rx()
3189 eth->tx_events++; in mtk_handle_irq_tx()
3190 if (likely(napi_schedule_prep(ð->tx_napi))) { in mtk_handle_irq_tx()
3192 __napi_schedule(ð->tx_napi); in mtk_handle_irq_tx()
3201 const struct mtk_reg_map *reg_map = eth->soc->reg_map; in mtk_handle_irq()
3203 if (mtk_r32(eth, reg_map->pdma.irq_mask) & in mtk_handle_irq()
3204 eth->soc->txrx.rx_irq_done_mask) { in mtk_handle_irq()
3205 if (mtk_r32(eth, reg_map->pdma.irq_status) & in mtk_handle_irq()
3206 eth->soc->txrx.rx_irq_done_mask) in mtk_handle_irq()
3209 if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) { in mtk_handle_irq()
3210 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) in mtk_handle_irq()
3221 struct mtk_eth *eth = mac->hw; in mtk_poll_controller()
3224 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); in mtk_poll_controller()
3225 mtk_handle_irq_rx(eth->irq[2], dev); in mtk_poll_controller()
3227 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); in mtk_poll_controller()
3234 const struct mtk_reg_map *reg_map = eth->soc->reg_map; in mtk_start_dma()
3243 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { in mtk_start_dma()
3244 val = mtk_r32(eth, reg_map->qdma.glo_cfg); in mtk_start_dma()
3255 mtk_w32(eth, val, reg_map->qdma.glo_cfg); in mtk_start_dma()
3260 reg_map->pdma.glo_cfg); in mtk_start_dma()
3264 reg_map->pdma.glo_cfg); in mtk_start_dma()
3274 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) in mtk_gdm_config()
3280 if (!eth->netdev[i]) in mtk_gdm_config()
3293 if (netdev_uses_dsa(eth->netdev[i])) in mtk_gdm_config()
3298 /* Reset and enable PSE */ in mtk_gdm_config()
3308 dev->dsa_ptr->tag_ops->proto == DSA_TAG_PROTO_MTK; in mtk_uses_dsa()
3317 struct mtk_eth *eth = mac->hw; in mtk_device_event()
3341 if (s.base.speed == 0 || s.base.speed == ((__u32)-1)) in mtk_device_event()
3345 if (dp->index >= MTK_QDMA_NUM_QUEUES) in mtk_device_event()
3348 if (mac->speed > 0 && mac->speed <= s.base.speed) in mtk_device_event()
3351 mtk_set_queue_speed(eth, dp->index + 3, s.base.speed); in mtk_device_event()
3359 struct mtk_eth *eth = mac->hw; in mtk_open()
3362 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0); in mtk_open()
3370 if (!refcount_read(ð->dma_refcnt)) { in mtk_open()
3371 const struct mtk_soc_data *soc = eth->soc; in mtk_open()
3377 phylink_disconnect_phy(mac->phylink); in mtk_open()
3381 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) in mtk_open()
3382 mtk_ppe_start(eth->ppe[i]); in mtk_open()
3384 gdm_config = soc->offload_version ? soc->reg_map->gdma_to_ppe in mtk_open()
3388 napi_enable(ð->tx_napi); in mtk_open()
3389 napi_enable(ð->rx_napi); in mtk_open()
3391 mtk_rx_irq_enable(eth, soc->txrx.rx_irq_done_mask); in mtk_open()
3392 refcount_set(ð->dma_refcnt, 1); in mtk_open()
3395 refcount_inc(ð->dma_refcnt); in mtk_open()
3397 phylink_start(mac->phylink); in mtk_open()
3403 if (mtk_uses_dsa(dev) && !eth->prog) { in mtk_open()
3404 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { in mtk_open()
3405 struct metadata_dst *md_dst = eth->dsa_meta[i]; in mtk_open()
3413 return -ENOMEM; in mtk_open()
3415 md_dst->u.port_info.port_id = i; in mtk_open()
3416 eth->dsa_meta[i] = md_dst; in mtk_open()
3439 spin_lock_bh(ð->page_lock); in mtk_stop_dma()
3443 spin_unlock_bh(ð->page_lock); in mtk_stop_dma()
3459 struct mtk_eth *eth = mac->hw; in mtk_stop()
3462 phylink_stop(mac->phylink); in mtk_stop()
3466 phylink_disconnect_phy(mac->phylink); in mtk_stop()
3469 if (!refcount_dec_and_test(ð->dma_refcnt)) in mtk_stop()
3475 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); in mtk_stop()
3476 napi_disable(ð->tx_napi); in mtk_stop()
3477 napi_disable(ð->rx_napi); in mtk_stop()
3479 cancel_work_sync(ð->rx_dim.work); in mtk_stop()
3480 cancel_work_sync(ð->tx_dim.work); in mtk_stop()
3482 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) in mtk_stop()
3483 mtk_stop_dma(eth, eth->soc->reg_map->qdma.glo_cfg); in mtk_stop()
3484 mtk_stop_dma(eth, eth->soc->reg_map->pdma.glo_cfg); in mtk_stop()
3488 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) in mtk_stop()
3489 mtk_ppe_stop(eth->ppe[i]); in mtk_stop()
3498 struct mtk_eth *eth = mac->hw; in mtk_xdp_setup()
3502 if (eth->hwlro) { in mtk_xdp_setup()
3504 return -EOPNOTSUPP; in mtk_xdp_setup()
3507 if (dev->mtu > MTK_PP_MAX_BUF_SIZE) { in mtk_xdp_setup()
3509 return -EOPNOTSUPP; in mtk_xdp_setup()
3512 need_update = !!eth->prog != !!prog; in mtk_xdp_setup()
3516 old_prog = rcu_replace_pointer(eth->prog, prog, lockdep_rtnl_is_held()); in mtk_xdp_setup()
3528 switch (xdp->command) { in mtk_xdp()
3530 return mtk_xdp_setup(dev, xdp->prog, xdp->extack); in mtk_xdp()
3532 return -EINVAL; in mtk_xdp()
3538 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, in ethsys_reset()
3543 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, in ethsys_reset()
3553 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) in mtk_clk_disable()
3554 clk_disable_unprepare(eth->clks[clk]); in mtk_clk_disable()
3562 ret = clk_prepare_enable(eth->clks[clk]); in mtk_clk_enable()
3570 while (--clk >= 0) in mtk_clk_enable()
3571 clk_disable_unprepare(eth->clks[clk]); in mtk_clk_enable()
3580 const struct mtk_reg_map *reg_map = eth->soc->reg_map; in mtk_dim_rx()
3584 cur_profile = net_dim_get_rx_moderation(eth->rx_dim.mode, in mtk_dim_rx()
3585 dim->profile_ix); in mtk_dim_rx()
3586 spin_lock_bh(ð->dim_lock); in mtk_dim_rx()
3588 val = mtk_r32(eth, reg_map->pdma.delay_irq); in mtk_dim_rx()
3598 mtk_w32(eth, val, reg_map->pdma.delay_irq); in mtk_dim_rx()
3599 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) in mtk_dim_rx()
3600 mtk_w32(eth, val, reg_map->qdma.delay_irq); in mtk_dim_rx()
3602 spin_unlock_bh(ð->dim_lock); in mtk_dim_rx()
3604 dim->state = DIM_START_MEASURE; in mtk_dim_rx()
3611 const struct mtk_reg_map *reg_map = eth->soc->reg_map; in mtk_dim_tx()
3615 cur_profile = net_dim_get_tx_moderation(eth->tx_dim.mode, in mtk_dim_tx()
3616 dim->profile_ix); in mtk_dim_tx()
3617 spin_lock_bh(ð->dim_lock); in mtk_dim_tx()
3619 val = mtk_r32(eth, reg_map->pdma.delay_irq); in mtk_dim_tx()
3629 mtk_w32(eth, val, reg_map->pdma.delay_irq); in mtk_dim_tx()
3630 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) in mtk_dim_tx()
3631 mtk_w32(eth, val, reg_map->qdma.delay_irq); in mtk_dim_tx()
3633 spin_unlock_bh(ð->dim_lock); in mtk_dim_tx()
3635 dim->state = DIM_START_MEASURE; in mtk_dim_tx()
3640 struct mtk_eth *eth = mac->hw; in mtk_set_mcr_max_rx()
3643 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) in mtk_set_mcr_max_rx()
3646 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); in mtk_set_mcr_max_rx()
3659 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); in mtk_set_mcr_max_rx()
3667 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); in mtk_hw_reset()
3672 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) in mtk_hw_reset()
3675 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) in mtk_hw_reset()
3682 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) in mtk_hw_reset()
3691 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, in mtk_hw_reset()
3694 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, in mtk_hw_reset()
3702 regmap_read(eth->ethsys, ETHSYS_RSTCTRL, &val); in mtk_hw_reset_read()
3710 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, RSTCTRL_FE, in mtk_hw_warm_reset()
3714 dev_err(eth->dev, "warm reset failed\n"); in mtk_hw_warm_reset()
3721 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) in mtk_hw_warm_reset()
3723 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) in mtk_hw_warm_reset()
3729 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) in mtk_hw_warm_reset()
3735 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, rst_mask); in mtk_hw_warm_reset()
3740 dev_err(eth->dev, "warm reset stage0 failed %08x (%08x)\n", in mtk_hw_warm_reset()
3744 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, ~rst_mask); in mtk_hw_warm_reset()
3749 dev_err(eth->dev, "warm reset stage1 failed %08x (%08x)\n", in mtk_hw_warm_reset()
3755 const struct mtk_reg_map *reg_map = eth->soc->reg_map; in mtk_hw_check_dma_hang()
3763 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) in mtk_hw_check_dma_hang()
3767 wdidx = mtk_r32(eth, reg_map->wdma_base[0] + 0xc); in mtk_hw_check_dma_hang()
3769 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x204); in mtk_hw_check_dma_hang()
3772 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x230); in mtk_hw_check_dma_hang()
3775 oq_free = (!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(24, 16)) && in mtk_hw_check_dma_hang()
3776 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x4) & GENMASK(8, 0)) && in mtk_hw_check_dma_hang()
3777 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x10) & GENMASK(24, 16))); in mtk_hw_check_dma_hang()
3779 if (wdidx == eth->reset.wdidx && wtx_busy && cdm_full && oq_free) { in mtk_hw_check_dma_hang()
3780 if (++eth->reset.wdma_hang_count > 2) { in mtk_hw_check_dma_hang()
3781 eth->reset.wdma_hang_count = 0; in mtk_hw_check_dma_hang()
3788 qfsm_hang = !!mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x234); in mtk_hw_check_dma_hang()
3789 qfwd_hang = !mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x308); in mtk_hw_check_dma_hang()
3795 gdm1_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x24); in mtk_hw_check_dma_hang()
3796 gdm2_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x64); in mtk_hw_check_dma_hang()
3801 if (++eth->reset.qdma_hang_count > 2) { in mtk_hw_check_dma_hang()
3802 eth->reset.qdma_hang_count = 0; in mtk_hw_check_dma_hang()
3809 oq_hang = !!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(8, 0)); in mtk_hw_check_dma_hang()
3811 adma_busy = !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & GENMASK(4, 0)) && in mtk_hw_check_dma_hang()
3812 !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & BIT(6)); in mtk_hw_check_dma_hang()
3815 if (++eth->reset.adma_hang_count > 2) { in mtk_hw_check_dma_hang()
3816 eth->reset.adma_hang_count = 0; in mtk_hw_check_dma_hang()
3822 eth->reset.wdma_hang_count = 0; in mtk_hw_check_dma_hang()
3823 eth->reset.qdma_hang_count = 0; in mtk_hw_check_dma_hang()
3824 eth->reset.adma_hang_count = 0; in mtk_hw_check_dma_hang()
3826 eth->reset.wdidx = wdidx; in mtk_hw_check_dma_hang()
3837 if (test_bit(MTK_RESETTING, ð->state)) in mtk_hw_reset_monitor_work()
3842 schedule_work(ð->pending_work); in mtk_hw_reset_monitor_work()
3845 schedule_delayed_work(ð->reset.monitor_work, in mtk_hw_reset_monitor_work()
3853 const struct mtk_reg_map *reg_map = eth->soc->reg_map; in mtk_hw_init()
3856 if (!reset && test_and_set_bit(MTK_HW_INIT, ð->state)) in mtk_hw_init()
3860 pm_runtime_enable(eth->dev); in mtk_hw_init()
3861 pm_runtime_get_sync(eth->dev); in mtk_hw_init()
3868 if (eth->ethsys) in mtk_hw_init()
3869 regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask, in mtk_hw_init()
3870 of_dma_is_coherent(eth->dma_dev->of_node) * dma_mask); in mtk_hw_init()
3872 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { in mtk_hw_init()
3873 ret = device_reset(eth->dev); in mtk_hw_init()
3875 dev_err(eth->dev, "MAC reset failed!\n"); in mtk_hw_init()
3880 mtk_dim_rx(ð->rx_dim.work); in mtk_hw_init()
3881 mtk_dim_tx(ð->tx_dim.work); in mtk_hw_init()
3903 if (eth->pctl) { in mtk_hw_init()
3905 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); in mtk_hw_init()
3908 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); in mtk_hw_init()
3911 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); in mtk_hw_init()
3919 struct net_device *dev = eth->netdev[i]; in mtk_hw_init()
3926 dev->mtu + MTK_RX_ETH_HLEN); in mtk_hw_init()
3942 mtk_dim_rx(ð->rx_dim.work); in mtk_hw_init()
3943 mtk_dim_tx(ð->tx_dim.work); in mtk_hw_init()
3950 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp); in mtk_hw_init()
3951 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->pdma.int_grp + 4); in mtk_hw_init()
3952 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp); in mtk_hw_init()
3953 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4); in mtk_hw_init()
3957 /* PSE should not drop port1, port8 and port9 packets */ in mtk_hw_init()
3967 /* PSE GDM3 MIB counter has incorrect hw default values, in mtk_hw_init()
3972 mtk_r32(eth, reg_map->gdm1_cnt + 0x100 + i); in mtk_hw_init()
3974 /* PSE should not drop port8 and port9 packets from WDMA Tx */ in mtk_hw_init()
3977 /* PSE should drop packets to port 8/9 on WDMA Rx ring full */ in mtk_hw_init()
3980 /* PSE Free Queue Flow Control */ in mtk_hw_init()
3983 /* PSE config input queue threshold */ in mtk_hw_init()
3993 /* PSE config output queue threshold */ in mtk_hw_init()
4016 pm_runtime_put_sync(eth->dev); in mtk_hw_init()
4017 pm_runtime_disable(eth->dev); in mtk_hw_init()
4025 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) in mtk_hw_deinit()
4030 pm_runtime_put_sync(eth->dev); in mtk_hw_deinit()
4031 pm_runtime_disable(eth->dev); in mtk_hw_deinit()
4039 struct mtk_eth *eth = mac->hw; in mtk_uninit()
4041 phylink_disconnect_phy(mac->phylink); in mtk_uninit()
4050 struct mtk_eth *eth = mac->hw; in mtk_change_mtu()
4052 if (rcu_access_pointer(eth->prog) && in mtk_change_mtu()
4055 return -EINVAL; in mtk_change_mtu()
4059 dev->mtu = new_mtu; in mtk_change_mtu()
4072 return phylink_mii_ioctl(mac->phylink, ifr, cmd); in mtk_do_ioctl()
4077 return -EOPNOTSUPP; in mtk_do_ioctl()
4090 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) in mtk_prepare_for_reset()
4092 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) in mtk_prepare_for_reset()
4098 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) in mtk_prepare_for_reset()
4099 mtk_ppe_prepare_reset(eth->ppe[i]); in mtk_prepare_for_reset()
4119 set_bit(MTK_RESETTING, ð->state); in mtk_pending_work()
4130 if (!eth->netdev[i] || !netif_running(eth->netdev[i])) in mtk_pending_work()
4133 mtk_stop(eth->netdev[i]); in mtk_pending_work()
4139 if (eth->dev->pins) in mtk_pending_work()
4140 pinctrl_select_state(eth->dev->pins->p, in mtk_pending_work()
4141 eth->dev->pins->default_state); in mtk_pending_work()
4146 if (!eth->netdev[i] || !test_bit(i, &restart)) in mtk_pending_work()
4149 if (mtk_open(eth->netdev[i])) { in mtk_pending_work()
4150 netif_alert(eth, ifup, eth->netdev[i], in mtk_pending_work()
4152 dev_close(eth->netdev[i]); in mtk_pending_work()
4161 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) in mtk_pending_work()
4163 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) in mtk_pending_work()
4169 clear_bit(MTK_RESETTING, ð->state); in mtk_pending_work()
4181 if (!eth->netdev[i]) in mtk_free_dev()
4183 free_netdev(eth->netdev[i]); in mtk_free_dev()
4186 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { in mtk_free_dev()
4187 if (!eth->dsa_meta[i]) in mtk_free_dev()
4189 metadata_dst_free(eth->dsa_meta[i]); in mtk_free_dev()
4201 if (!eth->netdev[i]) in mtk_unreg_dev()
4203 mac = netdev_priv(eth->netdev[i]); in mtk_unreg_dev()
4204 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) in mtk_unreg_dev()
4205 unregister_netdevice_notifier(&mac->device_notifier); in mtk_unreg_dev()
4206 unregister_netdev(eth->netdev[i]); in mtk_unreg_dev()
4217 mtk_pcs_lynxi_destroy(eth->sgmii_pcs[i]); in mtk_sgmii_destroy()
4225 cancel_work_sync(ð->pending_work); in mtk_cleanup()
4226 cancel_delayed_work_sync(ð->reset.monitor_work); in mtk_cleanup()
4236 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) in mtk_get_link_ksettings()
4237 return -EBUSY; in mtk_get_link_ksettings()
4239 return phylink_ethtool_ksettings_get(mac->phylink, cmd); in mtk_get_link_ksettings()
4247 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) in mtk_set_link_ksettings()
4248 return -EBUSY; in mtk_set_link_ksettings()
4250 return phylink_ethtool_ksettings_set(mac->phylink, cmd); in mtk_set_link_ksettings()
4258 strscpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); in mtk_get_drvinfo()
4259 strscpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); in mtk_get_drvinfo()
4260 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); in mtk_get_drvinfo()
4267 return mac->hw->msg_enable; in mtk_get_msglevel()
4274 mac->hw->msg_enable = value; in mtk_set_msglevel()
4281 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) in mtk_nway_reset()
4282 return -EBUSY; in mtk_nway_reset()
4284 if (!mac->phylink) in mtk_nway_reset()
4285 return -ENOTSUPP; in mtk_nway_reset()
4287 return phylink_ethtool_nway_reset(mac->phylink); in mtk_nway_reset()
4302 if (mtk_page_pool_enabled(mac->hw)) in mtk_get_strings()
4318 if (mtk_page_pool_enabled(mac->hw)) in mtk_get_sset_count()
4323 return -EOPNOTSUPP; in mtk_get_sset_count()
4332 for (i = 0; i < ARRAY_SIZE(eth->rx_ring); i++) { in mtk_ethtool_pp_stats()
4333 struct mtk_rx_ring *ring = ð->rx_ring[i]; in mtk_ethtool_pp_stats()
4335 if (!ring->page_pool) in mtk_ethtool_pp_stats()
4338 page_pool_get_stats(ring->page_pool, &stats); in mtk_ethtool_pp_stats()
4347 struct mtk_hw_stats *hwstats = mac->hw_stats; in mtk_get_ethtool_stats()
4352 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) in mtk_get_ethtool_stats()
4356 if (spin_trylock_bh(&hwstats->stats_lock)) { in mtk_get_ethtool_stats()
4358 spin_unlock_bh(&hwstats->stats_lock); in mtk_get_ethtool_stats()
4366 start = u64_stats_fetch_begin(&hwstats->syncp); in mtk_get_ethtool_stats()
4370 if (mtk_page_pool_enabled(mac->hw)) in mtk_get_ethtool_stats()
4371 mtk_ethtool_pp_stats(mac->hw, data_dst); in mtk_get_ethtool_stats()
4372 } while (u64_stats_fetch_retry(&hwstats->syncp, start)); in mtk_get_ethtool_stats()
4378 int ret = -EOPNOTSUPP; in mtk_get_rxnfc()
4380 switch (cmd->cmd) { in mtk_get_rxnfc()
4382 if (dev->hw_features & NETIF_F_LRO) { in mtk_get_rxnfc()
4383 cmd->data = MTK_MAX_RX_RING_NUM; in mtk_get_rxnfc()
4388 if (dev->hw_features & NETIF_F_LRO) { in mtk_get_rxnfc()
4391 cmd->rule_cnt = mac->hwlro_ip_cnt; in mtk_get_rxnfc()
4396 if (dev->hw_features & NETIF_F_LRO) in mtk_get_rxnfc()
4400 if (dev->hw_features & NETIF_F_LRO) in mtk_get_rxnfc()
4413 int ret = -EOPNOTSUPP; in mtk_set_rxnfc()
4415 switch (cmd->cmd) { in mtk_set_rxnfc()
4417 if (dev->hw_features & NETIF_F_LRO) in mtk_set_rxnfc()
4421 if (dev->hw_features & NETIF_F_LRO) in mtk_set_rxnfc()
4440 queue = mac->id; in mtk_select_queue()
4442 if (queue >= dev->num_tx_queues) in mtk_select_queue()
4496 dev_err(eth->dev, "missing mac id\n"); in mtk_add_mac()
4497 return -EINVAL; in mtk_add_mac()
4502 dev_err(eth->dev, "%d is not a valid mac id\n", id); in mtk_add_mac()
4503 return -EINVAL; in mtk_add_mac()
4506 if (eth->netdev[id]) { in mtk_add_mac()
4507 dev_err(eth->dev, "duplicate mac id found: %d\n", id); in mtk_add_mac()
4508 return -EINVAL; in mtk_add_mac()
4511 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) in mtk_add_mac()
4514 eth->netdev[id] = alloc_etherdev_mqs(sizeof(*mac), txqs, 1); in mtk_add_mac()
4515 if (!eth->netdev[id]) { in mtk_add_mac()
4516 dev_err(eth->dev, "alloc_etherdev failed\n"); in mtk_add_mac()
4517 return -ENOMEM; in mtk_add_mac()
4519 mac = netdev_priv(eth->netdev[id]); in mtk_add_mac()
4520 eth->mac[id] = mac; in mtk_add_mac()
4521 mac->id = id; in mtk_add_mac()
4522 mac->hw = eth; in mtk_add_mac()
4523 mac->of_node = np; in mtk_add_mac()
4525 err = of_get_ethdev_address(mac->of_node, eth->netdev[id]); in mtk_add_mac()
4526 if (err == -EPROBE_DEFER) in mtk_add_mac()
4531 eth_hw_addr_random(eth->netdev[id]); in mtk_add_mac()
4532 dev_err(eth->dev, "generated random MAC address %pM\n", in mtk_add_mac()
4533 eth->netdev[id]->dev_addr); in mtk_add_mac()
4536 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); in mtk_add_mac()
4537 mac->hwlro_ip_cnt = 0; in mtk_add_mac()
4539 mac->hw_stats = devm_kzalloc(eth->dev, in mtk_add_mac()
4540 sizeof(*mac->hw_stats), in mtk_add_mac()
4542 if (!mac->hw_stats) { in mtk_add_mac()
4543 dev_err(eth->dev, "failed to allocate counter memory\n"); in mtk_add_mac()
4544 err = -ENOMEM; in mtk_add_mac()
4547 spin_lock_init(&mac->hw_stats->stats_lock); in mtk_add_mac()
4548 u64_stats_init(&mac->hw_stats->syncp); in mtk_add_mac()
4551 mac->hw_stats->reg_offset = id * 0x80; in mtk_add_mac()
4553 mac->hw_stats->reg_offset = id * 0x40; in mtk_add_mac()
4558 dev_err(eth->dev, "incorrect phy-mode\n"); in mtk_add_mac()
4563 mac->interface = PHY_INTERFACE_MODE_NA; in mtk_add_mac()
4564 mac->speed = SPEED_UNKNOWN; in mtk_add_mac()
4566 mac->phylink_config.dev = ð->netdev[id]->dev; in mtk_add_mac()
4567 mac->phylink_config.type = PHYLINK_NETDEV; in mtk_add_mac()
4568 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | in mtk_add_mac()
4571 /* MT7623 gmac0 is now missing its speed-specific PLL configuration in mtk_add_mac()
4572 * in its .mac_config method (since state->speed is not valid there. in mtk_add_mac()
4575 if (!mac->hw->soc->disable_pll_modes || mac->id != 0) { in mtk_add_mac()
4577 mac->phylink_config.supported_interfaces); in mtk_add_mac()
4579 mac->phylink_config.supported_interfaces); in mtk_add_mac()
4581 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) in mtk_add_mac()
4582 phy_interface_set_rgmii(mac->phylink_config.supported_interfaces); in mtk_add_mac()
4585 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id) in mtk_add_mac()
4587 mac->phylink_config.supported_interfaces); in mtk_add_mac()
4590 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) && in mtk_add_mac()
4591 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII_MT7621_CLK)) { in mtk_add_mac()
4592 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val); in mtk_add_mac()
4595 mac->phylink_config.supported_interfaces); in mtk_add_mac()
4598 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) { in mtk_add_mac()
4600 mac->phylink_config.supported_interfaces); in mtk_add_mac()
4602 mac->phylink_config.supported_interfaces); in mtk_add_mac()
4604 mac->phylink_config.supported_interfaces); in mtk_add_mac()
4607 if (mtk_is_netsys_v3_or_greater(mac->hw) && in mtk_add_mac()
4608 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_ESW_BIT) && in mtk_add_mac()
4610 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | in mtk_add_mac()
4613 phy_interface_zero(mac->phylink_config.supported_interfaces); in mtk_add_mac()
4615 mac->phylink_config.supported_interfaces); in mtk_add_mac()
4618 phylink = phylink_create(&mac->phylink_config, in mtk_add_mac()
4619 of_fwnode_handle(mac->of_node), in mtk_add_mac()
4626 mac->phylink = phylink; in mtk_add_mac()
4628 SET_NETDEV_DEV(eth->netdev[id], eth->dev); in mtk_add_mac()
4629 eth->netdev[id]->watchdog_timeo = 5 * HZ; in mtk_add_mac()
4630 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; in mtk_add_mac()
4631 eth->netdev[id]->base_addr = (unsigned long)eth->base; in mtk_add_mac()
4633 eth->netdev[id]->hw_features = eth->soc->hw_features; in mtk_add_mac()
4634 if (eth->hwlro) in mtk_add_mac()
4635 eth->netdev[id]->hw_features |= NETIF_F_LRO; in mtk_add_mac()
4637 eth->netdev[id]->vlan_features = eth->soc->hw_features & in mtk_add_mac()
4639 eth->netdev[id]->features |= eth->soc->hw_features; in mtk_add_mac()
4640 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; in mtk_add_mac()
4642 eth->netdev[id]->irq = eth->irq[0]; in mtk_add_mac()
4643 eth->netdev[id]->dev.of_node = np; in mtk_add_mac()
4645 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) in mtk_add_mac()
4646 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; in mtk_add_mac()
4648 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; in mtk_add_mac()
4650 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { in mtk_add_mac()
4651 mac->device_notifier.notifier_call = mtk_device_event; in mtk_add_mac()
4652 register_netdevice_notifier(&mac->device_notifier); in mtk_add_mac()
4656 eth->netdev[id]->xdp_features = NETDEV_XDP_ACT_BASIC | in mtk_add_mac()
4664 free_netdev(eth->netdev[id]); in mtk_add_mac()
4677 dev = eth->netdev[i]; in mtk_eth_set_dma_device()
4679 if (!dev || !(dev->flags & IFF_UP)) in mtk_eth_set_dma_device()
4682 list_add_tail(&dev->close_list, &dev_list); in mtk_eth_set_dma_device()
4687 eth->dma_dev = dma_dev; in mtk_eth_set_dma_device()
4690 list_del_init(&dev->close_list); in mtk_eth_set_dma_device()
4705 np = of_parse_phandle(eth->dev->of_node, "mediatek,sgmiisys", i); in mtk_sgmii_init()
4719 eth->sgmii_pcs[i] = mtk_pcs_lynxi_create(eth->dev, regmap, in mtk_sgmii_init()
4720 eth->soc->ana_rgc3, in mtk_sgmii_init()
4734 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); in mtk_probe()
4736 return -ENOMEM; in mtk_probe()
4738 eth->soc = of_device_get_match_data(&pdev->dev); in mtk_probe()
4740 eth->dev = &pdev->dev; in mtk_probe()
4741 eth->dma_dev = &pdev->dev; in mtk_probe()
4742 eth->base = devm_platform_ioremap_resource(pdev, 0); in mtk_probe()
4743 if (IS_ERR(eth->base)) in mtk_probe()
4744 return PTR_ERR(eth->base); in mtk_probe()
4746 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) in mtk_probe()
4747 eth->ip_align = NET_IP_ALIGN; in mtk_probe()
4749 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) { in mtk_probe()
4755 eth->sram_base = (void __force *)devm_platform_ioremap_resource(pdev, 1); in mtk_probe()
4756 if (IS_ERR(eth->sram_base)) in mtk_probe()
4757 return PTR_ERR(eth->sram_base); in mtk_probe()
4759 eth->sram_base = (void __force *)eth->base + MTK_ETH_SRAM_OFFSET; in mtk_probe()
4763 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) { in mtk_probe()
4764 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(36)); in mtk_probe()
4766 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); in mtk_probe()
4769 dev_err(&pdev->dev, "Wrong DMA config\n"); in mtk_probe()
4770 return -EINVAL; in mtk_probe()
4774 spin_lock_init(ð->page_lock); in mtk_probe()
4775 spin_lock_init(ð->tx_irq_lock); in mtk_probe()
4776 spin_lock_init(ð->rx_irq_lock); in mtk_probe()
4777 spin_lock_init(ð->dim_lock); in mtk_probe()
4779 eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; in mtk_probe()
4780 INIT_WORK(ð->rx_dim.work, mtk_dim_rx); in mtk_probe()
4781 INIT_DELAYED_WORK(ð->reset.monitor_work, mtk_hw_reset_monitor_work); in mtk_probe()
4783 eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; in mtk_probe()
4784 INIT_WORK(ð->tx_dim.work, mtk_dim_tx); in mtk_probe()
4786 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { in mtk_probe()
4787 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, in mtk_probe()
4789 if (IS_ERR(eth->ethsys)) { in mtk_probe()
4790 dev_err(&pdev->dev, "no ethsys regmap found\n"); in mtk_probe()
4791 return PTR_ERR(eth->ethsys); in mtk_probe()
4795 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) { in mtk_probe()
4796 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, in mtk_probe()
4798 if (IS_ERR(eth->infra)) { in mtk_probe()
4799 dev_err(&pdev->dev, "no infracfg regmap found\n"); in mtk_probe()
4800 return PTR_ERR(eth->infra); in mtk_probe()
4804 if (of_dma_is_coherent(pdev->dev.of_node)) { in mtk_probe()
4807 cci = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, in mtk_probe()
4808 "cci-control-port"); in mtk_probe()
4814 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { in mtk_probe()
4821 if (eth->soc->required_pctl) { in mtk_probe()
4822 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, in mtk_probe()
4824 if (IS_ERR(eth->pctl)) { in mtk_probe()
4825 dev_err(&pdev->dev, "no pctl regmap found\n"); in mtk_probe()
4826 err = PTR_ERR(eth->pctl); in mtk_probe()
4834 err = -EINVAL; in mtk_probe()
4837 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) { in mtk_probe()
4841 err = -EINVAL; in mtk_probe()
4844 eth->phy_scratch_ring = res_sram->start; in mtk_probe()
4846 eth->phy_scratch_ring = res->start + MTK_ETH_SRAM_OFFSET; in mtk_probe()
4851 if (eth->soc->offload_version) { in mtk_probe()
4857 if (i >= ARRAY_SIZE(eth->soc->reg_map->wdma_base)) in mtk_probe()
4860 np = of_parse_phandle(pdev->dev.of_node, in mtk_probe()
4865 wdma_base = eth->soc->reg_map->wdma_base[i]; in mtk_probe()
4866 wdma_phy = res ? res->start + wdma_base : 0; in mtk_probe()
4867 mtk_wed_add_hw(np, eth, eth->base + wdma_base, in mtk_probe()
4873 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) in mtk_probe()
4874 eth->irq[i] = eth->irq[0]; in mtk_probe()
4876 eth->irq[i] = platform_get_irq(pdev, i); in mtk_probe()
4877 if (eth->irq[i] < 0) { in mtk_probe()
4878 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); in mtk_probe()
4879 err = -ENXIO; in mtk_probe()
4883 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { in mtk_probe()
4884 eth->clks[i] = devm_clk_get(eth->dev, in mtk_probe()
4886 if (IS_ERR(eth->clks[i])) { in mtk_probe()
4887 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) { in mtk_probe()
4888 err = -EPROBE_DEFER; in mtk_probe()
4891 if (eth->soc->required_clks & BIT(i)) { in mtk_probe()
4892 dev_err(&pdev->dev, "clock %s not found\n", in mtk_probe()
4894 err = -EINVAL; in mtk_probe()
4897 eth->clks[i] = NULL; in mtk_probe()
4901 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); in mtk_probe()
4902 INIT_WORK(ð->pending_work, mtk_pending_work); in mtk_probe()
4908 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); in mtk_probe()
4910 for_each_child_of_node(pdev->dev.of_node, mac_np) { in mtk_probe()
4912 "mediatek,eth-mac")) in mtk_probe()
4925 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) { in mtk_probe()
4926 err = devm_request_irq(eth->dev, eth->irq[0], in mtk_probe()
4928 dev_name(eth->dev), eth); in mtk_probe()
4930 err = devm_request_irq(eth->dev, eth->irq[1], in mtk_probe()
4932 dev_name(eth->dev), eth); in mtk_probe()
4936 err = devm_request_irq(eth->dev, eth->irq[2], in mtk_probe()
4938 dev_name(eth->dev), eth); in mtk_probe()
4944 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { in mtk_probe()
4950 if (eth->soc->offload_version) { in mtk_probe()
4953 num_ppe = min_t(u32, ARRAY_SIZE(eth->ppe), num_ppe); in mtk_probe()
4955 u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400; in mtk_probe()
4957 eth->ppe[i] = mtk_ppe_init(eth, eth->base + ppe_addr, i); in mtk_probe()
4959 if (!eth->ppe[i]) { in mtk_probe()
4960 err = -ENOMEM; in mtk_probe()
4971 if (!eth->netdev[i]) in mtk_probe()
4974 err = register_netdev(eth->netdev[i]); in mtk_probe()
4976 dev_err(eth->dev, "error bringing up device\n"); in mtk_probe()
4979 netif_info(eth, probe, eth->netdev[i], in mtk_probe()
4981 eth->netdev[i]->base_addr, eth->irq[0]); in mtk_probe()
4987 init_dummy_netdev(ð->dummy_dev); in mtk_probe()
4988 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx); in mtk_probe()
4989 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx); in mtk_probe()
4992 schedule_delayed_work(ð->reset.monitor_work, in mtk_probe()
5020 if (!eth->netdev[i]) in mtk_remove()
5022 mtk_stop(eth->netdev[i]); in mtk_remove()
5023 mac = netdev_priv(eth->netdev[i]); in mtk_remove()
5024 phylink_disconnect_phy(mac->phylink); in mtk_remove()
5030 netif_napi_del(ð->tx_napi); in mtk_remove()
5031 netif_napi_del(ð->rx_napi); in mtk_remove()
5219 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data },
5220 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data },
5221 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data },
5222 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data },
5223 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data },
5224 { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data },
5225 { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data },
5226 { .compatible = "mediatek,mt7988-eth", .data = &mt7988_data },
5227 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
5245 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");