Lines Matching +full:hw +full:- +full:device +full:- +full:address
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
12 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
13 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
14 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
15 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
16 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
17 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
18 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
19 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
20 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
21 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
22 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
23 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
25 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
26 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
29 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
30 * @hw: pointer to the hardware structure
35 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte) in ixgbe_out_i2c_byte_ack() argument
39 status = ixgbe_clock_out_i2c_byte(hw, byte); in ixgbe_out_i2c_byte_ack()
42 return ixgbe_get_i2c_ack(hw); in ixgbe_out_i2c_byte_ack()
46 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
47 * @hw: pointer to the hardware structure
52 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte) in ixgbe_in_i2c_byte_ack() argument
56 status = ixgbe_clock_in_i2c_byte(hw, byte); in ixgbe_in_i2c_byte_ack()
60 return ixgbe_clock_out_i2c_bit(hw, false); in ixgbe_in_i2c_byte_ack()
64 * ixgbe_ones_comp_byte_add - Perform one's complement addition
68 * Returns one's complement 8-bit sum.
79 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
80 * @hw: pointer to the hardware structure
81 * @addr: I2C bus address to read from
82 * @reg: I2C device register to read from
88 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, in ixgbe_read_i2c_combined_generic_int() argument
91 u32 swfw_mask = hw->phy.phy_semaphore_mask; in ixgbe_read_i2c_combined_generic_int()
104 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) in ixgbe_read_i2c_combined_generic_int()
105 return -EBUSY; in ixgbe_read_i2c_combined_generic_int()
106 ixgbe_i2c_start(hw); in ixgbe_read_i2c_combined_generic_int()
107 /* Device Address and write indication */ in ixgbe_read_i2c_combined_generic_int()
108 if (ixgbe_out_i2c_byte_ack(hw, addr)) in ixgbe_read_i2c_combined_generic_int()
111 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) in ixgbe_read_i2c_combined_generic_int()
114 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) in ixgbe_read_i2c_combined_generic_int()
117 if (ixgbe_out_i2c_byte_ack(hw, csum)) in ixgbe_read_i2c_combined_generic_int()
119 /* Re-start condition */ in ixgbe_read_i2c_combined_generic_int()
120 ixgbe_i2c_start(hw); in ixgbe_read_i2c_combined_generic_int()
121 /* Device Address and read indication */ in ixgbe_read_i2c_combined_generic_int()
122 if (ixgbe_out_i2c_byte_ack(hw, addr | 1)) in ixgbe_read_i2c_combined_generic_int()
125 if (ixgbe_in_i2c_byte_ack(hw, &high_bits)) in ixgbe_read_i2c_combined_generic_int()
128 if (ixgbe_in_i2c_byte_ack(hw, &low_bits)) in ixgbe_read_i2c_combined_generic_int()
131 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte)) in ixgbe_read_i2c_combined_generic_int()
134 if (ixgbe_clock_out_i2c_bit(hw, false)) in ixgbe_read_i2c_combined_generic_int()
136 ixgbe_i2c_stop(hw); in ixgbe_read_i2c_combined_generic_int()
138 hw->mac.ops.release_swfw_sync(hw, swfw_mask); in ixgbe_read_i2c_combined_generic_int()
143 ixgbe_i2c_bus_clear(hw); in ixgbe_read_i2c_combined_generic_int()
145 hw->mac.ops.release_swfw_sync(hw, swfw_mask); in ixgbe_read_i2c_combined_generic_int()
148 hw_dbg(hw, "I2C byte read combined error - Retry.\n"); in ixgbe_read_i2c_combined_generic_int()
150 hw_dbg(hw, "I2C byte read combined error.\n"); in ixgbe_read_i2c_combined_generic_int()
153 return -EIO; in ixgbe_read_i2c_combined_generic_int()
157 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
158 * @hw: pointer to the hardware structure
159 * @addr: I2C bus address to write to
160 * @reg: I2C device register to write to
166 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, in ixgbe_write_i2c_combined_generic_int() argument
169 u32 swfw_mask = hw->phy.phy_semaphore_mask; in ixgbe_write_i2c_combined_generic_int()
181 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) in ixgbe_write_i2c_combined_generic_int()
182 return -EBUSY; in ixgbe_write_i2c_combined_generic_int()
183 ixgbe_i2c_start(hw); in ixgbe_write_i2c_combined_generic_int()
184 /* Device Address and write indication */ in ixgbe_write_i2c_combined_generic_int()
185 if (ixgbe_out_i2c_byte_ack(hw, addr)) in ixgbe_write_i2c_combined_generic_int()
188 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) in ixgbe_write_i2c_combined_generic_int()
191 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) in ixgbe_write_i2c_combined_generic_int()
194 if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) in ixgbe_write_i2c_combined_generic_int()
197 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) in ixgbe_write_i2c_combined_generic_int()
200 if (ixgbe_out_i2c_byte_ack(hw, csum)) in ixgbe_write_i2c_combined_generic_int()
202 ixgbe_i2c_stop(hw); in ixgbe_write_i2c_combined_generic_int()
204 hw->mac.ops.release_swfw_sync(hw, swfw_mask); in ixgbe_write_i2c_combined_generic_int()
208 ixgbe_i2c_bus_clear(hw); in ixgbe_write_i2c_combined_generic_int()
210 hw->mac.ops.release_swfw_sync(hw, swfw_mask); in ixgbe_write_i2c_combined_generic_int()
213 hw_dbg(hw, "I2C byte write combined error - Retry.\n"); in ixgbe_write_i2c_combined_generic_int()
215 hw_dbg(hw, "I2C byte write combined error.\n"); in ixgbe_write_i2c_combined_generic_int()
218 return -EIO; in ixgbe_write_i2c_combined_generic_int()
222 * ixgbe_probe_phy - Probe a single address for a PHY
223 * @hw: pointer to hardware structure
224 * @phy_addr: PHY address to probe
228 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr) in ixgbe_probe_phy() argument
232 hw->phy.mdio.prtad = phy_addr; in ixgbe_probe_phy()
233 if (mdio45_probe(&hw->phy.mdio, phy_addr) != 0) in ixgbe_probe_phy()
236 if (ixgbe_get_phy_id(hw)) in ixgbe_probe_phy()
239 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id); in ixgbe_probe_phy()
241 if (hw->phy.type == ixgbe_phy_unknown) { in ixgbe_probe_phy()
242 hw->phy.ops.read_reg(hw, in ixgbe_probe_phy()
249 hw->phy.type = ixgbe_phy_cu_unknown; in ixgbe_probe_phy()
251 hw->phy.type = ixgbe_phy_generic; in ixgbe_probe_phy()
258 * ixgbe_identify_phy_generic - Get physical layer module
259 * @hw: pointer to hardware structure
263 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) in ixgbe_identify_phy_generic() argument
265 u32 status = -EFAULT; in ixgbe_identify_phy_generic()
268 if (!hw->phy.phy_semaphore_mask) { in ixgbe_identify_phy_generic()
269 if (hw->bus.lan_id) in ixgbe_identify_phy_generic()
270 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; in ixgbe_identify_phy_generic()
272 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; in ixgbe_identify_phy_generic()
275 if (hw->phy.type != ixgbe_phy_unknown) in ixgbe_identify_phy_generic()
278 if (hw->phy.nw_mng_if_sel) { in ixgbe_identify_phy_generic()
280 hw->phy.nw_mng_if_sel); in ixgbe_identify_phy_generic()
281 if (ixgbe_probe_phy(hw, phy_addr)) in ixgbe_identify_phy_generic()
284 return -EFAULT; in ixgbe_identify_phy_generic()
288 if (ixgbe_probe_phy(hw, phy_addr)) { in ixgbe_identify_phy_generic()
294 /* Certain media types do not have a phy so an address will not in ixgbe_identify_phy_generic()
299 hw->phy.mdio.prtad = MDIO_PRTAD_NONE; in ixgbe_identify_phy_generic()
305 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
306 * @hw: pointer to the hardware structure
313 bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw) in ixgbe_check_reset_blocked() argument
318 if (hw->mac.type == ixgbe_mac_82598EB) in ixgbe_check_reset_blocked()
321 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC); in ixgbe_check_reset_blocked()
323 hw_dbg(hw, "MNG_VETO bit detected.\n"); in ixgbe_check_reset_blocked()
331 * ixgbe_get_phy_id - Get the phy type
332 * @hw: pointer to hardware structure
335 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) in ixgbe_get_phy_id() argument
341 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD, in ixgbe_get_phy_id()
345 hw->phy.id = (u32)(phy_id_high << 16); in ixgbe_get_phy_id()
346 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD, in ixgbe_get_phy_id()
348 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); in ixgbe_get_phy_id()
349 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); in ixgbe_get_phy_id()
355 * ixgbe_get_phy_type_from_id - Get the phy type
394 * ixgbe_reset_phy_generic - Performs a PHY reset
395 * @hw: pointer to hardware structure
397 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) in ixgbe_reset_phy_generic() argument
403 if (hw->phy.type == ixgbe_phy_unknown) in ixgbe_reset_phy_generic()
404 status = ixgbe_identify_phy_generic(hw); in ixgbe_reset_phy_generic()
406 if (status != 0 || hw->phy.type == ixgbe_phy_none) in ixgbe_reset_phy_generic()
410 if (!hw->phy.reset_if_overtemp && hw->phy.ops.check_overtemp(hw)) in ixgbe_reset_phy_generic()
414 if (ixgbe_check_reset_blocked(hw)) in ixgbe_reset_phy_generic()
421 hw->phy.ops.write_reg(hw, MDIO_CTRL1, in ixgbe_reset_phy_generic()
426 * Poll for reset bit to self-clear indicating reset is complete. in ixgbe_reset_phy_generic()
432 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { in ixgbe_reset_phy_generic()
433 status = hw->phy.ops.read_reg(hw, in ixgbe_reset_phy_generic()
444 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1, in ixgbe_reset_phy_generic()
457 hw_dbg(hw, "PHY reset polling failed to complete.\n"); in ixgbe_reset_phy_generic()
458 return -EIO; in ixgbe_reset_phy_generic()
465 * ixgbe_read_phy_reg_mdi - read PHY register
466 * @hw: pointer to hardware structure
467 * @reg_addr: 32 bit address of PHY register to read
468 * @device_type: 5 bit device type
473 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, in ixgbe_read_phy_reg_mdi() argument
478 /* Setup and write the address cycle command */ in ixgbe_read_phy_reg_mdi()
481 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | in ixgbe_read_phy_reg_mdi()
484 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); in ixgbe_read_phy_reg_mdi()
486 /* Check every 10 usec to see if the address cycle completed. in ixgbe_read_phy_reg_mdi()
493 command = IXGBE_READ_REG(hw, IXGBE_MSCA); in ixgbe_read_phy_reg_mdi()
500 hw_dbg(hw, "PHY address command did not complete.\n"); in ixgbe_read_phy_reg_mdi()
501 return -EIO; in ixgbe_read_phy_reg_mdi()
504 /* Address cycle complete, setup and write the read in ixgbe_read_phy_reg_mdi()
509 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | in ixgbe_read_phy_reg_mdi()
512 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); in ixgbe_read_phy_reg_mdi()
514 /* Check every 10 usec to see if the address cycle in ixgbe_read_phy_reg_mdi()
521 command = IXGBE_READ_REG(hw, IXGBE_MSCA); in ixgbe_read_phy_reg_mdi()
527 hw_dbg(hw, "PHY read command didn't complete\n"); in ixgbe_read_phy_reg_mdi()
528 return -EIO; in ixgbe_read_phy_reg_mdi()
534 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); in ixgbe_read_phy_reg_mdi()
542 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
543 * using the SWFW lock - this function is needed in most cases
544 * @hw: pointer to hardware structure
545 * @reg_addr: 32 bit address of PHY register to read
546 * @device_type: 5 bit device type
549 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, in ixgbe_read_phy_reg_generic() argument
553 u32 gssr = hw->phy.phy_semaphore_mask; in ixgbe_read_phy_reg_generic()
555 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) { in ixgbe_read_phy_reg_generic()
556 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type, in ixgbe_read_phy_reg_generic()
558 hw->mac.ops.release_swfw_sync(hw, gssr); in ixgbe_read_phy_reg_generic()
560 return -EBUSY; in ixgbe_read_phy_reg_generic()
567 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
569 * @hw: pointer to hardware structure
571 * @device_type: 5 bit device type
574 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, in ixgbe_write_phy_reg_mdi() argument
580 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); in ixgbe_write_phy_reg_mdi()
582 /* Setup and write the address cycle command */ in ixgbe_write_phy_reg_mdi()
585 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | in ixgbe_write_phy_reg_mdi()
588 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); in ixgbe_write_phy_reg_mdi()
591 * Check every 10 usec to see if the address cycle completed. in ixgbe_write_phy_reg_mdi()
598 command = IXGBE_READ_REG(hw, IXGBE_MSCA); in ixgbe_write_phy_reg_mdi()
604 hw_dbg(hw, "PHY address cmd didn't complete\n"); in ixgbe_write_phy_reg_mdi()
605 return -EIO; in ixgbe_write_phy_reg_mdi()
609 * Address cycle complete, setup and write the write in ixgbe_write_phy_reg_mdi()
614 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | in ixgbe_write_phy_reg_mdi()
617 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); in ixgbe_write_phy_reg_mdi()
619 /* Check every 10 usec to see if the address cycle in ixgbe_write_phy_reg_mdi()
626 command = IXGBE_READ_REG(hw, IXGBE_MSCA); in ixgbe_write_phy_reg_mdi()
632 hw_dbg(hw, "PHY write cmd didn't complete\n"); in ixgbe_write_phy_reg_mdi()
633 return -EIO; in ixgbe_write_phy_reg_mdi()
640 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
641 * using SWFW lock- this function is needed in most cases
642 * @hw: pointer to hardware structure
644 * @device_type: 5 bit device type
647 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, in ixgbe_write_phy_reg_generic() argument
651 u32 gssr = hw->phy.phy_semaphore_mask; in ixgbe_write_phy_reg_generic()
653 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) { in ixgbe_write_phy_reg_generic()
654 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, in ixgbe_write_phy_reg_generic()
656 hw->mac.ops.release_swfw_sync(hw, gssr); in ixgbe_write_phy_reg_generic()
658 return -EBUSY; in ixgbe_write_phy_reg_generic()
664 #define IXGBE_HW_READ_REG(addr) IXGBE_READ_REG(hw, addr)
667 * ixgbe_msca_cmd - Write the command register and poll for completion/timeout
668 * @hw: pointer to hardware structure
671 static s32 ixgbe_msca_cmd(struct ixgbe_hw *hw, u32 cmd) in ixgbe_msca_cmd() argument
673 IXGBE_WRITE_REG(hw, IXGBE_MSCA, cmd); in ixgbe_msca_cmd()
681 * ixgbe_mii_bus_read_generic_c22 - Read a clause 22 register with gssr flags
682 * @hw: pointer to hardware structure
683 * @addr: address
687 static s32 ixgbe_mii_bus_read_generic_c22(struct ixgbe_hw *hw, int addr, in ixgbe_mii_bus_read_generic_c22() argument
693 if (hw->mac.ops.acquire_swfw_sync(hw, gssr)) in ixgbe_mii_bus_read_generic_c22()
694 return -EBUSY; in ixgbe_mii_bus_read_generic_c22()
701 data = ixgbe_msca_cmd(hw, cmd); in ixgbe_mii_bus_read_generic_c22()
705 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); in ixgbe_mii_bus_read_generic_c22()
709 hw->mac.ops.release_swfw_sync(hw, gssr); in ixgbe_mii_bus_read_generic_c22()
714 * ixgbe_mii_bus_read_generic_c45 - Read a clause 45 register with gssr flags
715 * @hw: pointer to hardware structure
716 * @addr: address
717 * @devad: device address to read
721 static s32 ixgbe_mii_bus_read_generic_c45(struct ixgbe_hw *hw, int addr, in ixgbe_mii_bus_read_generic_c45() argument
727 if (hw->mac.ops.acquire_swfw_sync(hw, gssr)) in ixgbe_mii_bus_read_generic_c45()
728 return -EBUSY; in ixgbe_mii_bus_read_generic_c45()
734 data = ixgbe_msca_cmd(hw, cmd); in ixgbe_mii_bus_read_generic_c45()
739 data = ixgbe_msca_cmd(hw, cmd); in ixgbe_mii_bus_read_generic_c45()
743 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); in ixgbe_mii_bus_read_generic_c45()
747 hw->mac.ops.release_swfw_sync(hw, gssr); in ixgbe_mii_bus_read_generic_c45()
752 * ixgbe_mii_bus_write_generic_c22 - Write a clause 22 register with gssr flags
753 * @hw: pointer to hardware structure
754 * @addr: address
759 static s32 ixgbe_mii_bus_write_generic_c22(struct ixgbe_hw *hw, int addr, in ixgbe_mii_bus_write_generic_c22() argument
765 if (hw->mac.ops.acquire_swfw_sync(hw, gssr)) in ixgbe_mii_bus_write_generic_c22()
766 return -EBUSY; in ixgbe_mii_bus_write_generic_c22()
768 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)val); in ixgbe_mii_bus_write_generic_c22()
775 err = ixgbe_msca_cmd(hw, cmd); in ixgbe_mii_bus_write_generic_c22()
777 hw->mac.ops.release_swfw_sync(hw, gssr); in ixgbe_mii_bus_write_generic_c22()
782 * ixgbe_mii_bus_write_generic_c45 - Write a clause 45 register with gssr flags
783 * @hw: pointer to hardware structure
784 * @addr: address
785 * @devad: device address to read
790 static s32 ixgbe_mii_bus_write_generic_c45(struct ixgbe_hw *hw, int addr, in ixgbe_mii_bus_write_generic_c45() argument
797 if (hw->mac.ops.acquire_swfw_sync(hw, gssr)) in ixgbe_mii_bus_write_generic_c45()
798 return -EBUSY; in ixgbe_mii_bus_write_generic_c45()
800 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)val); in ixgbe_mii_bus_write_generic_c45()
806 err = ixgbe_msca_cmd(hw, cmd); in ixgbe_mii_bus_write_generic_c45()
811 err = ixgbe_msca_cmd(hw, cmd); in ixgbe_mii_bus_write_generic_c45()
814 hw->mac.ops.release_swfw_sync(hw, gssr); in ixgbe_mii_bus_write_generic_c45()
819 * ixgbe_mii_bus_read_c22 - Read a clause 22 register
821 * @addr: address
826 struct ixgbe_adapter *adapter = bus->priv; in ixgbe_mii_bus_read_c22()
827 struct ixgbe_hw *hw = &adapter->hw; in ixgbe_mii_bus_read_c22() local
828 u32 gssr = hw->phy.phy_semaphore_mask; in ixgbe_mii_bus_read_c22()
830 return ixgbe_mii_bus_read_generic_c22(hw, addr, regnum, gssr); in ixgbe_mii_bus_read_c22()
834 * ixgbe_mii_bus_read_c45 - Read a clause 45 register
836 * @devad: device address to read
837 * @addr: address
843 struct ixgbe_adapter *adapter = bus->priv; in ixgbe_mii_bus_read_c45()
844 struct ixgbe_hw *hw = &adapter->hw; in ixgbe_mii_bus_read_c45() local
845 u32 gssr = hw->phy.phy_semaphore_mask; in ixgbe_mii_bus_read_c45()
847 return ixgbe_mii_bus_read_generic_c45(hw, addr, devad, regnum, gssr); in ixgbe_mii_bus_read_c45()
851 * ixgbe_mii_bus_write_c22 - Write a clause 22 register
853 * @addr: address
860 struct ixgbe_adapter *adapter = bus->priv; in ixgbe_mii_bus_write_c22()
861 struct ixgbe_hw *hw = &adapter->hw; in ixgbe_mii_bus_write_c22() local
862 u32 gssr = hw->phy.phy_semaphore_mask; in ixgbe_mii_bus_write_c22()
864 return ixgbe_mii_bus_write_generic_c22(hw, addr, regnum, val, gssr); in ixgbe_mii_bus_write_c22()
868 * ixgbe_mii_bus_write_c45 - Write a clause 45 register
870 * @addr: address
871 * @devad: device address to read
878 struct ixgbe_adapter *adapter = bus->priv; in ixgbe_mii_bus_write_c45()
879 struct ixgbe_hw *hw = &adapter->hw; in ixgbe_mii_bus_write_c45() local
880 u32 gssr = hw->phy.phy_semaphore_mask; in ixgbe_mii_bus_write_c45()
882 return ixgbe_mii_bus_write_generic_c45(hw, addr, devad, regnum, val, in ixgbe_mii_bus_write_c45()
887 * ixgbe_x550em_a_mii_bus_read_c22 - Read a clause 22 register on x550em_a
889 * @addr: address
895 struct ixgbe_adapter *adapter = bus->priv; in ixgbe_x550em_a_mii_bus_read_c22()
896 struct ixgbe_hw *hw = &adapter->hw; in ixgbe_x550em_a_mii_bus_read_c22() local
897 u32 gssr = hw->phy.phy_semaphore_mask; in ixgbe_x550em_a_mii_bus_read_c22()
900 return ixgbe_mii_bus_read_generic_c22(hw, addr, regnum, gssr); in ixgbe_x550em_a_mii_bus_read_c22()
904 * ixgbe_x550em_a_mii_bus_read_c45 - Read a clause 45 register on x550em_a
906 * @addr: address
907 * @devad: device address to read
913 struct ixgbe_adapter *adapter = bus->priv; in ixgbe_x550em_a_mii_bus_read_c45()
914 struct ixgbe_hw *hw = &adapter->hw; in ixgbe_x550em_a_mii_bus_read_c45() local
915 u32 gssr = hw->phy.phy_semaphore_mask; in ixgbe_x550em_a_mii_bus_read_c45()
918 return ixgbe_mii_bus_read_generic_c45(hw, addr, devad, regnum, gssr); in ixgbe_x550em_a_mii_bus_read_c45()
922 * ixgbe_x550em_a_mii_bus_write_c22 - Write a clause 22 register on x550em_a
924 * @addr: address
931 struct ixgbe_adapter *adapter = bus->priv; in ixgbe_x550em_a_mii_bus_write_c22()
932 struct ixgbe_hw *hw = &adapter->hw; in ixgbe_x550em_a_mii_bus_write_c22() local
933 u32 gssr = hw->phy.phy_semaphore_mask; in ixgbe_x550em_a_mii_bus_write_c22()
936 return ixgbe_mii_bus_write_generic_c22(hw, addr, regnum, val, gssr); in ixgbe_x550em_a_mii_bus_write_c22()
940 * ixgbe_x550em_a_mii_bus_write_c45 - Write a clause 45 register on x550em_a
942 * @addr: address
943 * @devad: device address to read
950 struct ixgbe_adapter *adapter = bus->priv; in ixgbe_x550em_a_mii_bus_write_c45()
951 struct ixgbe_hw *hw = &adapter->hw; in ixgbe_x550em_a_mii_bus_write_c45() local
952 u32 gssr = hw->phy.phy_semaphore_mask; in ixgbe_x550em_a_mii_bus_write_c45()
955 return ixgbe_mii_bus_write_generic_c45(hw, addr, devad, regnum, val, in ixgbe_x550em_a_mii_bus_write_c45()
960 * ixgbe_get_first_secondary_devfn - get first device downstream of root port
972 if (rp_pdev && rp_pdev->subordinate) { in ixgbe_get_first_secondary_devfn()
973 bus = rp_pdev->subordinate->number; in ixgbe_get_first_secondary_devfn()
983 * ixgbe_x550em_a_has_mii - is this the first ixgbe x550em_a PCI function?
984 * @hw: pointer to hardware structure
986 * Returns true if hw points to lowest numbered PCI B:D.F x550_em_a device in
990 static bool ixgbe_x550em_a_has_mii(struct ixgbe_hw *hw) in ixgbe_x550em_a_has_mii() argument
992 struct ixgbe_adapter *adapter = hw->back; in ixgbe_x550em_a_has_mii()
993 struct pci_dev *pdev = adapter->pdev; in ixgbe_x550em_a_has_mii()
1000 * so the lowest numbered ixgbe dev will be device 0 function 0 on one in ixgbe_x550em_a_has_mii()
1019 * ixgbe_mii_bus_init - mii_bus structure setup
1020 * @hw: pointer to hardware structure
1026 s32 ixgbe_mii_bus_init(struct ixgbe_hw *hw) in ixgbe_mii_bus_init() argument
1033 struct ixgbe_adapter *adapter = hw->back; in ixgbe_mii_bus_init()
1034 struct pci_dev *pdev = adapter->pdev; in ixgbe_mii_bus_init()
1035 struct device *dev = &adapter->netdev->dev; in ixgbe_mii_bus_init()
1038 switch (hw->device_id) { in ixgbe_mii_bus_init()
1049 if (!ixgbe_x550em_a_has_mii(hw)) in ixgbe_mii_bus_init()
1066 return -ENOMEM; in ixgbe_mii_bus_init()
1068 bus->read = read_c22; in ixgbe_mii_bus_init()
1069 bus->write = write_c22; in ixgbe_mii_bus_init()
1070 bus->read_c45 = read_c45; in ixgbe_mii_bus_init()
1071 bus->write_c45 = write_c45; in ixgbe_mii_bus_init()
1073 /* Use the position of the device in the PCI hierarchy as the id */ in ixgbe_mii_bus_init()
1074 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mdio-%s", ixgbe_driver_name, in ixgbe_mii_bus_init()
1077 bus->name = "ixgbe-mdio"; in ixgbe_mii_bus_init()
1078 bus->priv = adapter; in ixgbe_mii_bus_init()
1079 bus->parent = dev; in ixgbe_mii_bus_init()
1080 bus->phy_mask = GENMASK(31, 0); in ixgbe_mii_bus_init()
1086 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_SUPPORTS_C22; in ixgbe_mii_bus_init()
1088 adapter->mii_bus = bus; in ixgbe_mii_bus_init()
1093 * ixgbe_setup_phy_link_generic - Set and restart autoneg
1094 * @hw: pointer to hardware structure
1098 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) in ixgbe_setup_phy_link_generic() argument
1105 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); in ixgbe_setup_phy_link_generic()
1107 /* Set or unset auto-negotiation 10G advertisement */ in ixgbe_setup_phy_link_generic()
1108 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, &autoneg_reg); in ixgbe_setup_phy_link_generic()
1111 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) && in ixgbe_setup_phy_link_generic()
1115 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, autoneg_reg); in ixgbe_setup_phy_link_generic()
1117 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, in ixgbe_setup_phy_link_generic()
1120 if (hw->mac.type == ixgbe_mac_X550) { in ixgbe_setup_phy_link_generic()
1121 /* Set or unset auto-negotiation 5G advertisement */ in ixgbe_setup_phy_link_generic()
1123 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) && in ixgbe_setup_phy_link_generic()
1127 /* Set or unset auto-negotiation 2.5G advertisement */ in ixgbe_setup_phy_link_generic()
1129 if ((hw->phy.autoneg_advertised & in ixgbe_setup_phy_link_generic()
1135 /* Set or unset auto-negotiation 1G advertisement */ in ixgbe_setup_phy_link_generic()
1137 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) && in ixgbe_setup_phy_link_generic()
1141 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, in ixgbe_setup_phy_link_generic()
1144 /* Set or unset auto-negotiation 100M advertisement */ in ixgbe_setup_phy_link_generic()
1145 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg); in ixgbe_setup_phy_link_generic()
1148 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) && in ixgbe_setup_phy_link_generic()
1152 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg); in ixgbe_setup_phy_link_generic()
1155 if (ixgbe_check_reset_blocked(hw)) in ixgbe_setup_phy_link_generic()
1159 hw->phy.ops.read_reg(hw, MDIO_CTRL1, in ixgbe_setup_phy_link_generic()
1164 hw->phy.ops.write_reg(hw, MDIO_CTRL1, in ixgbe_setup_phy_link_generic()
1171 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
1172 * @hw: pointer to hardware structure
1176 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, in ixgbe_setup_phy_link_speed_generic() argument
1183 hw->phy.autoneg_advertised = 0; in ixgbe_setup_phy_link_speed_generic()
1186 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; in ixgbe_setup_phy_link_speed_generic()
1189 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL; in ixgbe_setup_phy_link_speed_generic()
1192 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL; in ixgbe_setup_phy_link_speed_generic()
1195 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; in ixgbe_setup_phy_link_speed_generic()
1198 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; in ixgbe_setup_phy_link_speed_generic()
1201 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL; in ixgbe_setup_phy_link_speed_generic()
1204 if (hw->phy.ops.setup_link) in ixgbe_setup_phy_link_speed_generic()
1205 hw->phy.ops.setup_link(hw); in ixgbe_setup_phy_link_speed_generic()
1211 * ixgbe_get_copper_speeds_supported - Get copper link speed from phy
1212 * @hw: pointer to hardware structure
1217 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw) in ixgbe_get_copper_speeds_supported() argument
1222 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD, in ixgbe_get_copper_speeds_supported()
1228 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL; in ixgbe_get_copper_speeds_supported()
1230 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL; in ixgbe_get_copper_speeds_supported()
1232 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL; in ixgbe_get_copper_speeds_supported()
1234 switch (hw->mac.type) { in ixgbe_get_copper_speeds_supported()
1236 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL; in ixgbe_get_copper_speeds_supported()
1237 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL; in ixgbe_get_copper_speeds_supported()
1241 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL; in ixgbe_get_copper_speeds_supported()
1251 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
1252 * @hw: pointer to hardware structure
1254 * @autoneg: boolean auto-negotiation value
1256 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, in ixgbe_get_copper_link_capabilities_generic() argument
1263 if (!hw->phy.speeds_supported) in ixgbe_get_copper_link_capabilities_generic()
1264 status = ixgbe_get_copper_speeds_supported(hw); in ixgbe_get_copper_link_capabilities_generic()
1266 *speed = hw->phy.speeds_supported; in ixgbe_get_copper_link_capabilities_generic()
1271 * ixgbe_check_phy_link_tnx - Determine link and speed status
1272 * @hw: pointer to hardware structure
1279 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, in ixgbe_check_phy_link_tnx() argument
1300 status = hw->phy.ops.read_reg(hw, in ixgbe_check_phy_link_tnx()
1321 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
1322 * @hw: pointer to hardware structure
1329 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) in ixgbe_setup_phy_link_tnx() argument
1335 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); in ixgbe_setup_phy_link_tnx()
1338 /* Set or unset auto-negotiation 10G advertisement */ in ixgbe_setup_phy_link_tnx()
1339 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, in ixgbe_setup_phy_link_tnx()
1344 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) in ixgbe_setup_phy_link_tnx()
1347 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, in ixgbe_setup_phy_link_tnx()
1353 /* Set or unset auto-negotiation 1G advertisement */ in ixgbe_setup_phy_link_tnx()
1354 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, in ixgbe_setup_phy_link_tnx()
1359 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) in ixgbe_setup_phy_link_tnx()
1362 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, in ixgbe_setup_phy_link_tnx()
1368 /* Set or unset auto-negotiation 100M advertisement */ in ixgbe_setup_phy_link_tnx()
1369 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, in ixgbe_setup_phy_link_tnx()
1375 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) in ixgbe_setup_phy_link_tnx()
1378 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, in ixgbe_setup_phy_link_tnx()
1384 if (ixgbe_check_reset_blocked(hw)) in ixgbe_setup_phy_link_tnx()
1388 hw->phy.ops.read_reg(hw, MDIO_CTRL1, in ixgbe_setup_phy_link_tnx()
1393 hw->phy.ops.write_reg(hw, MDIO_CTRL1, in ixgbe_setup_phy_link_tnx()
1399 * ixgbe_reset_phy_nl - Performs a PHY reset
1400 * @hw: pointer to hardware structure
1402 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) in ixgbe_reset_phy_nl() argument
1412 if (ixgbe_check_reset_blocked(hw)) in ixgbe_reset_phy_nl()
1415 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data); in ixgbe_reset_phy_nl()
1418 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, in ixgbe_reset_phy_nl()
1422 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, in ixgbe_reset_phy_nl()
1430 hw_dbg(hw, "PHY reset did not complete.\n"); in ixgbe_reset_phy_nl()
1431 return -EIO; in ixgbe_reset_phy_nl()
1435 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, in ixgbe_reset_phy_nl()
1440 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); in ixgbe_reset_phy_nl()
1446 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); in ixgbe_reset_phy_nl()
1454 hw_dbg(hw, "DELAY: %d MS\n", edata); in ixgbe_reset_phy_nl()
1458 hw_dbg(hw, "DATA:\n"); in ixgbe_reset_phy_nl()
1460 ret_val = hw->eeprom.ops.read(hw, data_offset++, in ixgbe_reset_phy_nl()
1465 ret_val = hw->eeprom.ops.read(hw, data_offset, in ixgbe_reset_phy_nl()
1469 hw->phy.ops.write_reg(hw, phy_offset, in ixgbe_reset_phy_nl()
1471 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword, in ixgbe_reset_phy_nl()
1479 hw_dbg(hw, "CONTROL:\n"); in ixgbe_reset_phy_nl()
1481 hw_dbg(hw, "EOL\n"); in ixgbe_reset_phy_nl()
1484 hw_dbg(hw, "SOL\n"); in ixgbe_reset_phy_nl()
1486 hw_dbg(hw, "Bad control value\n"); in ixgbe_reset_phy_nl()
1487 return -EIO; in ixgbe_reset_phy_nl()
1491 hw_dbg(hw, "Bad control type\n"); in ixgbe_reset_phy_nl()
1492 return -EIO; in ixgbe_reset_phy_nl()
1499 hw_err(hw, "eeprom read at offset %d failed\n", data_offset); in ixgbe_reset_phy_nl()
1500 return -EIO; in ixgbe_reset_phy_nl()
1504 * ixgbe_identify_module_generic - Identifies module type
1505 * @hw: pointer to hardware structure
1507 * Determines HW type and calls appropriate function.
1509 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) in ixgbe_identify_module_generic() argument
1511 switch (hw->mac.ops.get_media_type(hw)) { in ixgbe_identify_module_generic()
1513 return ixgbe_identify_sfp_module_generic(hw); in ixgbe_identify_module_generic()
1515 return ixgbe_identify_qsfp_module_generic(hw); in ixgbe_identify_module_generic()
1517 hw->phy.sfp_type = ixgbe_sfp_type_not_present; in ixgbe_identify_module_generic()
1518 return -ENOENT; in ixgbe_identify_module_generic()
1521 return -ENOENT; in ixgbe_identify_module_generic()
1525 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1526 * @hw: pointer to hardware structure
1530 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) in ixgbe_identify_sfp_module_generic() argument
1532 struct ixgbe_adapter *adapter = hw->back; in ixgbe_identify_sfp_module_generic()
1535 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; in ixgbe_identify_sfp_module_generic()
1544 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { in ixgbe_identify_sfp_module_generic()
1545 hw->phy.sfp_type = ixgbe_sfp_type_not_present; in ixgbe_identify_sfp_module_generic()
1546 return -ENOENT; in ixgbe_identify_sfp_module_generic()
1550 hw->mac.ops.set_lan_id(hw); in ixgbe_identify_sfp_module_generic()
1552 status = hw->phy.ops.read_i2c_eeprom(hw, in ixgbe_identify_sfp_module_generic()
1560 hw->phy.type = ixgbe_phy_sfp_unsupported; in ixgbe_identify_sfp_module_generic()
1561 return -EOPNOTSUPP; in ixgbe_identify_sfp_module_generic()
1563 status = hw->phy.ops.read_i2c_eeprom(hw, in ixgbe_identify_sfp_module_generic()
1570 status = hw->phy.ops.read_i2c_eeprom(hw, in ixgbe_identify_sfp_module_generic()
1576 status = hw->phy.ops.read_i2c_eeprom(hw, in ixgbe_identify_sfp_module_generic()
1588 * 3 SFP_DA_CORE0 - 82599-specific in ixgbe_identify_sfp_module_generic()
1589 * 4 SFP_DA_CORE1 - 82599-specific in ixgbe_identify_sfp_module_generic()
1590 * 5 SFP_SR/LR_CORE0 - 82599-specific in ixgbe_identify_sfp_module_generic()
1591 * 6 SFP_SR/LR_CORE1 - 82599-specific in ixgbe_identify_sfp_module_generic()
1592 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific in ixgbe_identify_sfp_module_generic()
1593 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific in ixgbe_identify_sfp_module_generic()
1594 * 9 SFP_1g_cu_CORE0 - 82599-specific in ixgbe_identify_sfp_module_generic()
1595 * 10 SFP_1g_cu_CORE1 - 82599-specific in ixgbe_identify_sfp_module_generic()
1596 * 11 SFP_1g_sx_CORE0 - 82599-specific in ixgbe_identify_sfp_module_generic()
1597 * 12 SFP_1g_sx_CORE1 - 82599-specific in ixgbe_identify_sfp_module_generic()
1599 if (hw->mac.type == ixgbe_mac_82598EB) { in ixgbe_identify_sfp_module_generic()
1601 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; in ixgbe_identify_sfp_module_generic()
1603 hw->phy.sfp_type = ixgbe_sfp_type_sr; in ixgbe_identify_sfp_module_generic()
1605 hw->phy.sfp_type = ixgbe_sfp_type_lr; in ixgbe_identify_sfp_module_generic()
1607 hw->phy.sfp_type = ixgbe_sfp_type_unknown; in ixgbe_identify_sfp_module_generic()
1610 if (hw->bus.lan_id == 0) in ixgbe_identify_sfp_module_generic()
1611 hw->phy.sfp_type = in ixgbe_identify_sfp_module_generic()
1614 hw->phy.sfp_type = in ixgbe_identify_sfp_module_generic()
1617 hw->phy.ops.read_i2c_eeprom( in ixgbe_identify_sfp_module_generic()
1618 hw, IXGBE_SFF_CABLE_SPEC_COMP, in ixgbe_identify_sfp_module_generic()
1622 if (hw->bus.lan_id == 0) in ixgbe_identify_sfp_module_generic()
1623 hw->phy.sfp_type = in ixgbe_identify_sfp_module_generic()
1626 hw->phy.sfp_type = in ixgbe_identify_sfp_module_generic()
1629 hw->phy.sfp_type = in ixgbe_identify_sfp_module_generic()
1635 if (hw->bus.lan_id == 0) in ixgbe_identify_sfp_module_generic()
1636 hw->phy.sfp_type = in ixgbe_identify_sfp_module_generic()
1639 hw->phy.sfp_type = in ixgbe_identify_sfp_module_generic()
1642 if (hw->bus.lan_id == 0) in ixgbe_identify_sfp_module_generic()
1643 hw->phy.sfp_type = in ixgbe_identify_sfp_module_generic()
1646 hw->phy.sfp_type = in ixgbe_identify_sfp_module_generic()
1649 if (hw->bus.lan_id == 0) in ixgbe_identify_sfp_module_generic()
1650 hw->phy.sfp_type = in ixgbe_identify_sfp_module_generic()
1653 hw->phy.sfp_type = in ixgbe_identify_sfp_module_generic()
1656 if (hw->bus.lan_id == 0) in ixgbe_identify_sfp_module_generic()
1657 hw->phy.sfp_type = in ixgbe_identify_sfp_module_generic()
1660 hw->phy.sfp_type = in ixgbe_identify_sfp_module_generic()
1663 hw->phy.sfp_type = ixgbe_sfp_type_unknown; in ixgbe_identify_sfp_module_generic()
1667 if (hw->phy.sfp_type != stored_sfp_type) in ixgbe_identify_sfp_module_generic()
1668 hw->phy.sfp_setup_needed = true; in ixgbe_identify_sfp_module_generic()
1671 hw->phy.multispeed_fiber = false; in ixgbe_identify_sfp_module_generic()
1676 hw->phy.multispeed_fiber = true; in ixgbe_identify_sfp_module_generic()
1679 if (hw->phy.type != ixgbe_phy_nl) { in ixgbe_identify_sfp_module_generic()
1680 hw->phy.id = identifier; in ixgbe_identify_sfp_module_generic()
1681 status = hw->phy.ops.read_i2c_eeprom(hw, in ixgbe_identify_sfp_module_generic()
1688 status = hw->phy.ops.read_i2c_eeprom(hw, in ixgbe_identify_sfp_module_generic()
1695 status = hw->phy.ops.read_i2c_eeprom(hw, in ixgbe_identify_sfp_module_generic()
1710 hw->phy.type = in ixgbe_identify_sfp_module_generic()
1715 hw->phy.type = ixgbe_phy_sfp_ftl_active; in ixgbe_identify_sfp_module_generic()
1717 hw->phy.type = ixgbe_phy_sfp_ftl; in ixgbe_identify_sfp_module_generic()
1720 hw->phy.type = ixgbe_phy_sfp_avago; in ixgbe_identify_sfp_module_generic()
1723 hw->phy.type = ixgbe_phy_sfp_intel; in ixgbe_identify_sfp_module_generic()
1727 hw->phy.type = in ixgbe_identify_sfp_module_generic()
1730 hw->phy.type = in ixgbe_identify_sfp_module_generic()
1733 hw->phy.type = ixgbe_phy_sfp_unknown; in ixgbe_identify_sfp_module_generic()
1745 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || in ixgbe_identify_sfp_module_generic()
1746 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || in ixgbe_identify_sfp_module_generic()
1747 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || in ixgbe_identify_sfp_module_generic()
1748 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || in ixgbe_identify_sfp_module_generic()
1749 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || in ixgbe_identify_sfp_module_generic()
1750 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { in ixgbe_identify_sfp_module_generic()
1751 hw->phy.type = ixgbe_phy_sfp_unsupported; in ixgbe_identify_sfp_module_generic()
1752 return -EOPNOTSUPP; in ixgbe_identify_sfp_module_generic()
1755 /* Anything else 82598-based is supported */ in ixgbe_identify_sfp_module_generic()
1756 if (hw->mac.type == ixgbe_mac_82598EB) in ixgbe_identify_sfp_module_generic()
1759 hw->mac.ops.get_device_caps(hw, &enforce_sfp); in ixgbe_identify_sfp_module_generic()
1761 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || in ixgbe_identify_sfp_module_generic()
1762 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || in ixgbe_identify_sfp_module_generic()
1763 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || in ixgbe_identify_sfp_module_generic()
1764 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || in ixgbe_identify_sfp_module_generic()
1765 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || in ixgbe_identify_sfp_module_generic()
1766 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { in ixgbe_identify_sfp_module_generic()
1768 if (hw->phy.type == ixgbe_phy_sfp_intel) in ixgbe_identify_sfp_module_generic()
1770 if (hw->allow_unsupported_sfp) { in ixgbe_identify_sfp_module_generic()
1774 hw_dbg(hw, "SFP+ module not supported\n"); in ixgbe_identify_sfp_module_generic()
1775 hw->phy.type = ixgbe_phy_sfp_unsupported; in ixgbe_identify_sfp_module_generic()
1776 return -EOPNOTSUPP; in ixgbe_identify_sfp_module_generic()
1781 hw->phy.sfp_type = ixgbe_sfp_type_not_present; in ixgbe_identify_sfp_module_generic()
1782 if (hw->phy.type != ixgbe_phy_nl) { in ixgbe_identify_sfp_module_generic()
1783 hw->phy.id = 0; in ixgbe_identify_sfp_module_generic()
1784 hw->phy.type = ixgbe_phy_unknown; in ixgbe_identify_sfp_module_generic()
1786 return -ENOENT; in ixgbe_identify_sfp_module_generic()
1790 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1791 * @hw: pointer to hardware structure
1795 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) in ixgbe_identify_qsfp_module_generic() argument
1797 struct ixgbe_adapter *adapter = hw->back; in ixgbe_identify_qsfp_module_generic()
1800 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; in ixgbe_identify_qsfp_module_generic()
1811 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { in ixgbe_identify_qsfp_module_generic()
1812 hw->phy.sfp_type = ixgbe_sfp_type_not_present; in ixgbe_identify_qsfp_module_generic()
1813 return -ENOENT; in ixgbe_identify_qsfp_module_generic()
1817 hw->mac.ops.set_lan_id(hw); in ixgbe_identify_qsfp_module_generic()
1819 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, in ixgbe_identify_qsfp_module_generic()
1826 hw->phy.type = ixgbe_phy_sfp_unsupported; in ixgbe_identify_qsfp_module_generic()
1827 return -EOPNOTSUPP; in ixgbe_identify_qsfp_module_generic()
1830 hw->phy.id = identifier; in ixgbe_identify_qsfp_module_generic()
1832 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, in ixgbe_identify_qsfp_module_generic()
1838 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, in ixgbe_identify_qsfp_module_generic()
1845 hw->phy.type = ixgbe_phy_qsfp_passive_unknown; in ixgbe_identify_qsfp_module_generic()
1846 if (hw->bus.lan_id == 0) in ixgbe_identify_qsfp_module_generic()
1847 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; in ixgbe_identify_qsfp_module_generic()
1849 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; in ixgbe_identify_qsfp_module_generic()
1852 if (hw->bus.lan_id == 0) in ixgbe_identify_qsfp_module_generic()
1853 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; in ixgbe_identify_qsfp_module_generic()
1855 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; in ixgbe_identify_qsfp_module_generic()
1861 /* check for active DA cables that pre-date in ixgbe_identify_qsfp_module_generic()
1862 * SFF-8436 v3.6 in ixgbe_identify_qsfp_module_generic()
1864 hw->phy.ops.read_i2c_eeprom(hw, in ixgbe_identify_qsfp_module_generic()
1868 hw->phy.ops.read_i2c_eeprom(hw, in ixgbe_identify_qsfp_module_generic()
1872 hw->phy.ops.read_i2c_eeprom(hw, in ixgbe_identify_qsfp_module_generic()
1885 hw->phy.type = ixgbe_phy_qsfp_active_unknown; in ixgbe_identify_qsfp_module_generic()
1886 if (hw->bus.lan_id == 0) in ixgbe_identify_qsfp_module_generic()
1887 hw->phy.sfp_type = in ixgbe_identify_qsfp_module_generic()
1890 hw->phy.sfp_type = in ixgbe_identify_qsfp_module_generic()
1894 hw->phy.type = ixgbe_phy_sfp_unsupported; in ixgbe_identify_qsfp_module_generic()
1895 return -EOPNOTSUPP; in ixgbe_identify_qsfp_module_generic()
1899 if (hw->phy.sfp_type != stored_sfp_type) in ixgbe_identify_qsfp_module_generic()
1900 hw->phy.sfp_setup_needed = true; in ixgbe_identify_qsfp_module_generic()
1903 hw->phy.multispeed_fiber = false; in ixgbe_identify_qsfp_module_generic()
1908 hw->phy.multispeed_fiber = true; in ixgbe_identify_qsfp_module_generic()
1913 status = hw->phy.ops.read_i2c_eeprom(hw, in ixgbe_identify_qsfp_module_generic()
1920 status = hw->phy.ops.read_i2c_eeprom(hw, in ixgbe_identify_qsfp_module_generic()
1927 status = hw->phy.ops.read_i2c_eeprom(hw, in ixgbe_identify_qsfp_module_generic()
1940 hw->phy.type = ixgbe_phy_qsfp_intel; in ixgbe_identify_qsfp_module_generic()
1942 hw->phy.type = ixgbe_phy_qsfp_unknown; in ixgbe_identify_qsfp_module_generic()
1944 hw->mac.ops.get_device_caps(hw, &enforce_sfp); in ixgbe_identify_qsfp_module_generic()
1947 if (hw->phy.type == ixgbe_phy_qsfp_intel) in ixgbe_identify_qsfp_module_generic()
1949 if (hw->allow_unsupported_sfp) { in ixgbe_identify_qsfp_module_generic()
1953 hw_dbg(hw, "QSFP module not supported\n"); in ixgbe_identify_qsfp_module_generic()
1954 hw->phy.type = ixgbe_phy_sfp_unsupported; in ixgbe_identify_qsfp_module_generic()
1955 return -EOPNOTSUPP; in ixgbe_identify_qsfp_module_generic()
1962 hw->phy.sfp_type = ixgbe_sfp_type_not_present; in ixgbe_identify_qsfp_module_generic()
1963 hw->phy.id = 0; in ixgbe_identify_qsfp_module_generic()
1964 hw->phy.type = ixgbe_phy_unknown; in ixgbe_identify_qsfp_module_generic()
1966 return -ENOENT; in ixgbe_identify_qsfp_module_generic()
1970 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1971 * @hw: pointer to hardware structure
1978 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, in ixgbe_get_sfp_init_sequence_offsets() argument
1983 u16 sfp_type = hw->phy.sfp_type; in ixgbe_get_sfp_init_sequence_offsets()
1985 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) in ixgbe_get_sfp_init_sequence_offsets()
1986 return -EOPNOTSUPP; in ixgbe_get_sfp_init_sequence_offsets()
1988 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) in ixgbe_get_sfp_init_sequence_offsets()
1989 return -ENOENT; in ixgbe_get_sfp_init_sequence_offsets()
1991 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && in ixgbe_get_sfp_init_sequence_offsets()
1992 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) in ixgbe_get_sfp_init_sequence_offsets()
1993 return -EOPNOTSUPP; in ixgbe_get_sfp_init_sequence_offsets()
2011 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { in ixgbe_get_sfp_init_sequence_offsets()
2012 hw_err(hw, "eeprom read at %d failed\n", in ixgbe_get_sfp_init_sequence_offsets()
2014 return -EIO; in ixgbe_get_sfp_init_sequence_offsets()
2018 return -EIO; in ixgbe_get_sfp_init_sequence_offsets()
2027 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) in ixgbe_get_sfp_init_sequence_offsets()
2033 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) in ixgbe_get_sfp_init_sequence_offsets()
2036 hw_dbg(hw, "SFP+ module not supported\n"); in ixgbe_get_sfp_init_sequence_offsets()
2037 return -EOPNOTSUPP; in ixgbe_get_sfp_init_sequence_offsets()
2043 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) in ixgbe_get_sfp_init_sequence_offsets()
2049 hw_dbg(hw, "No matching SFP+ module found\n"); in ixgbe_get_sfp_init_sequence_offsets()
2050 return -EOPNOTSUPP; in ixgbe_get_sfp_init_sequence_offsets()
2056 hw_err(hw, "eeprom read at offset %d failed\n", *list_offset); in ixgbe_get_sfp_init_sequence_offsets()
2057 return -EIO; in ixgbe_get_sfp_init_sequence_offsets()
2061 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
2062 * @hw: pointer to hardware structure
2068 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, in ixgbe_read_i2c_eeprom_generic() argument
2071 return hw->phy.ops.read_i2c_byte(hw, byte_offset, in ixgbe_read_i2c_eeprom_generic()
2077 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
2078 * @hw: pointer to hardware structure
2079 * @byte_offset: byte offset at address 0xA2
2082 * Performs byte read operation to SFP module's SFF-8472 data over I2C
2084 s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, in ixgbe_read_i2c_sff8472_generic() argument
2087 return hw->phy.ops.read_i2c_byte(hw, byte_offset, in ixgbe_read_i2c_sff8472_generic()
2093 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
2094 * @hw: pointer to hardware structure
2100 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, in ixgbe_write_i2c_eeprom_generic() argument
2103 return hw->phy.ops.write_i2c_byte(hw, byte_offset, in ixgbe_write_i2c_eeprom_generic()
2109 * ixgbe_is_sfp_probe - Returns true if SFP is being detected
2110 * @hw: pointer to hardware structure
2112 * @addr: I2C address to be read
2114 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr) in ixgbe_is_sfp_probe() argument
2118 hw->phy.sfp_type == ixgbe_sfp_type_not_present) in ixgbe_is_sfp_probe()
2124 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
2125 * @hw: pointer to hardware structure
2127 * @dev_addr: device address
2132 * a specified device address.
2134 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, in ixgbe_read_i2c_byte_generic_int() argument
2140 u32 swfw_mask = hw->phy.phy_semaphore_mask; in ixgbe_read_i2c_byte_generic_int()
2143 if (hw->mac.type >= ixgbe_mac_X550) in ixgbe_read_i2c_byte_generic_int()
2145 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr)) in ixgbe_read_i2c_byte_generic_int()
2151 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) in ixgbe_read_i2c_byte_generic_int()
2152 return -EBUSY; in ixgbe_read_i2c_byte_generic_int()
2154 ixgbe_i2c_start(hw); in ixgbe_read_i2c_byte_generic_int()
2156 /* Device Address and write indication */ in ixgbe_read_i2c_byte_generic_int()
2157 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); in ixgbe_read_i2c_byte_generic_int()
2161 status = ixgbe_get_i2c_ack(hw); in ixgbe_read_i2c_byte_generic_int()
2165 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); in ixgbe_read_i2c_byte_generic_int()
2169 status = ixgbe_get_i2c_ack(hw); in ixgbe_read_i2c_byte_generic_int()
2173 ixgbe_i2c_start(hw); in ixgbe_read_i2c_byte_generic_int()
2175 /* Device Address and read indication */ in ixgbe_read_i2c_byte_generic_int()
2176 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); in ixgbe_read_i2c_byte_generic_int()
2180 status = ixgbe_get_i2c_ack(hw); in ixgbe_read_i2c_byte_generic_int()
2184 status = ixgbe_clock_in_i2c_byte(hw, data); in ixgbe_read_i2c_byte_generic_int()
2188 status = ixgbe_clock_out_i2c_bit(hw, nack); in ixgbe_read_i2c_byte_generic_int()
2192 ixgbe_i2c_stop(hw); in ixgbe_read_i2c_byte_generic_int()
2194 hw->mac.ops.release_swfw_sync(hw, swfw_mask); in ixgbe_read_i2c_byte_generic_int()
2198 ixgbe_i2c_bus_clear(hw); in ixgbe_read_i2c_byte_generic_int()
2200 hw->mac.ops.release_swfw_sync(hw, swfw_mask); in ixgbe_read_i2c_byte_generic_int()
2205 hw_dbg(hw, "I2C byte read error - Retrying.\n"); in ixgbe_read_i2c_byte_generic_int()
2207 hw_dbg(hw, "I2C byte read error.\n"); in ixgbe_read_i2c_byte_generic_int()
2215 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2216 * @hw: pointer to hardware structure
2218 * @dev_addr: device address
2222 * a specified device address.
2224 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, in ixgbe_read_i2c_byte_generic() argument
2227 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, in ixgbe_read_i2c_byte_generic()
2232 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2233 * @hw: pointer to hardware structure
2235 * @dev_addr: device address
2239 * a specified device address.
2241 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, in ixgbe_read_i2c_byte_generic_unlocked() argument
2244 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, in ixgbe_read_i2c_byte_generic_unlocked()
2249 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2250 * @hw: pointer to hardware structure
2252 * @dev_addr: device address
2257 * a specified device address.
2259 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, in ixgbe_write_i2c_byte_generic_int() argument
2265 u32 swfw_mask = hw->phy.phy_semaphore_mask; in ixgbe_write_i2c_byte_generic_int()
2267 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) in ixgbe_write_i2c_byte_generic_int()
2268 return -EBUSY; in ixgbe_write_i2c_byte_generic_int()
2271 ixgbe_i2c_start(hw); in ixgbe_write_i2c_byte_generic_int()
2273 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); in ixgbe_write_i2c_byte_generic_int()
2277 status = ixgbe_get_i2c_ack(hw); in ixgbe_write_i2c_byte_generic_int()
2281 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); in ixgbe_write_i2c_byte_generic_int()
2285 status = ixgbe_get_i2c_ack(hw); in ixgbe_write_i2c_byte_generic_int()
2289 status = ixgbe_clock_out_i2c_byte(hw, data); in ixgbe_write_i2c_byte_generic_int()
2293 status = ixgbe_get_i2c_ack(hw); in ixgbe_write_i2c_byte_generic_int()
2297 ixgbe_i2c_stop(hw); in ixgbe_write_i2c_byte_generic_int()
2299 hw->mac.ops.release_swfw_sync(hw, swfw_mask); in ixgbe_write_i2c_byte_generic_int()
2303 ixgbe_i2c_bus_clear(hw); in ixgbe_write_i2c_byte_generic_int()
2306 hw_dbg(hw, "I2C byte write error - Retrying.\n"); in ixgbe_write_i2c_byte_generic_int()
2308 hw_dbg(hw, "I2C byte write error.\n"); in ixgbe_write_i2c_byte_generic_int()
2312 hw->mac.ops.release_swfw_sync(hw, swfw_mask); in ixgbe_write_i2c_byte_generic_int()
2318 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2319 * @hw: pointer to hardware structure
2321 * @dev_addr: device address
2325 * a specified device address.
2327 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, in ixgbe_write_i2c_byte_generic() argument
2330 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, in ixgbe_write_i2c_byte_generic()
2335 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2336 * @hw: pointer to hardware structure
2338 * @dev_addr: device address
2342 * a specified device address.
2344 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, in ixgbe_write_i2c_byte_generic_unlocked() argument
2347 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, in ixgbe_write_i2c_byte_generic_unlocked()
2352 * ixgbe_i2c_start - Sets I2C start condition
2353 * @hw: pointer to hardware structure
2355 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2356 * Set bit-bang mode on X550 hardware.
2358 static void ixgbe_i2c_start(struct ixgbe_hw *hw) in ixgbe_i2c_start() argument
2360 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); in ixgbe_i2c_start()
2362 i2cctl |= IXGBE_I2C_BB_EN(hw); in ixgbe_i2c_start()
2365 ixgbe_set_i2c_data(hw, &i2cctl, 1); in ixgbe_i2c_start()
2366 ixgbe_raise_i2c_clk(hw, &i2cctl); in ixgbe_i2c_start()
2371 ixgbe_set_i2c_data(hw, &i2cctl, 0); in ixgbe_i2c_start()
2376 ixgbe_lower_i2c_clk(hw, &i2cctl); in ixgbe_i2c_start()
2384 * ixgbe_i2c_stop - Sets I2C stop condition
2385 * @hw: pointer to hardware structure
2387 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2388 * Disables bit-bang mode and negates data output enable on X550
2391 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) in ixgbe_i2c_stop() argument
2393 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); in ixgbe_i2c_stop()
2394 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw); in ixgbe_i2c_stop()
2395 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw); in ixgbe_i2c_stop()
2396 u32 bb_en_bit = IXGBE_I2C_BB_EN(hw); in ixgbe_i2c_stop()
2399 ixgbe_set_i2c_data(hw, &i2cctl, 0); in ixgbe_i2c_stop()
2400 ixgbe_raise_i2c_clk(hw, &i2cctl); in ixgbe_i2c_stop()
2405 ixgbe_set_i2c_data(hw, &i2cctl, 1); in ixgbe_i2c_stop()
2413 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl); in ixgbe_i2c_stop()
2414 IXGBE_WRITE_FLUSH(hw); in ixgbe_i2c_stop()
2419 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2420 * @hw: pointer to hardware structure
2425 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) in ixgbe_clock_in_i2c_byte() argument
2431 for (i = 7; i >= 0; i--) { in ixgbe_clock_in_i2c_byte()
2432 ixgbe_clock_in_i2c_bit(hw, &bit); in ixgbe_clock_in_i2c_byte()
2440 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2441 * @hw: pointer to hardware structure
2446 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) in ixgbe_clock_out_i2c_byte() argument
2453 for (i = 7; i >= 0; i--) { in ixgbe_clock_out_i2c_byte()
2455 status = ixgbe_clock_out_i2c_bit(hw, bit); in ixgbe_clock_out_i2c_byte()
2462 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); in ixgbe_clock_out_i2c_byte()
2463 i2cctl |= IXGBE_I2C_DATA_OUT(hw); in ixgbe_clock_out_i2c_byte()
2464 i2cctl |= IXGBE_I2C_DATA_OE_N_EN(hw); in ixgbe_clock_out_i2c_byte()
2465 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl); in ixgbe_clock_out_i2c_byte()
2466 IXGBE_WRITE_FLUSH(hw); in ixgbe_clock_out_i2c_byte()
2472 * ixgbe_get_i2c_ack - Polls for I2C ACK
2473 * @hw: pointer to hardware structure
2477 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) in ixgbe_get_i2c_ack() argument
2479 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw); in ixgbe_get_i2c_ack()
2482 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); in ixgbe_get_i2c_ack()
2487 i2cctl |= IXGBE_I2C_DATA_OUT(hw); in ixgbe_get_i2c_ack()
2489 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl); in ixgbe_get_i2c_ack()
2490 IXGBE_WRITE_FLUSH(hw); in ixgbe_get_i2c_ack()
2492 ixgbe_raise_i2c_clk(hw, &i2cctl); in ixgbe_get_i2c_ack()
2500 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); in ixgbe_get_i2c_ack()
2501 ack = ixgbe_get_i2c_data(hw, &i2cctl); in ixgbe_get_i2c_ack()
2509 hw_dbg(hw, "I2C ack was not received.\n"); in ixgbe_get_i2c_ack()
2510 status = -EIO; in ixgbe_get_i2c_ack()
2513 ixgbe_lower_i2c_clk(hw, &i2cctl); in ixgbe_get_i2c_ack()
2522 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2523 * @hw: pointer to hardware structure
2528 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) in ixgbe_clock_in_i2c_bit() argument
2530 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); in ixgbe_clock_in_i2c_bit()
2531 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw); in ixgbe_clock_in_i2c_bit()
2534 i2cctl |= IXGBE_I2C_DATA_OUT(hw); in ixgbe_clock_in_i2c_bit()
2536 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl); in ixgbe_clock_in_i2c_bit()
2537 IXGBE_WRITE_FLUSH(hw); in ixgbe_clock_in_i2c_bit()
2539 ixgbe_raise_i2c_clk(hw, &i2cctl); in ixgbe_clock_in_i2c_bit()
2544 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); in ixgbe_clock_in_i2c_bit()
2545 *data = ixgbe_get_i2c_data(hw, &i2cctl); in ixgbe_clock_in_i2c_bit()
2547 ixgbe_lower_i2c_clk(hw, &i2cctl); in ixgbe_clock_in_i2c_bit()
2556 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2557 * @hw: pointer to hardware structure
2562 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) in ixgbe_clock_out_i2c_bit() argument
2565 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); in ixgbe_clock_out_i2c_bit()
2567 status = ixgbe_set_i2c_data(hw, &i2cctl, data); in ixgbe_clock_out_i2c_bit()
2569 ixgbe_raise_i2c_clk(hw, &i2cctl); in ixgbe_clock_out_i2c_bit()
2574 ixgbe_lower_i2c_clk(hw, &i2cctl); in ixgbe_clock_out_i2c_bit()
2581 hw_dbg(hw, "I2C data was not set to %X\n", data); in ixgbe_clock_out_i2c_bit()
2582 return -EIO; in ixgbe_clock_out_i2c_bit()
2588 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2589 * @hw: pointer to hardware structure
2592 * Raises the I2C clock line '0'->'1'
2595 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) in ixgbe_raise_i2c_clk() argument
2597 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw); in ixgbe_raise_i2c_clk()
2604 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); in ixgbe_raise_i2c_clk()
2608 *i2cctl |= IXGBE_I2C_CLK_OUT(hw); in ixgbe_raise_i2c_clk()
2609 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); in ixgbe_raise_i2c_clk()
2610 IXGBE_WRITE_FLUSH(hw); in ixgbe_raise_i2c_clk()
2614 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); in ixgbe_raise_i2c_clk()
2615 if (i2cctl_r & IXGBE_I2C_CLK_IN(hw)) in ixgbe_raise_i2c_clk()
2621 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2622 * @hw: pointer to hardware structure
2625 * Lowers the I2C clock line '1'->'0'
2628 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) in ixgbe_lower_i2c_clk() argument
2631 *i2cctl &= ~IXGBE_I2C_CLK_OUT(hw); in ixgbe_lower_i2c_clk()
2632 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN(hw); in ixgbe_lower_i2c_clk()
2634 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); in ixgbe_lower_i2c_clk()
2635 IXGBE_WRITE_FLUSH(hw); in ixgbe_lower_i2c_clk()
2642 * ixgbe_set_i2c_data - Sets the I2C data bit
2643 * @hw: pointer to hardware structure
2650 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) in ixgbe_set_i2c_data() argument
2652 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw); in ixgbe_set_i2c_data()
2655 *i2cctl |= IXGBE_I2C_DATA_OUT(hw); in ixgbe_set_i2c_data()
2657 *i2cctl &= ~IXGBE_I2C_DATA_OUT(hw); in ixgbe_set_i2c_data()
2660 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); in ixgbe_set_i2c_data()
2661 IXGBE_WRITE_FLUSH(hw); in ixgbe_set_i2c_data()
2663 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ in ixgbe_set_i2c_data()
2670 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); in ixgbe_set_i2c_data()
2671 IXGBE_WRITE_FLUSH(hw); in ixgbe_set_i2c_data()
2675 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); in ixgbe_set_i2c_data()
2676 if (data != ixgbe_get_i2c_data(hw, i2cctl)) { in ixgbe_set_i2c_data()
2677 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data); in ixgbe_set_i2c_data()
2678 return -EIO; in ixgbe_set_i2c_data()
2685 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2686 * @hw: pointer to hardware structure
2692 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl) in ixgbe_get_i2c_data() argument
2694 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw); in ixgbe_get_i2c_data()
2698 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); in ixgbe_get_i2c_data()
2699 IXGBE_WRITE_FLUSH(hw); in ixgbe_get_i2c_data()
2703 if (*i2cctl & IXGBE_I2C_DATA_IN(hw)) in ixgbe_get_i2c_data()
2709 * ixgbe_i2c_bus_clear - Clears the I2C bus
2710 * @hw: pointer to hardware structure
2715 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) in ixgbe_i2c_bus_clear() argument
2720 ixgbe_i2c_start(hw); in ixgbe_i2c_bus_clear()
2721 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); in ixgbe_i2c_bus_clear()
2723 ixgbe_set_i2c_data(hw, &i2cctl, 1); in ixgbe_i2c_bus_clear()
2726 ixgbe_raise_i2c_clk(hw, &i2cctl); in ixgbe_i2c_bus_clear()
2731 ixgbe_lower_i2c_clk(hw, &i2cctl); in ixgbe_i2c_bus_clear()
2737 ixgbe_i2c_start(hw); in ixgbe_i2c_bus_clear()
2740 ixgbe_i2c_stop(hw); in ixgbe_i2c_bus_clear()
2744 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2745 * @hw: pointer to hardware structure
2751 bool ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) in ixgbe_tn_check_overtemp() argument
2756 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) in ixgbe_tn_check_overtemp()
2760 status = hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, in ixgbe_tn_check_overtemp()
2768 /** ixgbe_set_copper_phy_power - Control power for copper phy
2769 * @hw: pointer to hardware structure
2772 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on) in ixgbe_set_copper_phy_power() argument
2778 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) in ixgbe_set_copper_phy_power()
2781 if (!on && ixgbe_mng_present(hw)) in ixgbe_set_copper_phy_power()
2784 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, ®); in ixgbe_set_copper_phy_power()
2791 if (ixgbe_check_reset_blocked(hw)) in ixgbe_set_copper_phy_power()
2796 status = hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, reg); in ixgbe_set_copper_phy_power()