Lines Matching +full:hw +full:- +full:flow +full:- +full:ctrl
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
19 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
20 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
21 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
24 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
27 static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw);
28 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
30 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
33 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
36 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
37 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
39 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
41 static s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw);
42 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
44 bool ixgbe_mng_enabled(struct ixgbe_hw *hw) in ixgbe_mng_enabled() argument
48 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); in ixgbe_mng_enabled()
52 manc = IXGBE_READ_REG(hw, IXGBE_MANC); in ixgbe_mng_enabled()
56 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw)); in ixgbe_mng_enabled()
63 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) in ixgbe_init_mac_link_ops_82599() argument
65 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_init_mac_link_ops_82599()
70 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) && in ixgbe_init_mac_link_ops_82599()
71 !ixgbe_mng_enabled(hw)) { in ixgbe_init_mac_link_ops_82599()
72 mac->ops.disable_tx_laser = in ixgbe_init_mac_link_ops_82599()
74 mac->ops.enable_tx_laser = in ixgbe_init_mac_link_ops_82599()
76 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber; in ixgbe_init_mac_link_ops_82599()
78 mac->ops.disable_tx_laser = NULL; in ixgbe_init_mac_link_ops_82599()
79 mac->ops.enable_tx_laser = NULL; in ixgbe_init_mac_link_ops_82599()
80 mac->ops.flap_tx_laser = NULL; in ixgbe_init_mac_link_ops_82599()
83 if (hw->phy.multispeed_fiber) { in ixgbe_init_mac_link_ops_82599()
85 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber; in ixgbe_init_mac_link_ops_82599()
86 mac->ops.setup_mac_link = ixgbe_setup_mac_link_82599; in ixgbe_init_mac_link_ops_82599()
87 mac->ops.set_rate_select_speed = in ixgbe_init_mac_link_ops_82599()
90 if ((mac->ops.get_media_type(hw) == in ixgbe_init_mac_link_ops_82599()
92 (hw->phy.smart_speed == ixgbe_smart_speed_auto || in ixgbe_init_mac_link_ops_82599()
93 hw->phy.smart_speed == ixgbe_smart_speed_on) && in ixgbe_init_mac_link_ops_82599()
94 !ixgbe_verify_lesm_fw_enabled_82599(hw)) in ixgbe_init_mac_link_ops_82599()
95 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed; in ixgbe_init_mac_link_ops_82599()
97 mac->ops.setup_link = &ixgbe_setup_mac_link_82599; in ixgbe_init_mac_link_ops_82599()
101 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) in ixgbe_setup_sfp_modules_82599() argument
106 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { in ixgbe_setup_sfp_modules_82599()
107 ixgbe_init_mac_link_ops_82599(hw); in ixgbe_setup_sfp_modules_82599()
109 hw->phy.ops.reset = NULL; in ixgbe_setup_sfp_modules_82599()
111 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, in ixgbe_setup_sfp_modules_82599()
117 ret_val = hw->mac.ops.acquire_swfw_sync(hw, in ixgbe_setup_sfp_modules_82599()
120 return -EBUSY; in ixgbe_setup_sfp_modules_82599()
122 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) in ixgbe_setup_sfp_modules_82599()
125 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value); in ixgbe_setup_sfp_modules_82599()
126 IXGBE_WRITE_FLUSH(hw); in ixgbe_setup_sfp_modules_82599()
127 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) in ixgbe_setup_sfp_modules_82599()
132 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); in ixgbe_setup_sfp_modules_82599()
137 usleep_range(hw->eeprom.semaphore_delay * 1000, in ixgbe_setup_sfp_modules_82599()
138 hw->eeprom.semaphore_delay * 2000); in ixgbe_setup_sfp_modules_82599()
141 ret_val = hw->mac.ops.prot_autoc_write(hw, in ixgbe_setup_sfp_modules_82599()
142 hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL, in ixgbe_setup_sfp_modules_82599()
146 hw_dbg(hw, " sfp module setup not complete\n"); in ixgbe_setup_sfp_modules_82599()
147 return -EIO; in ixgbe_setup_sfp_modules_82599()
155 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); in ixgbe_setup_sfp_modules_82599()
159 usleep_range(hw->eeprom.semaphore_delay * 1000, in ixgbe_setup_sfp_modules_82599()
160 hw->eeprom.semaphore_delay * 2000); in ixgbe_setup_sfp_modules_82599()
161 hw_err(hw, "eeprom read at offset %d failed\n", data_offset); in ixgbe_setup_sfp_modules_82599()
162 return -EIO; in ixgbe_setup_sfp_modules_82599()
166 * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read
167 * @hw: pointer to hardware structure
171 * For this part (82599) we need to wrap read-modify-writes with a possible
176 static s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, in prot_autoc_read_82599() argument
183 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { in prot_autoc_read_82599()
184 ret_val = hw->mac.ops.acquire_swfw_sync(hw, in prot_autoc_read_82599()
187 return -EBUSY; in prot_autoc_read_82599()
192 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); in prot_autoc_read_82599()
197 * prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write
198 * @hw: pointer to hardware structure
206 static s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked) in prot_autoc_write_82599() argument
211 if (ixgbe_check_reset_blocked(hw)) in prot_autoc_write_82599()
215 * - We didn't do it already (in the read part of a read-modify-write) in prot_autoc_write_82599()
216 * - LESM is enabled. in prot_autoc_write_82599()
218 if (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) { in prot_autoc_write_82599()
219 ret_val = hw->mac.ops.acquire_swfw_sync(hw, in prot_autoc_write_82599()
222 return -EBUSY; in prot_autoc_write_82599()
227 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); in prot_autoc_write_82599()
228 ret_val = ixgbe_reset_pipeline_82599(hw); in prot_autoc_write_82599()
235 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); in prot_autoc_write_82599()
240 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw) in ixgbe_get_invariants_82599() argument
242 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_get_invariants_82599()
244 ixgbe_init_mac_link_ops_82599(hw); in ixgbe_get_invariants_82599()
246 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE; in ixgbe_get_invariants_82599()
247 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE; in ixgbe_get_invariants_82599()
248 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES; in ixgbe_get_invariants_82599()
249 mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE; in ixgbe_get_invariants_82599()
250 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES; in ixgbe_get_invariants_82599()
251 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES; in ixgbe_get_invariants_82599()
252 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); in ixgbe_get_invariants_82599()
258 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
259 * @hw: pointer to hardware structure
266 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) in ixgbe_init_phy_ops_82599() argument
268 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_init_phy_ops_82599()
269 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_init_phy_ops_82599()
273 if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) { in ixgbe_init_phy_ops_82599()
275 hw->phy.qsfp_shared_i2c_bus = true; in ixgbe_init_phy_ops_82599()
278 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); in ixgbe_init_phy_ops_82599()
284 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); in ixgbe_init_phy_ops_82599()
285 IXGBE_WRITE_FLUSH(hw); in ixgbe_init_phy_ops_82599()
287 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_82599; in ixgbe_init_phy_ops_82599()
288 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_82599; in ixgbe_init_phy_ops_82599()
292 ret_val = phy->ops.identify(hw); in ixgbe_init_phy_ops_82599()
295 ixgbe_init_mac_link_ops_82599(hw); in ixgbe_init_phy_ops_82599()
298 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { in ixgbe_init_phy_ops_82599()
299 mac->ops.setup_link = &ixgbe_setup_copper_link_82599; in ixgbe_init_phy_ops_82599()
300 mac->ops.get_link_capabilities = in ixgbe_init_phy_ops_82599()
305 switch (hw->phy.type) { in ixgbe_init_phy_ops_82599()
307 phy->ops.check_link = &ixgbe_check_phy_link_tnx; in ixgbe_init_phy_ops_82599()
308 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; in ixgbe_init_phy_ops_82599()
318 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
319 * @hw: pointer to hardware structure
325 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, in ixgbe_get_link_capabilities_82599() argument
332 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || in ixgbe_get_link_capabilities_82599()
333 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || in ixgbe_get_link_capabilities_82599()
334 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || in ixgbe_get_link_capabilities_82599()
335 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || in ixgbe_get_link_capabilities_82599()
336 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || in ixgbe_get_link_capabilities_82599()
337 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) { in ixgbe_get_link_capabilities_82599()
348 if (hw->mac.orig_link_settings_stored) in ixgbe_get_link_capabilities_82599()
349 autoc = hw->mac.orig_autoc; in ixgbe_get_link_capabilities_82599()
351 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); in ixgbe_get_link_capabilities_82599()
403 return -EIO; in ixgbe_get_link_capabilities_82599()
406 if (hw->phy.multispeed_fiber) { in ixgbe_get_link_capabilities_82599()
410 /* QSFP must not enable auto-negotiation */ in ixgbe_get_link_capabilities_82599()
411 if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp) in ixgbe_get_link_capabilities_82599()
421 * ixgbe_get_media_type_82599 - Get media type
422 * @hw: pointer to hardware structure
426 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw) in ixgbe_get_media_type_82599() argument
429 switch (hw->phy.type) { in ixgbe_get_media_type_82599()
438 switch (hw->device_id) { in ixgbe_get_media_type_82599()
474 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3
475 * @hw: pointer to hardware structure
480 static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw) in ixgbe_stop_mac_link_on_d3_82599() argument
485 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2); in ixgbe_stop_mac_link_on_d3_82599()
487 if (!ixgbe_mng_present(hw) && !hw->wol_enabled && in ixgbe_stop_mac_link_on_d3_82599()
489 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); in ixgbe_stop_mac_link_on_d3_82599()
491 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); in ixgbe_stop_mac_link_on_d3_82599()
496 * ixgbe_start_mac_link_82599 - Setup MAC link settings
497 * @hw: pointer to hardware structure
503 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, in ixgbe_start_mac_link_82599() argument
512 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { in ixgbe_start_mac_link_82599()
513 status = hw->mac.ops.acquire_swfw_sync(hw, in ixgbe_start_mac_link_82599()
522 ixgbe_reset_pipeline_82599(hw); in ixgbe_start_mac_link_82599()
525 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); in ixgbe_start_mac_link_82599()
529 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); in ixgbe_start_mac_link_82599()
538 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); in ixgbe_start_mac_link_82599()
544 status = -EIO; in ixgbe_start_mac_link_82599()
545 hw_dbg(hw, "Autoneg did not complete.\n"); in ixgbe_start_mac_link_82599()
557 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
558 * @hw: pointer to hardware structure
564 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) in ixgbe_disable_tx_laser_multispeed_fiber() argument
566 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); in ixgbe_disable_tx_laser_multispeed_fiber()
569 if (ixgbe_check_reset_blocked(hw)) in ixgbe_disable_tx_laser_multispeed_fiber()
574 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); in ixgbe_disable_tx_laser_multispeed_fiber()
575 IXGBE_WRITE_FLUSH(hw); in ixgbe_disable_tx_laser_multispeed_fiber()
580 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
581 * @hw: pointer to hardware structure
587 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) in ixgbe_enable_tx_laser_multispeed_fiber() argument
589 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); in ixgbe_enable_tx_laser_multispeed_fiber()
593 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); in ixgbe_enable_tx_laser_multispeed_fiber()
594 IXGBE_WRITE_FLUSH(hw); in ixgbe_enable_tx_laser_multispeed_fiber()
599 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
600 * @hw: pointer to hardware structure
605 * so, we set the speed then disable and re-enable the tx laser, to
610 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) in ixgbe_flap_tx_laser_multispeed_fiber() argument
613 if (ixgbe_check_reset_blocked(hw)) in ixgbe_flap_tx_laser_multispeed_fiber()
616 if (hw->mac.autotry_restart) { in ixgbe_flap_tx_laser_multispeed_fiber()
617 ixgbe_disable_tx_laser_multispeed_fiber(hw); in ixgbe_flap_tx_laser_multispeed_fiber()
618 ixgbe_enable_tx_laser_multispeed_fiber(hw); in ixgbe_flap_tx_laser_multispeed_fiber()
619 hw->mac.autotry_restart = false; in ixgbe_flap_tx_laser_multispeed_fiber()
624 * ixgbe_set_hard_rate_select_speed - Set module link speed
625 * @hw: pointer to hardware structure
631 ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed) in ixgbe_set_hard_rate_select_speed() argument
633 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); in ixgbe_set_hard_rate_select_speed()
644 hw_dbg(hw, "Invalid fixed module speed\n"); in ixgbe_set_hard_rate_select_speed()
648 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); in ixgbe_set_hard_rate_select_speed()
649 IXGBE_WRITE_FLUSH(hw); in ixgbe_set_hard_rate_select_speed()
653 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
654 * @hw: pointer to hardware structure
660 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, in ixgbe_setup_mac_link_smartspeed() argument
668 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); in ixgbe_setup_mac_link_smartspeed()
671 hw->phy.autoneg_advertised = 0; in ixgbe_setup_mac_link_smartspeed()
674 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; in ixgbe_setup_mac_link_smartspeed()
677 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; in ixgbe_setup_mac_link_smartspeed()
680 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; in ixgbe_setup_mac_link_smartspeed()
690 hw->phy.smart_speed_active = false; in ixgbe_setup_mac_link_smartspeed()
692 status = ixgbe_setup_mac_link_82599(hw, speed, in ixgbe_setup_mac_link_smartspeed()
707 status = hw->mac.ops.check_link(hw, &link_speed, in ixgbe_setup_mac_link_smartspeed()
726 hw->phy.smart_speed_active = true; in ixgbe_setup_mac_link_smartspeed()
727 status = ixgbe_setup_mac_link_82599(hw, speed, in ixgbe_setup_mac_link_smartspeed()
736 * connect attempts as defined in the AN MAS table 73-7. in ixgbe_setup_mac_link_smartspeed()
742 status = hw->mac.ops.check_link(hw, &link_speed, in ixgbe_setup_mac_link_smartspeed()
752 hw->phy.smart_speed_active = false; in ixgbe_setup_mac_link_smartspeed()
753 status = ixgbe_setup_mac_link_82599(hw, speed, in ixgbe_setup_mac_link_smartspeed()
758 hw_dbg(hw, "Smartspeed has downgraded the link speed from the maximum advertised\n"); in ixgbe_setup_mac_link_smartspeed()
763 * ixgbe_setup_mac_link_82599 - Set MAC link speed
764 * @hw: pointer to hardware structure
770 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, in ixgbe_setup_mac_link_82599() argument
777 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); in ixgbe_setup_mac_link_82599()
782 u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); in ixgbe_setup_mac_link_82599()
789 status = hw->mac.ops.get_link_capabilities(hw, &link_capabilities, in ixgbe_setup_mac_link_82599()
797 return -EINVAL; in ixgbe_setup_mac_link_82599()
800 if (hw->mac.orig_link_settings_stored) in ixgbe_setup_mac_link_82599()
801 orig_autoc = hw->mac.orig_autoc; in ixgbe_setup_mac_link_82599()
817 (hw->phy.smart_speed_active == false)) in ixgbe_setup_mac_link_82599()
846 status = hw->mac.ops.prot_autoc_write(hw, autoc, false); in ixgbe_setup_mac_link_82599()
858 IXGBE_READ_REG(hw, IXGBE_LINKS); in ixgbe_setup_mac_link_82599()
864 status = -EIO; in ixgbe_setup_mac_link_82599()
865 hw_dbg(hw, "Autoneg did not complete.\n"); in ixgbe_setup_mac_link_82599()
878 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
879 * @hw: pointer to hardware structure
885 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, in ixgbe_setup_copper_link_82599() argument
892 status = hw->phy.ops.setup_link_speed(hw, speed, in ixgbe_setup_copper_link_82599()
895 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete); in ixgbe_setup_copper_link_82599()
901 * ixgbe_reset_hw_82599 - Perform hardware reset
902 * @hw: pointer to hardware structure
908 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw) in ixgbe_reset_hw_82599() argument
912 u32 ctrl, i, autoc, autoc2; in ixgbe_reset_hw_82599() local
917 status = hw->mac.ops.stop_adapter(hw); in ixgbe_reset_hw_82599()
922 ixgbe_clear_tx_pending(hw); in ixgbe_reset_hw_82599()
927 status = hw->phy.ops.init(hw); in ixgbe_reset_hw_82599()
929 if (status == -EOPNOTSUPP) in ixgbe_reset_hw_82599()
933 if (hw->phy.sfp_setup_needed) { in ixgbe_reset_hw_82599()
934 status = hw->mac.ops.setup_sfp(hw); in ixgbe_reset_hw_82599()
935 hw->phy.sfp_setup_needed = false; in ixgbe_reset_hw_82599()
938 if (status == -EOPNOTSUPP) in ixgbe_reset_hw_82599()
942 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL) in ixgbe_reset_hw_82599()
943 hw->phy.ops.reset(hw); in ixgbe_reset_hw_82599()
946 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK; in ixgbe_reset_hw_82599()
955 ctrl = IXGBE_CTRL_LNK_RST; in ixgbe_reset_hw_82599()
956 if (!hw->force_full_reset) { in ixgbe_reset_hw_82599()
957 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); in ixgbe_reset_hw_82599()
959 ctrl = IXGBE_CTRL_RST; in ixgbe_reset_hw_82599()
962 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); in ixgbe_reset_hw_82599()
963 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); in ixgbe_reset_hw_82599()
964 IXGBE_WRITE_FLUSH(hw); in ixgbe_reset_hw_82599()
967 /* Poll for reset bit to self-clear indicating reset is complete */ in ixgbe_reset_hw_82599()
969 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); in ixgbe_reset_hw_82599()
970 if (!(ctrl & IXGBE_CTRL_RST_MASK)) in ixgbe_reset_hw_82599()
975 if (ctrl & IXGBE_CTRL_RST_MASK) { in ixgbe_reset_hw_82599()
976 status = -EIO; in ixgbe_reset_hw_82599()
977 hw_dbg(hw, "Reset polling failed to complete.\n"); in ixgbe_reset_hw_82599()
985 * for any pending HW events to complete. in ixgbe_reset_hw_82599()
987 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { in ixgbe_reset_hw_82599()
988 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; in ixgbe_reset_hw_82599()
997 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); in ixgbe_reset_hw_82599()
998 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); in ixgbe_reset_hw_82599()
1003 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); in ixgbe_reset_hw_82599()
1004 IXGBE_WRITE_FLUSH(hw); in ixgbe_reset_hw_82599()
1007 if (hw->mac.orig_link_settings_stored == false) { in ixgbe_reset_hw_82599()
1008 hw->mac.orig_autoc = autoc; in ixgbe_reset_hw_82599()
1009 hw->mac.orig_autoc2 = autoc2; in ixgbe_reset_hw_82599()
1010 hw->mac.orig_link_settings_stored = true; in ixgbe_reset_hw_82599()
1013 /* If MNG FW is running on a multi-speed device that in ixgbe_reset_hw_82599()
1019 if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) || in ixgbe_reset_hw_82599()
1020 hw->wol_enabled) in ixgbe_reset_hw_82599()
1021 hw->mac.orig_autoc = in ixgbe_reset_hw_82599()
1022 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) | in ixgbe_reset_hw_82599()
1025 if (autoc != hw->mac.orig_autoc) { in ixgbe_reset_hw_82599()
1026 status = hw->mac.ops.prot_autoc_write(hw, in ixgbe_reset_hw_82599()
1027 hw->mac.orig_autoc, in ixgbe_reset_hw_82599()
1034 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { in ixgbe_reset_hw_82599()
1036 autoc2 |= (hw->mac.orig_autoc2 & in ixgbe_reset_hw_82599()
1038 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); in ixgbe_reset_hw_82599()
1043 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); in ixgbe_reset_hw_82599()
1050 hw->mac.num_rar_entries = IXGBE_82599_RAR_ENTRIES; in ixgbe_reset_hw_82599()
1051 hw->mac.ops.init_rx_addrs(hw); in ixgbe_reset_hw_82599()
1054 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); in ixgbe_reset_hw_82599()
1057 if (is_valid_ether_addr(hw->mac.san_addr)) { in ixgbe_reset_hw_82599()
1059 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; in ixgbe_reset_hw_82599()
1061 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index, in ixgbe_reset_hw_82599()
1062 hw->mac.san_addr, 0, IXGBE_RAH_AV); in ixgbe_reset_hw_82599()
1065 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index, in ixgbe_reset_hw_82599()
1069 hw->mac.num_rar_entries--; in ixgbe_reset_hw_82599()
1073 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, in ixgbe_reset_hw_82599()
1074 &hw->mac.wwpn_prefix); in ixgbe_reset_hw_82599()
1080 * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete
1081 * @hw: pointer to hardware structure
1084 static s32 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, u32 *fdircmd) in ixgbe_fdir_check_cmd_complete() argument
1089 *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD); in ixgbe_fdir_check_cmd_complete()
1095 return -EIO; in ixgbe_fdir_check_cmd_complete()
1099 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1100 * @hw: pointer to hardware structure
1102 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) in ixgbe_reinit_fdir_tables_82599() argument
1105 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); in ixgbe_reinit_fdir_tables_82599()
1115 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); in ixgbe_reinit_fdir_tables_82599()
1117 …hw_dbg(hw, "Flow Director previous command did not complete, aborting table re-initialization.\n"); in ixgbe_reinit_fdir_tables_82599()
1121 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0); in ixgbe_reinit_fdir_tables_82599()
1122 IXGBE_WRITE_FLUSH(hw); in ixgbe_reinit_fdir_tables_82599()
1124 * 82599 adapters flow director init flow cannot be restarted, in ixgbe_reinit_fdir_tables_82599()
1126 * before re-writing the FDIRCTRL control register with the same value. in ixgbe_reinit_fdir_tables_82599()
1127 * - write 1 to bit 8 of FDIRCMD register & in ixgbe_reinit_fdir_tables_82599()
1128 * - write 0 to bit 8 of FDIRCMD register in ixgbe_reinit_fdir_tables_82599()
1130 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, in ixgbe_reinit_fdir_tables_82599()
1131 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | in ixgbe_reinit_fdir_tables_82599()
1133 IXGBE_WRITE_FLUSH(hw); in ixgbe_reinit_fdir_tables_82599()
1134 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, in ixgbe_reinit_fdir_tables_82599()
1135 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & in ixgbe_reinit_fdir_tables_82599()
1137 IXGBE_WRITE_FLUSH(hw); in ixgbe_reinit_fdir_tables_82599()
1142 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00); in ixgbe_reinit_fdir_tables_82599()
1143 IXGBE_WRITE_FLUSH(hw); in ixgbe_reinit_fdir_tables_82599()
1145 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); in ixgbe_reinit_fdir_tables_82599()
1146 IXGBE_WRITE_FLUSH(hw); in ixgbe_reinit_fdir_tables_82599()
1148 /* Poll init-done after we write FDIRCTRL register */ in ixgbe_reinit_fdir_tables_82599()
1150 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & in ixgbe_reinit_fdir_tables_82599()
1156 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n"); in ixgbe_reinit_fdir_tables_82599()
1157 return -EIO; in ixgbe_reinit_fdir_tables_82599()
1161 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT); in ixgbe_reinit_fdir_tables_82599()
1162 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT); in ixgbe_reinit_fdir_tables_82599()
1163 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); in ixgbe_reinit_fdir_tables_82599()
1164 IXGBE_READ_REG(hw, IXGBE_FDIRMISS); in ixgbe_reinit_fdir_tables_82599()
1165 IXGBE_READ_REG(hw, IXGBE_FDIRLEN); in ixgbe_reinit_fdir_tables_82599()
1171 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1172 * @hw: pointer to hardware structure
1173 * @fdirctrl: value to write to flow director control register
1175 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl) in ixgbe_fdir_enable_82599() argument
1180 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY); in ixgbe_fdir_enable_82599()
1181 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY); in ixgbe_fdir_enable_82599()
1184 * Poll init-done after we write the register. Estimated times: in ixgbe_fdir_enable_82599()
1196 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); in ixgbe_fdir_enable_82599()
1197 IXGBE_WRITE_FLUSH(hw); in ixgbe_fdir_enable_82599()
1199 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & in ixgbe_fdir_enable_82599()
1206 hw_dbg(hw, "Flow Director poll time exceeded!\n"); in ixgbe_fdir_enable_82599()
1210 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1211 * @hw: pointer to hardware structure
1212 * @fdirctrl: value to write to flow director control register, initially
1215 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl) in ixgbe_init_fdir_signature_82599() argument
1219 * Move the flexible bytes to use the ethertype - shift 6 words in ixgbe_init_fdir_signature_82599()
1228 ixgbe_fdir_enable_82599(hw, fdirctrl); in ixgbe_init_fdir_signature_82599()
1234 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1235 * @hw: pointer to hardware structure
1236 * @fdirctrl: value to write to flow director control register, initially
1239 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl) in ixgbe_init_fdir_perfect_82599() argument
1245 * Move the flexible bytes to use the ethertype - shift 6 words in ixgbe_init_fdir_perfect_82599()
1256 ixgbe_fdir_enable_82599(hw, fdirctrl); in ixgbe_init_fdir_perfect_82599()
1276 sig_hash ^= lo_hash_dword << (16 - n); \
1282 sig_hash ^= hi_hash_dword << (16 - n); \
1286 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1311 /* apply flow ID/VM pool/VLAN ID bits to hash words */ in ixgbe_atr_compute_sig_hash_82599()
1318 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to in ixgbe_atr_compute_sig_hash_82599()
1353 * ixgbe_fdir_add_signature_filter_82599 - Adds a signature hash filter
1354 * @hw: pointer to hardware structure
1362 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, in ixgbe_fdir_add_signature_filter_82599() argument
1378 (IXGBE_ATR_L4TYPE_TUNNEL_MASK - 1); in ixgbe_fdir_add_signature_filter_82599()
1388 hw_dbg(hw, " Error on flow type input\n"); in ixgbe_fdir_add_signature_filter_82599()
1389 return -EIO; in ixgbe_fdir_add_signature_filter_82599()
1401 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits in ixgbe_fdir_add_signature_filter_82599()
1402 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH. in ixgbe_fdir_add_signature_filter_82599()
1406 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd); in ixgbe_fdir_add_signature_filter_82599()
1408 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd); in ixgbe_fdir_add_signature_filter_82599()
1423 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1444 input->dword_stream[i] &= input_mask->dword_stream[i]; in ixgbe_atr_compute_perfect_hash_82599()
1447 flow_vm_vlan = ntohl(input->dword_stream[0]); in ixgbe_atr_compute_perfect_hash_82599()
1451 hi_dword ^= input->dword_stream[i]; in ixgbe_atr_compute_perfect_hash_82599()
1457 /* apply flow ID/VM pool/VLAN ID bits to hash words */ in ixgbe_atr_compute_perfect_hash_82599()
1464 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to in ixgbe_atr_compute_perfect_hash_82599()
1478 input->formatted.bkt_hash = (__force __be16)(bucket_hash & 0x1FFF); in ixgbe_atr_compute_perfect_hash_82599()
1482 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1485 * The source and destination port masks for flow director are bit swapped
1492 u32 mask = ntohs(input_mask->formatted.dst_port); in ixgbe_get_fdirtcpm_82599()
1495 mask |= ntohs(input_mask->formatted.src_port); in ixgbe_get_fdirtcpm_82599()
1504 * that are either all or in part big-endian. As a result on big-endian
1505 * systems we will end up byte swapping the value to little-endian before
1507 * big-endian format.
1518 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, in ixgbe_fdir_set_input_mask_82599() argument
1536 if (input_mask->formatted.bkt_hash) in ixgbe_fdir_set_input_mask_82599()
1537 hw_dbg(hw, " bucket hash should always be 0 in mask\n"); in ixgbe_fdir_set_input_mask_82599()
1540 switch (input_mask->formatted.vm_pool & 0x7F) { in ixgbe_fdir_set_input_mask_82599()
1547 hw_dbg(hw, " Error on vm pool mask\n"); in ixgbe_fdir_set_input_mask_82599()
1548 return -EIO; in ixgbe_fdir_set_input_mask_82599()
1551 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) { in ixgbe_fdir_set_input_mask_82599()
1554 if (input_mask->formatted.dst_port || in ixgbe_fdir_set_input_mask_82599()
1555 input_mask->formatted.src_port) { in ixgbe_fdir_set_input_mask_82599()
1556 hw_dbg(hw, " Error on src/dst port mask\n"); in ixgbe_fdir_set_input_mask_82599()
1557 return -EIO; in ixgbe_fdir_set_input_mask_82599()
1563 hw_dbg(hw, " Error on flow type mask\n"); in ixgbe_fdir_set_input_mask_82599()
1564 return -EIO; in ixgbe_fdir_set_input_mask_82599()
1567 switch (ntohs(input_mask->formatted.vlan_id) & 0xEFFF) { in ixgbe_fdir_set_input_mask_82599()
1584 hw_dbg(hw, " Error on VLAN mask\n"); in ixgbe_fdir_set_input_mask_82599()
1585 return -EIO; in ixgbe_fdir_set_input_mask_82599()
1588 switch ((__force u16)input_mask->formatted.flex_bytes & 0xFFFF) { in ixgbe_fdir_set_input_mask_82599()
1596 hw_dbg(hw, " Error on flexible byte mask\n"); in ixgbe_fdir_set_input_mask_82599()
1597 return -EIO; in ixgbe_fdir_set_input_mask_82599()
1600 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */ in ixgbe_fdir_set_input_mask_82599()
1601 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); in ixgbe_fdir_set_input_mask_82599()
1607 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm); in ixgbe_fdir_set_input_mask_82599()
1608 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm); in ixgbe_fdir_set_input_mask_82599()
1611 switch (hw->mac.type) { in ixgbe_fdir_set_input_mask_82599()
1615 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm); in ixgbe_fdir_set_input_mask_82599()
1621 /* store source and destination IP masks (big-enian) */ in ixgbe_fdir_set_input_mask_82599()
1622 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, in ixgbe_fdir_set_input_mask_82599()
1623 ~input_mask->formatted.src_ip[0]); in ixgbe_fdir_set_input_mask_82599()
1624 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, in ixgbe_fdir_set_input_mask_82599()
1625 ~input_mask->formatted.dst_ip[0]); in ixgbe_fdir_set_input_mask_82599()
1630 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, in ixgbe_fdir_write_perfect_filter_82599() argument
1638 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), in ixgbe_fdir_write_perfect_filter_82599()
1639 input->formatted.src_ip[0]); in ixgbe_fdir_write_perfect_filter_82599()
1640 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), in ixgbe_fdir_write_perfect_filter_82599()
1641 input->formatted.src_ip[1]); in ixgbe_fdir_write_perfect_filter_82599()
1642 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), in ixgbe_fdir_write_perfect_filter_82599()
1643 input->formatted.src_ip[2]); in ixgbe_fdir_write_perfect_filter_82599()
1645 /* record the source address (big-endian) */ in ixgbe_fdir_write_perfect_filter_82599()
1646 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]); in ixgbe_fdir_write_perfect_filter_82599()
1648 /* record the first 32 bits of the destination address (big-endian) */ in ixgbe_fdir_write_perfect_filter_82599()
1649 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]); in ixgbe_fdir_write_perfect_filter_82599()
1651 /* record source and destination port (little-endian)*/ in ixgbe_fdir_write_perfect_filter_82599()
1652 fdirport = be16_to_cpu(input->formatted.dst_port); in ixgbe_fdir_write_perfect_filter_82599()
1654 fdirport |= be16_to_cpu(input->formatted.src_port); in ixgbe_fdir_write_perfect_filter_82599()
1655 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport); in ixgbe_fdir_write_perfect_filter_82599()
1657 /* record vlan (little-endian) and flex_bytes(big-endian) */ in ixgbe_fdir_write_perfect_filter_82599()
1658 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes); in ixgbe_fdir_write_perfect_filter_82599()
1660 fdirvlan |= ntohs(input->formatted.vlan_id); in ixgbe_fdir_write_perfect_filter_82599()
1661 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan); in ixgbe_fdir_write_perfect_filter_82599()
1664 fdirhash = (__force u32)input->formatted.bkt_hash; in ixgbe_fdir_write_perfect_filter_82599()
1666 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); in ixgbe_fdir_write_perfect_filter_82599()
1672 IXGBE_WRITE_FLUSH(hw); in ixgbe_fdir_write_perfect_filter_82599()
1679 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; in ixgbe_fdir_write_perfect_filter_82599()
1681 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT; in ixgbe_fdir_write_perfect_filter_82599()
1683 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); in ixgbe_fdir_write_perfect_filter_82599()
1684 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); in ixgbe_fdir_write_perfect_filter_82599()
1686 hw_dbg(hw, "Flow Director command did not complete!\n"); in ixgbe_fdir_write_perfect_filter_82599()
1693 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, in ixgbe_fdir_erase_perfect_filter_82599() argument
1702 fdirhash = (__force u32)input->formatted.bkt_hash; in ixgbe_fdir_erase_perfect_filter_82599()
1704 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); in ixgbe_fdir_erase_perfect_filter_82599()
1706 /* flush hash to HW */ in ixgbe_fdir_erase_perfect_filter_82599()
1707 IXGBE_WRITE_FLUSH(hw); in ixgbe_fdir_erase_perfect_filter_82599()
1710 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT); in ixgbe_fdir_erase_perfect_filter_82599()
1712 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); in ixgbe_fdir_erase_perfect_filter_82599()
1714 hw_dbg(hw, "Flow Director command did not complete!\n"); in ixgbe_fdir_erase_perfect_filter_82599()
1720 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); in ixgbe_fdir_erase_perfect_filter_82599()
1721 IXGBE_WRITE_FLUSH(hw); in ixgbe_fdir_erase_perfect_filter_82599()
1722 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, in ixgbe_fdir_erase_perfect_filter_82599()
1730 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1731 * @hw: pointer to hardware structure
1737 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val) in ixgbe_read_analog_reg8_82599() argument
1741 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD | in ixgbe_read_analog_reg8_82599()
1743 IXGBE_WRITE_FLUSH(hw); in ixgbe_read_analog_reg8_82599()
1745 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); in ixgbe_read_analog_reg8_82599()
1752 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1753 * @hw: pointer to hardware structure
1759 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val) in ixgbe_write_analog_reg8_82599() argument
1764 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl); in ixgbe_write_analog_reg8_82599()
1765 IXGBE_WRITE_FLUSH(hw); in ixgbe_write_analog_reg8_82599()
1772 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1773 * @hw: pointer to hardware structure
1777 * Then performs revision-specific operations, if any.
1779 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw) in ixgbe_start_hw_82599() argument
1783 ret_val = ixgbe_start_hw_generic(hw); in ixgbe_start_hw_82599()
1787 ret_val = ixgbe_start_hw_gen2(hw); in ixgbe_start_hw_82599()
1792 hw->mac.autotry_restart = true; in ixgbe_start_hw_82599()
1794 return ixgbe_verify_fw_version_82599(hw); in ixgbe_start_hw_82599()
1798 * ixgbe_identify_phy_82599 - Get physical layer module
1799 * @hw: pointer to hardware structure
1802 * If PHY already detected, maintains current PHY type in hw struct,
1805 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw) in ixgbe_identify_phy_82599() argument
1809 /* Detect PHY if not unknown - returns success if already detected. */ in ixgbe_identify_phy_82599()
1810 status = ixgbe_identify_phy_generic(hw); in ixgbe_identify_phy_82599()
1812 /* 82599 10GBASE-T requires an external PHY */ in ixgbe_identify_phy_82599()
1813 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) in ixgbe_identify_phy_82599()
1815 status = ixgbe_identify_module_generic(hw); in ixgbe_identify_phy_82599()
1819 if (hw->phy.type == ixgbe_phy_unknown) { in ixgbe_identify_phy_82599()
1820 hw->phy.type = ixgbe_phy_none; in ixgbe_identify_phy_82599()
1825 if (hw->phy.type == ixgbe_phy_sfp_unsupported) in ixgbe_identify_phy_82599()
1826 return -EOPNOTSUPP; in ixgbe_identify_phy_82599()
1832 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1833 * @hw: pointer to hardware structure
1838 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) in ixgbe_enable_rx_dma_82599() argument
1846 hw->mac.ops.disable_rx_buff(hw); in ixgbe_enable_rx_dma_82599()
1849 hw->mac.ops.enable_rx(hw); in ixgbe_enable_rx_dma_82599()
1851 hw->mac.ops.disable_rx(hw); in ixgbe_enable_rx_dma_82599()
1853 hw->mac.ops.enable_rx_buff(hw); in ixgbe_enable_rx_dma_82599()
1859 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
1860 * @hw: pointer to hardware structure
1865 * Return: -EACCES if the FW is not present or if the FW version is
1868 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) in ixgbe_verify_fw_version_82599() argument
1871 s32 status = -EACCES; in ixgbe_verify_fw_version_82599()
1876 if (hw->phy.media_type != ixgbe_media_type_fiber) in ixgbe_verify_fw_version_82599()
1881 if (hw->eeprom.ops.read(hw, offset, &fw_offset)) in ixgbe_verify_fw_version_82599()
1885 return -EACCES; in ixgbe_verify_fw_version_82599()
1889 if (hw->eeprom.ops.read(hw, offset, &fw_ptp_cfg_offset)) in ixgbe_verify_fw_version_82599()
1893 return -EACCES; in ixgbe_verify_fw_version_82599()
1897 if (hw->eeprom.ops.read(hw, offset, &fw_version)) in ixgbe_verify_fw_version_82599()
1906 hw_err(hw, "eeprom read at offset %d failed\n", offset); in ixgbe_verify_fw_version_82599()
1907 return -EACCES; in ixgbe_verify_fw_version_82599()
1911 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
1912 * @hw: pointer to hardware structure
1917 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw) in ixgbe_verify_lesm_fw_enabled_82599() argument
1923 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); in ixgbe_verify_lesm_fw_enabled_82599()
1929 status = hw->eeprom.ops.read(hw, (fw_offset + in ixgbe_verify_lesm_fw_enabled_82599()
1938 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset + in ixgbe_verify_lesm_fw_enabled_82599()
1949 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
1952 * @hw: pointer to hardware structure
1959 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset, in ixgbe_read_eeprom_buffer_82599() argument
1962 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; in ixgbe_read_eeprom_buffer_82599()
1967 if (eeprom->type == ixgbe_eeprom_spi && in ixgbe_read_eeprom_buffer_82599()
1968 offset + (words - 1) <= IXGBE_EERD_MAX_ADDR) in ixgbe_read_eeprom_buffer_82599()
1969 return ixgbe_read_eerd_buffer_generic(hw, offset, words, data); in ixgbe_read_eeprom_buffer_82599()
1971 return ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset, words, in ixgbe_read_eeprom_buffer_82599()
1976 * ixgbe_read_eeprom_82599 - Read EEPROM word using
1979 * @hw: pointer to hardware structure
1985 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, in ixgbe_read_eeprom_82599() argument
1988 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; in ixgbe_read_eeprom_82599()
1994 if (eeprom->type == ixgbe_eeprom_spi && offset <= IXGBE_EERD_MAX_ADDR) in ixgbe_read_eeprom_82599()
1995 return ixgbe_read_eerd_generic(hw, offset, data); in ixgbe_read_eeprom_82599()
1997 return ixgbe_read_eeprom_bit_bang_generic(hw, offset, data); in ixgbe_read_eeprom_82599()
2001 * ixgbe_reset_pipeline_82599 - perform pipeline reset
2003 * @hw: pointer to hardware structure
2006 * full pipeline reset. Note - We must hold the SW/FW semaphore before writing
2009 static s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw) in ixgbe_reset_pipeline_82599() argument
2016 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); in ixgbe_reset_pipeline_82599()
2019 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); in ixgbe_reset_pipeline_82599()
2020 IXGBE_WRITE_FLUSH(hw); in ixgbe_reset_pipeline_82599()
2023 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); in ixgbe_reset_pipeline_82599()
2027 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, in ixgbe_reset_pipeline_82599()
2033 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); in ixgbe_reset_pipeline_82599()
2039 hw_dbg(hw, "auto negotiation not completed\n"); in ixgbe_reset_pipeline_82599()
2040 ret_val = -EIO; in ixgbe_reset_pipeline_82599()
2048 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); in ixgbe_reset_pipeline_82599()
2049 IXGBE_WRITE_FLUSH(hw); in ixgbe_reset_pipeline_82599()
2055 * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C
2056 * @hw: pointer to hardware structure
2064 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, in ixgbe_read_i2c_byte_82599() argument
2071 if (hw->phy.qsfp_shared_i2c_bus == true) { in ixgbe_read_i2c_byte_82599()
2073 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); in ixgbe_read_i2c_byte_82599()
2075 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); in ixgbe_read_i2c_byte_82599()
2076 IXGBE_WRITE_FLUSH(hw); in ixgbe_read_i2c_byte_82599()
2079 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); in ixgbe_read_i2c_byte_82599()
2084 timeout--; in ixgbe_read_i2c_byte_82599()
2088 hw_dbg(hw, "Driver can't access resource, acquiring I2C bus timeout.\n"); in ixgbe_read_i2c_byte_82599()
2089 status = -EIO; in ixgbe_read_i2c_byte_82599()
2094 status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data); in ixgbe_read_i2c_byte_82599()
2097 if (hw->phy.qsfp_shared_i2c_bus == true) { in ixgbe_read_i2c_byte_82599()
2099 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); in ixgbe_read_i2c_byte_82599()
2101 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); in ixgbe_read_i2c_byte_82599()
2102 IXGBE_WRITE_FLUSH(hw); in ixgbe_read_i2c_byte_82599()
2109 * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C
2110 * @hw: pointer to hardware structure
2118 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, in ixgbe_write_i2c_byte_82599() argument
2125 if (hw->phy.qsfp_shared_i2c_bus == true) { in ixgbe_write_i2c_byte_82599()
2127 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); in ixgbe_write_i2c_byte_82599()
2129 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); in ixgbe_write_i2c_byte_82599()
2130 IXGBE_WRITE_FLUSH(hw); in ixgbe_write_i2c_byte_82599()
2133 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); in ixgbe_write_i2c_byte_82599()
2138 timeout--; in ixgbe_write_i2c_byte_82599()
2142 hw_dbg(hw, "Driver can't access resource, acquiring I2C bus timeout.\n"); in ixgbe_write_i2c_byte_82599()
2143 status = -EIO; in ixgbe_write_i2c_byte_82599()
2148 status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data); in ixgbe_write_i2c_byte_82599()
2151 if (hw->phy.qsfp_shared_i2c_bus == true) { in ixgbe_write_i2c_byte_82599()
2153 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); in ixgbe_write_i2c_byte_82599()
2155 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); in ixgbe_write_i2c_byte_82599()
2156 IXGBE_WRITE_FLUSH(hw); in ixgbe_write_i2c_byte_82599()