intel/igc/igc_defines.h

1 /* SPDX-License-Identifier: GPL-2.0 */
15 /* Definitions for power management and wakeup registers */
20 #define IGC_WUFC_LNKC		0x00000001 /* Link Status Change Wakeup Enable */
21 #define IGC_WUFC_MAG		0x00000002 /* Magic Packet Wakeup Enable */
22 #define IGC_WUFC_EX		0x00000004 /* Directed Exact Wakeup Enable */
23 #define IGC_WUFC_MC		0x00000008 /* Directed Multicast Wakeup Enable */
24 #define IGC_WUFC_BC		0x00000010 /* Broadcast Wakeup Enable */
60 /* Wakeup Filter Control Extended */
88 /* Loop limit on how long we wait for auto-negotiation to complete */
112 #define IGC_RAH_AV		0x80000000 /* Receive descriptor valid */
170 /* 1000BASE-T Control Register */
174 /* 1000BASE-T Status Register */
224 #define IGC_STATUS_FUNC_MASK	0x0000000C      /* PCI Function Mask */
238 /* 1Gbps and 2.5Gbps half duplex is not supported, nor spec-compliant. */
277 /* Interrupt Mask Set */
287 #define IGC_QVECTOR_MASK	0x7FFC		/* Q-vector mask */
288 #define IGC_ITR_VAL_MASK	0x04		/* ITR value mask */
333 #define IGC_TCTL_RTLC		0x01000000 /* Re-transmit on late collision */
405 #define IGC_DTXMXPKTSZ_DEFAULT	0x98 /* 9728-byte Jumbo frames */
432 #define IGC_TSYNCRXCTL_TYPE_MASK	0x0000000E  /* Rx type mask */
448 #define IGC_IMIR_CLEAR_MASK	0xF001FFFF /* IMIR Reg Clear Mask */
451 #define IGC_IMIREXT_CLEAR_MASK	0x7FFFF /* IMIREXT Reg Clear Mask */
458 #define IGC_TSYNCTXCTL_TXTT_0			0x00000001  /* Tx timestamp reg 0 valid */
459 #define IGC_TSYNCTXCTL_TXTT_1			0x00000002  /* Tx timestamp reg 1 valid */
460 #define IGC_TSYNCTXCTL_TXTT_2			0x00000004  /* Tx timestamp reg 2 valid */
461 #define IGC_TSYNCTXCTL_TXTT_3			0x00000008  /* Tx timestamp reg 3 valid */
579 #define IGC_PTM_STAT_ADJUST_CYC		BIT(5) /* 1588 timer adjusted during non-1st PTM cycle */
585 /* GPY211 - I225 defines */
598 #define IGC_MANC_SMBUS_EN	0x00000001 /* SMBus Enabled - RO */
599 #define IGC_MANC_ASF_EN		0x00000002 /* ASF Enabled - RO */
603 #define MAX_PHY_REG_ADDRESS	0x1F  /* 5 bit address bus (0-0x1F) */
624 #define PHY_1000T_CTRL		0x09 /* 1000Base-T Control Reg */
625 #define PHY_1000T_STATUS	0x0A /* 1000Base-T Status Reg */
638 #define IGC_N0_QUEUE		-1
669 /* Minimum time for 100BASE-T where no data will be transmit following move out