Lines Matching +full:0 +full:x94000
122 ICE_RCLKA_PIN = 0, /* SCL pin */
132 ZL_REF0P = 0,
146 ZL_OUT0 = 0,
157 SI_REF0P = 0,
169 SI_OUT0 = 0,
200 #define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL
290 #define ICE_PTP_CLOCK_INDEX_0 0x00
291 #define ICE_PTP_CLOCK_INDEX_1 0x01
298 #define GLTSYN_CMD_INIT_TIME BIT(0)
300 #define GLTSYN_CMD_INIT_TIME_INCVAL (BIT(0) | BIT(1))
306 #define PHY_CMD_INIT_TIME BIT(0)
308 #define PHY_CMD_ADJ_TIME (BIT(0) | BIT(1))
309 #define PHY_CMD_ADJ_TIME_AT_TIME (BIT(0) | BIT(2))
310 #define PHY_CMD_READ_TIME (BIT(0) | BIT(1) | BIT(2))
312 #define TS_CMD_MASK_E810 0xFF
313 #define TS_CMD_MASK 0xF
314 #define SYNC_EXEC_CMD 0x3
317 #define P_Q0_L(a, p) ((((a) + (0x2000 * (p)))) & 0xFFFF)
318 #define P_Q0_H(a, p) ((((a) + (0x2000 * (p)))) >> 16)
319 #define P_Q1_L(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) & 0xFFFF)
320 #define P_Q1_H(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) >> 16)
323 #define Q_0_BASE 0x94000
324 #define Q_1_BASE 0x114000
327 #define Q_REG_TS_CTRL 0x618
328 #define Q_REG_TS_CTRL_S 0
329 #define Q_REG_TS_CTRL_M BIT(0)
332 #define Q_REG_TX_MEMORY_STATUS_L 0xCF0
333 #define Q_REG_TX_MEMORY_STATUS_U 0xCF4
336 #define Q_REG_FIFO23_STATUS 0xCF8
337 #define Q_REG_FIFO01_STATUS 0xCFC
338 #define Q_REG_FIFO02_S 0
339 #define Q_REG_FIFO02_M ICE_M(0x3FF, 0)
341 #define Q_REG_FIFO13_M ICE_M(0x3FF, 10)
344 #define Q_REG_TX_MEM_GBL_CFG 0xC08
345 #define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_S 0
346 #define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M BIT(0)
348 #define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_M ICE_M(0xFF, 1)
350 #define Q_REG_TX_MEM_GBL_CFG_INTR_THR_M ICE_M(0x3F, 9)
355 #define Q_REG_TX_MEMORY_BANK_START 0xA00
358 #define P_0_BASE 0x80000
359 #define P_4_BASE 0x106000
362 #define P_REG_RX_TIMER_INC_PRE_L 0x46C
363 #define P_REG_RX_TIMER_INC_PRE_U 0x470
364 #define P_REG_TX_TIMER_INC_PRE_L 0x44C
365 #define P_REG_TX_TIMER_INC_PRE_U 0x450
368 #define P_REG_RX_TIMER_CNT_ADJ_L 0x474
369 #define P_REG_RX_TIMER_CNT_ADJ_U 0x478
370 #define P_REG_TX_TIMER_CNT_ADJ_L 0x454
371 #define P_REG_TX_TIMER_CNT_ADJ_U 0x458
374 #define P_REG_RX_CAPTURE_L 0x4D8
375 #define P_REG_RX_CAPTURE_U 0x4DC
376 #define P_REG_TX_CAPTURE_L 0x4B4
377 #define P_REG_TX_CAPTURE_U 0x4B8
380 #define P_REG_TIMETUS_L 0x410
381 #define P_REG_TIMETUS_U 0x414
383 #define P_REG_40B_LOW_M 0xFF
387 #define P_REG_WL 0x40C
389 #define PTP_VERNIER_WL 0x111ed
392 #define P_REG_PS 0x408
393 #define P_REG_PS_START_S 0
394 #define P_REG_PS_START_M BIT(0)
405 #define P_REG_TX_OV_STATUS 0x4D4
406 #define P_REG_TX_OV_STATUS_OV_S 0
407 #define P_REG_TX_OV_STATUS_OV_M BIT(0)
408 #define P_REG_RX_OV_STATUS 0x4F8
409 #define P_REG_RX_OV_STATUS_OV_S 0
410 #define P_REG_RX_OV_STATUS_OV_M BIT(0)
413 #define P_REG_TX_OR 0x45C
414 #define P_REG_RX_OR 0x47C
417 #define P_REG_TOTAL_RX_OFFSET_L 0x460
418 #define P_REG_TOTAL_RX_OFFSET_U 0x464
419 #define P_REG_TOTAL_TX_OFFSET_L 0x440
420 #define P_REG_TOTAL_TX_OFFSET_U 0x444
423 #define P_REG_UIX66_10G_40G_L 0x480
424 #define P_REG_UIX66_10G_40G_U 0x484
425 #define P_REG_UIX66_25G_100G_L 0x488
426 #define P_REG_UIX66_25G_100G_U 0x48C
427 #define P_REG_DESK_PAR_RX_TUS_L 0x490
428 #define P_REG_DESK_PAR_RX_TUS_U 0x494
429 #define P_REG_DESK_PAR_TX_TUS_L 0x498
430 #define P_REG_DESK_PAR_TX_TUS_U 0x49C
431 #define P_REG_DESK_PCS_RX_TUS_L 0x4A0
432 #define P_REG_DESK_PCS_RX_TUS_U 0x4A4
433 #define P_REG_DESK_PCS_TX_TUS_L 0x4A8
434 #define P_REG_DESK_PCS_TX_TUS_U 0x4AC
435 #define P_REG_PAR_RX_TUS_L 0x420
436 #define P_REG_PAR_RX_TUS_U 0x424
437 #define P_REG_PAR_TX_TUS_L 0x428
438 #define P_REG_PAR_TX_TUS_U 0x42C
439 #define P_REG_PCS_RX_TUS_L 0x430
440 #define P_REG_PCS_RX_TUS_U 0x434
441 #define P_REG_PCS_TX_TUS_L 0x438
442 #define P_REG_PCS_TX_TUS_U 0x43C
443 #define P_REG_PAR_RX_TIME_L 0x4F0
444 #define P_REG_PAR_RX_TIME_U 0x4F4
445 #define P_REG_PAR_TX_TIME_L 0x4CC
446 #define P_REG_PAR_TX_TIME_U 0x4D0
447 #define P_REG_PAR_PCS_RX_OFFSET_L 0x4E8
448 #define P_REG_PAR_PCS_RX_OFFSET_U 0x4EC
449 #define P_REG_PAR_PCS_TX_OFFSET_L 0x4C4
450 #define P_REG_PAR_PCS_TX_OFFSET_U 0x4C8
451 #define P_REG_LINK_SPEED 0x4FC
452 #define P_REG_LINK_SPEED_SERDES_S 0
453 #define P_REG_LINK_SPEED_SERDES_M ICE_M(0x7, 0)
455 #define P_REG_LINK_SPEED_FEC_MODE_M ICE_M(0x3, 3)
461 #define P_REG_PMD_ALIGNMENT 0x0FC
462 #define P_REG_RX_80_TO_160_CNT 0x6FC
463 #define P_REG_RX_80_TO_160_CNT_RXCYC_S 0
464 #define P_REG_RX_80_TO_160_CNT_RXCYC_M BIT(0)
465 #define P_REG_RX_40_TO_160_CNT 0x8FC
466 #define P_REG_RX_40_TO_160_CNT_RXCYC_S 0
467 #define P_REG_RX_40_TO_160_CNT_RXCYC_M ICE_M(0x3, 0)
470 #define P_REG_RX_OV_FS 0x4F8
472 #define P_REG_RX_OV_FS_FIFO_STATUS_M ICE_M(0x3FF, 2)
475 #define P_REG_TX_TMR_CMD 0x448
476 #define P_REG_RX_TMR_CMD 0x468
479 #define ETH_GLTSYN_ENA(_i) (0x03000348 + ((_i) * 4))
482 #define ETH_GLTSYN_SHTIME_0(i) (0x03000368 + ((i) * 32))
483 #define ETH_GLTSYN_SHTIME_L(i) (0x0300036C + ((i) * 32))
486 #define ETH_GLTSYN_SHADJ_L(_i) (0x03000378 + ((_i) * 32))
487 #define ETH_GLTSYN_SHADJ_H(_i) (0x0300037C + ((_i) * 32))
490 #define ETH_GLTSYN_CMD 0x03000344
493 #define INCVAL_HIGH_M 0xFF
496 #define TS_VALID BIT(0)
497 #define TS_LOW_M 0xFFFFFFFF
498 #define TS_HIGH_M 0xFF
501 #define TS_PHY_LOW_M 0xFF
502 #define TS_PHY_HIGH_M 0xFFFFFFFF
521 #define TS_EXT(a, port, idx) ((a) + (0x1000 * (port)) + \
524 #define LOW_TX_MEMORY_BANK_START 0x03090000
525 #define HIGH_TX_MEMORY_BANK_START 0x03090004
547 #define ICE_PCA9575_P0_IN 0x0