616  * ice_fill_quad_msg_e82x - Fill message data for quad register access
618  * @quad: the quad to access
621  * Fill a message buffer for accessing a register in a quad shared between
625 ice_fill_quad_msg_e82x(struct ice_sbq_msg_input *msg, u8 quad, u16 offset)  in ice_fill_quad_msg_e82x()  argument
629 	if (quad >= ICE_MAX_QUAD)  in ice_fill_quad_msg_e82x()
634 	if ((quad % ICE_QUADS_PER_PHY_E82X) == 0)  in ice_fill_quad_msg_e82x()
646  * ice_read_quad_reg_e82x - Read a PHY quad register
648  * @quad: quad to read from
649  * @offset: quad register offset to read
650  * @val: on return, the contents read from the quad
652  * Read a quad register over the device sideband queue. Quad registers are
656 ice_read_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 *val)  in ice_read_quad_reg_e82x()  argument
661 	err = ice_fill_quad_msg_e82x(&msg, quad, offset);  in ice_read_quad_reg_e82x()
680  * ice_write_quad_reg_e82x - Write a PHY quad register
682  * @quad: quad to write to
683  * @offset: quad register offset to write
686  * Write a quad register over the device sideband queue. Quad registers are
690 ice_write_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 val)  in ice_write_quad_reg_e82x()  argument
695 	err = ice_fill_quad_msg_e82x(&msg, quad, offset);  in ice_write_quad_reg_e82x()
713  * ice_read_phy_tstamp_e82x - Read a PHY timestamp out of the quad block
715  * @quad: the quad to read from
720  * quad memory block that is shared between the internal PHYs of the E822
724 ice_read_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp)  in ice_read_phy_tstamp_e82x()  argument
733 	err = ice_read_quad_reg_e82x(hw, quad, lo_addr, &lo);  in ice_read_phy_tstamp_e82x()
740 	err = ice_read_quad_reg_e82x(hw, quad, hi_addr, &hi);  in ice_read_phy_tstamp_e82x()
757  * ice_clear_phy_tstamp_e82x - Clear a timestamp from the quad block
759  * @quad: the quad to read from
762  * Read the timestamp out of the quad to clear its timestamp status bit from
763  * the PHY quad block that is shared between the internal PHYs of the E822
766  * Note that unlike E810, software cannot directly write to the quad memory
779 ice_clear_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx)  in ice_clear_phy_tstamp_e82x()  argument
784 	err = ice_read_phy_tstamp_e82x(hw, quad, idx, &unused_tstamp);  in ice_clear_phy_tstamp_e82x()
786 		ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for quad %u, idx %u, err %d\n",  in ice_clear_phy_tstamp_e82x()
787 			  quad, idx, err);  in ice_clear_phy_tstamp_e82x()
795  * ice_ptp_reset_ts_memory_quad_e82x - Clear all timestamps from the quad block
797  * @quad: the quad to read from
799  * Clear all timestamps from the PHY quad block that is shared between the
802 void ice_ptp_reset_ts_memory_quad_e82x(struct ice_hw *hw, u8 quad)  in ice_ptp_reset_ts_memory_quad_e82x()  argument
804 	ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL, Q_REG_TS_CTRL_M);  in ice_ptp_reset_ts_memory_quad_e82x()
805 	ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL, ~(u32)Q_REG_TS_CTRL_M);  in ice_ptp_reset_ts_memory_quad_e82x()
809  * ice_ptp_reset_ts_memory_e82x - Clear all timestamps from all quad blocks
814 	unsigned int quad;  in ice_ptp_reset_ts_memory_e82x()  local
816 	for (quad = 0; quad < ICE_MAX_QUAD; quad++)  in ice_ptp_reset_ts_memory_e82x()
817 		ice_ptp_reset_ts_memory_quad_e82x(hw, quad);  in ice_ptp_reset_ts_memory_e82x()
1588  * ice_phy_cfg_lane_e82x - Configure PHY quad for single/multi-lane timestamp
1590  * @port: to configure the quad for
1597 	u8 quad;  in ice_phy_cfg_lane_e82x()  local
1606 	quad = port / ICE_PORTS_PER_QUAD;  in ice_phy_cfg_lane_e82x()
1608 	err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val);  in ice_phy_cfg_lane_e82x()
1620 	err = ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, val);  in ice_phy_cfg_lane_e82x()
2604  * @quad: the timestamp quad to read from
2612 ice_get_phy_tx_tstamp_ready_e82x(struct ice_hw *hw, u8 quad, u64 *tstamp_ready)  in ice_get_phy_tx_tstamp_ready_e82x()  argument
2617 	err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEMORY_STATUS_U, &hi);  in ice_get_phy_tx_tstamp_ready_e82x()
2619 		ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_U for quad %u, err %d\n",  in ice_get_phy_tx_tstamp_ready_e82x()
2620 			  quad, err);  in ice_get_phy_tx_tstamp_ready_e82x()
2624 	err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEMORY_STATUS_L, &lo);  in ice_get_phy_tx_tstamp_ready_e82x()
2626 		ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_L for quad %u, err %d\n",  in ice_get_phy_tx_tstamp_ready_e82x()
2627 			  quad, err);  in ice_get_phy_tx_tstamp_ready_e82x()
3516  * the block is the quad to read from. For E810 devices, the block is the
3541  * For E822 devices, the block number is the PHY quad to clear from. For E810