Lines Matching +full:hi +full:- +full:speed
1 // SPDX-License-Identifier: GPL-2.0
24 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
26 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
28 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0, },
29 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0, },
34 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
40 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
42 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
44 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, },
45 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, },
46 { "C827_1-RCLKA", ZL_REF2P, DPLL_PIN_TYPE_MUX, },
47 { "C827_1-RCLKB", ZL_REF2N, DPLL_PIN_TYPE_MUX, },
52 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
58 { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT,
60 { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT,
62 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, },
63 { "MAC-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, },
64 { "CVL-SDP21", ZL_OUT4, DPLL_PIN_TYPE_EXT,
66 { "CVL-SDP23", ZL_OUT5, DPLL_PIN_TYPE_EXT,
71 { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT,
73 { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT,
75 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
76 { "PHY2-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
77 { "MAC-CLK", ZL_OUT4, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
78 { "CVL-SDP21", ZL_OUT5, DPLL_PIN_TYPE_EXT,
80 { "CVL-SDP23", ZL_OUT6, DPLL_PIN_TYPE_EXT,
99 { "1588-TIME_SYNC", SI_OUT0, DPLL_PIN_TYPE_EXT,
101 { "PHY-CLK", SI_OUT1, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
102 { "10MHZ-SMA2", SI_OUT2, DPLL_PIN_TYPE_EXT,
104 { "PPS-SMA1", SI_OUT3, DPLL_PIN_TYPE_EXT,
125 { "PPS-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT,
127 { "10MHZ-SMA2", ZL_OUT1, DPLL_PIN_TYPE_EXT,
129 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
130 { "1588-TIME_REF", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
131 { "CPK-TIME_SYNC", ZL_OUT4, DPLL_PIN_TYPE_EXT,
142 * +---------------+ +---------------+ +---------------+
144 * +---------------+ +---------------+ +---------------+
150 * +---------------+ +---------------+
152 * +---------------+ +---------------+
163 * - 823.4375 MHz
164 * - 783.36 MHz
165 * - 796.875 MHz
166 * - 816 MHz
167 * - 830.078125 MHz
168 * - 783.36 MHz
184 * - E822 based devices have additional support for fine grained Vernier
186 * - The layout of timestamp data in the PHY register blocks is different
187 * - The way timer synchronization commands are issued is different.
199 * ice_get_ptp_src_clock_index - determine source clock index
207 return hw->func_caps.ts_func_info.tmr_index_assoc; in ice_get_ptp_src_clock_index()
211 * ice_ptp_read_src_incval - Read source timer increment value
218 u32 lo, hi; in ice_ptp_read_src_incval() local
224 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx)); in ice_ptp_read_src_incval()
226 return ((u64)(hi & INCVAL_HIGH_M) << 32) | lo; in ice_ptp_read_src_incval()
230 * ice_ptp_src_cmd - Prepare source timer for a timer command
268 * ice_ptp_exec_tmr_cmd - Execute all prepared timer commands
287 * ice_fill_phy_msg_e82x - Fill message data for a PHY register access
302 msg->msg_addr_low = P_Q0_L(P_0_BASE + offset, phy_port); in ice_fill_phy_msg_e82x()
303 msg->msg_addr_high = P_Q0_H(P_0_BASE + offset, phy_port); in ice_fill_phy_msg_e82x()
305 msg->msg_addr_low = P_Q1_L(P_4_BASE + offset, phy_port); in ice_fill_phy_msg_e82x()
306 msg->msg_addr_high = P_Q1_H(P_4_BASE + offset, phy_port); in ice_fill_phy_msg_e82x()
310 msg->dest_dev = rmn_0; in ice_fill_phy_msg_e82x()
312 msg->dest_dev = rmn_1; in ice_fill_phy_msg_e82x()
314 msg->dest_dev = rmn_2; in ice_fill_phy_msg_e82x()
318 * ice_is_64b_phy_reg_e82x - Check if this is a 64bit PHY register
371 * ice_is_40b_phy_reg_e82x - Check if this is a 40bit PHY register
416 * ice_read_phy_reg_e82x - Read a PHY register
446 * ice_read_64b_phy_reg_e82x - Read a 64bit value from PHY registers
470 return -EINVAL; in ice_read_64b_phy_reg_e82x()
493 * ice_write_phy_reg_e82x - Write a PHY register
522 * ice_write_40b_phy_reg_e82x - Write a 40b value to the PHY
544 return -EINVAL; in ice_write_40b_phy_reg_e82x()
568 * ice_write_64b_phy_reg_e82x - Write a 64bit value to PHY registers
592 return -EINVAL; in ice_write_64b_phy_reg_e82x()
616 * ice_fill_quad_msg_e82x - Fill message data for quad register access
630 return -EINVAL; in ice_fill_quad_msg_e82x()
632 msg->dest_dev = rmn_0; in ice_fill_quad_msg_e82x()
639 msg->msg_addr_low = lower_16_bits(addr); in ice_fill_quad_msg_e82x()
640 msg->msg_addr_high = upper_16_bits(addr); in ice_fill_quad_msg_e82x()
646 * ice_read_quad_reg_e82x - Read a PHY quad register
680 * ice_write_quad_reg_e82x - Write a PHY quad register
713 * ice_read_phy_tstamp_e82x - Read a PHY timestamp out of the quad block
727 u32 lo, hi; in ice_read_phy_tstamp_e82x() local
740 err = ice_read_quad_reg_e82x(hw, quad, hi_addr, &hi); in ice_read_phy_tstamp_e82x()
751 *tstamp = ((u64)hi) << TS_PHY_HIGH_S | ((u64)lo & TS_PHY_LOW_M); in ice_read_phy_tstamp_e82x()
757 * ice_clear_phy_tstamp_e82x - Clear a timestamp from the quad block
768 * to determine which timestamps are valid. Reading a timestamp auto-clears
795 * ice_ptp_reset_ts_memory_quad_e82x - Clear all timestamps from the quad block
809 * ice_ptp_reset_ts_memory_e82x - Clear all timestamps from all quad blocks
821 * ice_read_cgu_reg_e82x - Read a CGU register
853 * ice_write_cgu_reg_e82x - Write a CGU register
884 * ice_clk_freq_str - Convert time_ref_freq to string
910 * ice_clk_src_str - Convert time_ref_src to string
928 * ice_cfg_cgu_pll_e82x - Configure the Clock Generation Unit
950 return -EINVAL; in ice_cfg_cgu_pll_e82x()
956 return -EINVAL; in ice_cfg_cgu_pll_e82x()
963 return -EINVAL; in ice_cfg_cgu_pll_e82x()
979 ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", in ice_cfg_cgu_pll_e82x()
1053 return -EBUSY; in ice_cfg_cgu_pll_e82x()
1057 ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", in ice_cfg_cgu_pll_e82x()
1067 * ice_init_cgu_e82x - Initialize CGU with settings from firmware
1074 struct ice_ts_func_info *ts_info = &hw->func_caps.ts_func_info; in ice_init_cgu_e82x()
1095 err = ice_cfg_cgu_pll_e82x(hw, ts_info->time_ref, in ice_init_cgu_e82x()
1096 (enum ice_clk_src)ts_info->clk_src); in ice_init_cgu_e82x()
1104 * ice_ptp_set_vernier_wl - Set the window length for vernier calibration
1129 * ice_ptp_init_phc_e82x - Perform E822 specific PHC initialization
1157 * ice_ptp_prep_phy_time_e82x - Prepare PHY port with initial time
1204 * ice_ptp_prep_port_adj_e82x - Prepare a single port for time adjust
1214 * including the lower sub-nanosecond portion of the port timer.
1258 * ice_ptp_prep_phy_adj_e82x - Prep PHY ports for a time adjustment
1272 /* The port clock supports adjustment of the sub-nanosecond portion of in ice_ptp_prep_phy_adj_e82x()
1279 cycles = -(((s64)-adj) << 32); in ice_ptp_prep_phy_adj_e82x()
1293 * ice_ptp_prep_phy_incval_e82x - Prepare PHY ports for time adjustment
1324 * ice_ptp_read_port_capture - Read a port's local time capture
1365 * ice_ptp_write_port_cmd_e82x - Prepare a single PHY port for a timer command
1448 * ice_ptp_one_port_cmd - Prepare one port for a timer command
1481 * ice_ptp_port_cmd_e82x - Prepare all ports for a timer command
1512 * ice_phy_get_speed_and_fec_e82x - Get link speed and FEC based on serdes mode
1515 * @link_out: if non-NULL, holds link speed on success
1516 * @fec_out: if non-NULL, holds FEC algorithm on success
1518 * Read the serdes data for the PHY port and extract the link speed and FEC
1542 /* Determine the link speed */ in ice_phy_get_speed_and_fec_e82x()
1555 return -EIO; in ice_phy_get_speed_and_fec_e82x()
1575 return -EIO; in ice_phy_get_speed_and_fec_e82x()
1588 * ice_phy_cfg_lane_e82x - Configure PHY quad for single/multi-lane timestamp
1601 ice_debug(hw, ICE_DBG_PTP, "Failed to get PHY link speed, err %d\n", in ice_phy_cfg_lane_e82x()
1629 * ice_phy_cfg_uix_e82x - Configure Serdes UI to TU conversion for E822
1655 * -------+--------------+--------------+-------------
1714 * ice_phy_cfg_parpcs_e82x - Configure TUs per PAR/PCS clock cycle
1719 * timestamp calibration process. This depends on the link speed, as the PHY
1720 * uses different markers depending on the speed.
1723 * - Tx/Rx PAR/PCS markers
1726 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers
1729 * - Tx/Rx PAR/PCS markers
1730 * - Rx Deskew PAR/PCS markers
1733 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers
1734 * - Rx Deskew PAR/PCS markers
1735 * - Tx PAR/PCS markers
1743 * -------+-------+--------
1774 * speed frequency and determine the TUs per that clock's cycle time. in ice_phy_cfg_parpcs_e82x()
1776 * appropriate register. If that link speed does not use the in ice_phy_cfg_parpcs_e82x()
1876 * ice_calc_fixed_tx_offset_e82x - Calculated Fixed Tx offset for a port
1878 * @link_spd: the Link speed to calculate for
1907 * ice_phy_cfg_tx_offset_e82x - Configure total Tx timestamp offset
1926 * Returns zero on success, -EBUSY if the hardware vernier offset
1956 return -EBUSY; in ice_phy_cfg_tx_offset_e82x()
1983 * multi-lane link speeds with RS-FEC. The lanes will always be in ice_phy_cfg_tx_offset_e82x()
2017 * ice_phy_calc_pmd_adj_e82x - Calculate PMD adjustment for Rx
2020 * @link_spd: the current link speed of the PHY
2025 * This varies by link speed and FEC mode. The value calculated accounts for
2053 /* The PMD alignment adjustment measurement depends on the link speed, in ice_phy_calc_pmd_adj_e82x()
2054 * and whether FEC is enabled. For each link speed, the alignment in ice_phy_calc_pmd_adj_e82x()
2068 * For RS-FEC, if align is < 17 then we must also add 1.6 * 32/33. in ice_phy_calc_pmd_adj_e82x()
2099 ice_debug(hw, ICE_DBG_PTP, "Unknown link speed %d, skipping PMD adjustment\n", in ice_phy_calc_pmd_adj_e82x()
2113 * speed pmd_adj_divisor value. in ice_phy_calc_pmd_adj_e82x()
2119 /* Finally, for 25G-RS and 50G-RS, a further adjustment for the Rx in ice_phy_calc_pmd_adj_e82x()
2129 ice_debug(hw, ICE_DBG_PTP, "Failed to read 25G-RS Rx cycle count, err %d\n", in ice_phy_calc_pmd_adj_e82x()
2136 mult = (4 - rx_cycle) * 40; in ice_phy_calc_pmd_adj_e82x()
2151 ice_debug(hw, ICE_DBG_PTP, "Failed to read 50G-RS Rx cycle count, err %d\n", in ice_phy_calc_pmd_adj_e82x()
2175 * ice_calc_fixed_rx_offset_e82x - Calculated the fixed Rx offset for a port
2177 * @link_spd: The Link speed to calculate for
2179 * Determine the fixed Rx latency for a given link speed.
2206 * ice_phy_cfg_rx_offset_e82x - Configure total Rx timestamp offset
2213 * well as adjusting for multi-lane alignment delay.
2229 * Returns zero on success, -EBUSY if the hardware vernier offset
2259 return -EBUSY; in ice_phy_cfg_rx_offset_e82x()
2278 /* For Rx, all multi-lane link speeds include a second Vernier in ice_phy_cfg_rx_offset_e82x()
2299 /* For RS-FEC, this adjustment adds delay, but for other modes, it in ice_phy_cfg_rx_offset_e82x()
2305 total_offset -= pmd; in ice_phy_cfg_rx_offset_e82x()
2327 * ice_read_phy_and_phc_time_e82x - Simultaneously capture PHC and PHY time
2384 * ice_sync_phy_timer_e82x - Synchronize the PHY timer with PHC timer
2402 return -EBUSY; in ice_sync_phy_timer_e82x()
2417 difference = phc_time - phy_time; in ice_sync_phy_timer_e82x()
2433 /* Re-capture the timer values to flush the command registers and in ice_sync_phy_timer_e82x()
2455 * ice_stop_phy_timer_e82x - Stop the PHY clock timer
2461 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
2462 * initialized or when link speed changes.
2505 * ice_start_phy_timer_e82x - Start the PHY clock timer
2510 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
2511 * initialized or when link speed changes.
2517 u32 lo, hi, val; in ice_start_phy_timer_e82x() local
2539 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx)); in ice_start_phy_timer_e82x()
2540 incval = (u64)hi << 32 | lo; in ice_start_phy_timer_e82x()
2602 * ice_get_phy_tx_tstamp_ready_e82x - Read Tx memory status register
2614 u32 hi, lo; in ice_get_phy_tx_tstamp_ready_e82x() local
2617 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEMORY_STATUS_U, &hi); in ice_get_phy_tx_tstamp_ready_e82x()
2631 *tstamp_ready = (u64)hi << 32 | (u64)lo; in ice_get_phy_tx_tstamp_ready_e82x()
2643 * ice_read_phy_reg_e810 - Read register from external PHY on E810
2673 * ice_write_phy_reg_e810 - Write register on external PHY on E810
2702 * ice_read_phy_tstamp_ll_e810 - Read a PHY timestamp registers through the FW
2705 * @hi: 8 bit timestamp high value
2713 ice_read_phy_tstamp_ll_e810(struct ice_hw *hw, u8 idx, u8 *hi, u32 *lo) in ice_read_phy_tstamp_ll_e810() argument
2723 for (i = TS_LL_READ_RETRIES; i > 0; i--) { in ice_read_phy_tstamp_ll_e810()
2729 *hi = FIELD_GET(TS_LL_READ_TS_HIGH, val); in ice_read_phy_tstamp_ll_e810()
2741 return -EINVAL; in ice_read_phy_tstamp_ll_e810()
2745 * ice_read_phy_tstamp_sbq_e810 - Read a PHY timestamp registers through the sbq
2749 * @hi: 8 bit timestamp high value
2756 ice_read_phy_tstamp_sbq_e810(struct ice_hw *hw, u8 lport, u8 idx, u8 *hi, in ice_read_phy_tstamp_sbq_e810() argument
2779 *hi = (u8)hi_val; in ice_read_phy_tstamp_sbq_e810()
2785 * ice_read_phy_tstamp_e810 - Read a PHY timestamp out of the external PHY
2798 u8 hi = 0; in ice_read_phy_tstamp_e810() local
2801 if (hw->dev_caps.ts_dev_info.ts_ll_read) in ice_read_phy_tstamp_e810()
2802 err = ice_read_phy_tstamp_ll_e810(hw, idx, &hi, &lo); in ice_read_phy_tstamp_e810()
2804 err = ice_read_phy_tstamp_sbq_e810(hw, lport, idx, &hi, &lo); in ice_read_phy_tstamp_e810()
2812 *tstamp = ((u64)hi) << TS_HIGH_S | ((u64)lo & TS_LOW_M); in ice_read_phy_tstamp_e810()
2818 * ice_clear_phy_tstamp_e810 - Clear a timestamp from the external PHY
2863 * ice_ptp_init_phy_e810 - Enable PTP function on the external PHY
2874 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; in ice_ptp_init_phy_e810()
2885 * ice_ptp_init_phc_e810 - Perform E810 specific PHC initialization
2888 * Perform E810-specific PTP hardware clock initialization steps.
2900 * ice_ptp_prep_phy_time_e810 - Prepare PHY port with initial time
2916 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; in ice_ptp_prep_phy_time_e810()
2935 * ice_ptp_prep_phy_adj_e810 - Prep PHY port for a time adjustment
2952 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; in ice_ptp_prep_phy_adj_e810()
2955 * nanoseconds. Sub-nanosecond adjustment is not supported. in ice_ptp_prep_phy_adj_e810()
2975 * ice_ptp_prep_phy_incval_e810 - Prep PHY port increment value change
2989 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; in ice_ptp_prep_phy_incval_e810()
3011 * ice_ptp_port_cmd_e810 - Prepare all external PHYs for a timer command
3064 * ice_get_phy_tx_tstamp_ready_e810 - Read Tx memory status register
3091 * When found - the value will be cached in the hw structure and following calls
3103 if (hw->io_expander_handle) { in ice_get_pca9575_handle()
3104 *pca9575_handle = hw->io_expander_handle; in ice_get_pca9575_handle()
3113 cmd->addr.topo_params.node_type_ctx = in ice_get_pca9575_handle()
3121 if (hw->device_id == ICE_DEV_ID_E810C_SFP) in ice_get_pca9575_handle()
3123 else if (hw->device_id == ICE_DEV_ID_E810C_QSFP) in ice_get_pca9575_handle()
3126 return -EOPNOTSUPP; in ice_get_pca9575_handle()
3128 cmd->addr.topo_params.index = idx; in ice_get_pca9575_handle()
3132 return -EOPNOTSUPP; in ice_get_pca9575_handle()
3137 return -EOPNOTSUPP; in ice_get_pca9575_handle()
3140 hw->io_expander_handle = in ice_get_pca9575_handle()
3142 *pca9575_handle = hw->io_expander_handle; in ice_get_pca9575_handle()
3152 * Read the SMA controller state. It is connected to pins 3-7 of Port 1 of the
3153 * PCA9575 expander, so only bits 3-7 in data are valid.
3185 * Write the data to the SMA controller. It is connected to pins 3-7 of Port 1
3186 * of the PCA9575 expander, so only bits 3-7 in data are valid.
3250 * ice_ptp_lock - Acquire PTP global semaphore register lock
3272 hw_lock = rd32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id)); in ice_ptp_lock()
3287 * ice_ptp_unlock - Release PTP global semaphore register lock
3295 wr32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), 0); in ice_ptp_unlock()
3299 * ice_ptp_init_phy_model - Initialize hw->phy_model based on device type
3302 * Determine the PHY model for the device, and initialize hw->phy_model
3308 hw->phy_model = ICE_PHY_E810; in ice_ptp_init_phy_model()
3310 hw->phy_model = ICE_PHY_E82X; in ice_ptp_init_phy_model()
3314 * ice_ptp_tmr_cmd - Prepare and trigger a timer sync command
3331 switch (hw->phy_model) { in ice_ptp_tmr_cmd()
3339 err = -EOPNOTSUPP; in ice_ptp_tmr_cmd()
3357 * ice_ptp_init_time - Initialize device time to provided value
3374 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; in ice_ptp_init_time()
3383 switch (hw->phy_model) { in ice_ptp_init_time()
3391 err = -EOPNOTSUPP; in ice_ptp_init_time()
3401 * ice_ptp_write_incval - Program PHC with new increment value
3405 * Program the PHC with a new increment value. This requires a three-step
3419 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; in ice_ptp_write_incval()
3425 switch (hw->phy_model) { in ice_ptp_write_incval()
3433 err = -EOPNOTSUPP; in ice_ptp_write_incval()
3443 * ice_ptp_write_incval_locked - Program new incval while holding semaphore
3454 return -EBUSY; in ice_ptp_write_incval_locked()
3464 * ice_ptp_adj_clock - Adjust PHC clock time atomically
3469 * nanoseconds. This requires a three-step process:
3481 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; in ice_ptp_adj_clock()
3491 switch (hw->phy_model) { in ice_ptp_adj_clock()
3499 err = -EOPNOTSUPP; in ice_ptp_adj_clock()
3509 * ice_read_phy_tstamp - Read a PHY timestamp from the timestamo block
3521 switch (hw->phy_model) { in ice_read_phy_tstamp()
3527 return -EOPNOTSUPP; in ice_read_phy_tstamp()
3532 * ice_clear_phy_tstamp - Clear a timestamp from the timestamp block
3549 switch (hw->phy_model) { in ice_clear_phy_tstamp()
3555 return -EOPNOTSUPP; in ice_clear_phy_tstamp()
3560 * ice_get_pf_c827_idx - find and return the C827 index for the current pf
3564 * * 0 - success
3565 * * negative - failure
3575 if (hw->mac_type != ICE_MAC_E810) in ice_get_pf_c827_idx()
3576 return -ENODEV; in ice_get_pf_c827_idx()
3578 if (hw->device_id != ICE_DEV_ID_E810C_QSFP) { in ice_get_pf_c827_idx()
3592 return -ENOENT; in ice_get_pf_c827_idx()
3599 return -EIO; in ice_get_pf_c827_idx()
3605 * ice_ptp_reset_ts_memory - Reset timestamp memory for all blocks
3610 switch (hw->phy_model) { in ice_ptp_reset_ts_memory()
3621 * ice_ptp_init_phc - Initialize PTP hardware clock
3628 u8 src_idx = hw->func_caps.ts_func_info.tmr_index_owned; in ice_ptp_init_phc()
3636 switch (hw->phy_model) { in ice_ptp_init_phc()
3642 return -EOPNOTSUPP; in ice_ptp_init_phc()
3647 * ice_get_phy_tx_tstamp_ready - Read PHY Tx memory status indication
3659 switch (hw->phy_model) { in ice_get_phy_tx_tstamp_ready()
3668 return -EOPNOTSUPP; in ice_get_phy_tx_tstamp_ready()
3673 * ice_cgu_get_pin_desc_e823 - get pin description array
3685 if (hw->cgu_part_number == in ice_cgu_get_pin_desc_e823()
3694 } else if (hw->cgu_part_number == in ice_cgu_get_pin_desc_e823()
3712 * ice_cgu_get_pin_desc - get pin description array
3724 switch (hw->device_id) { in ice_cgu_get_pin_desc()
3763 * ice_cgu_get_pin_type - get pin's type
3787 * ice_cgu_get_pin_freq_supp - get pin's supported frequency
3815 * ice_cgu_get_pin_name - get pin's name
3841 * ice_get_cgu_state - get the state of the DPLL
3851 * This function will read the state of the DPLL(dpll_idx). Non-null
3885 * it would never return to FREERUN. This aligns to ITU-T G.781 in ice_get_cgu_state()
3907 * ice_get_cgu_rclk_pin_info - get info on available recovered clock pins
3916 * * 0 - success, information is valid
3917 * * negative - failure, information is not valid
3924 switch (hw->device_id) { in ice_get_cgu_rclk_pin_info()
3947 if (hw->cgu_part_number == in ice_get_cgu_rclk_pin_info()
3950 else if (hw->cgu_part_number == in ice_get_cgu_rclk_pin_info()
3954 ret = -ENODEV; in ice_get_cgu_rclk_pin_info()
3958 ret = -ENODEV; in ice_get_cgu_rclk_pin_info()
3966 * ice_cgu_get_output_pin_state_caps - get output pin state capabilities
3972 * * 0 - success, state capabilities were modified
3973 * * negative - failure, capabilities were not modified
3980 switch (hw->device_id) { in ice_cgu_get_output_pin_state_caps()
3999 if (hw->cgu_part_number == in ice_cgu_get_output_pin_state_caps()
4003 else if (hw->cgu_part_number == in ice_cgu_get_output_pin_state_caps()
4009 return -EINVAL; in ice_cgu_get_output_pin_state_caps()