Lines Matching full:30
21 #define PF_FW_ARQLEN_ARQCRIT_M BIT(30)
32 #define PF_FW_ATQLEN_ATQCRIT_M BIT(30)
43 #define PF_MBX_ARQLEN_ARQCRIT_M BIT(30)
52 #define PF_MBX_ATQLEN_ATQCRIT_M BIT(30)
73 #define PF_SB_ARQLEN_ARQCRIT_S 30
74 #define PF_SB_ARQLEN_ARQCRIT_M BIT(30)
96 #define PF_SB_ATQLEN_ATQCRIT_S 30
97 #define PF_SB_ATQLEN_ATQCRIT_M BIT(30)
119 #define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_S 30
120 #define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_M ICE_M(0x3, 30)
124 #define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_S 30
125 #define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_M ICE_M(0x3, 30)
129 #define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_S 30
130 #define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_M ICE_M(0x3, 30)
134 #define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_S 30
135 #define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_M ICE_M(0x3, 30)
191 #define GLINT_DYN_CTL_WB_ON_ITR_M BIT(30)
209 #define PFINT_FW_CTL_CAUSE_ENA_M BIT(30)
214 #define PFINT_MBX_CTL_CAUSE_ENA_M BIT(30)
231 #define PFINT_OICR_CTL_CAUSE_ENA_M BIT(30)
235 #define PFINT_SB_CTL_CAUSE_ENA_M BIT(30)
242 #define QINT_RQCTL_CAUSE_ENA_M BIT(30)
248 #define QINT_TQCTL_CAUSE_ENA_M BIT(30)
262 #define VPINT_MBX_CTL_CAUSE_ENA_M BIT(30)
352 #define GL_MNG_FWSM_FW_LOADING_M BIT(30)
376 #define GL_PWR_MODE_CTL_CAR_MAX_BW_S 30
377 #define GL_PWR_MODE_CTL_CAR_MAX_BW_M ICE_M(0x3, 30)
382 #define E800_GLQF_FD_CNT_FD_BCNT_M GENMASK(30, 16)
389 #define E800_GLQF_FD_SIZE_FD_BSIZE_M GENMASK(30, 16)
415 #define E800_PFQF_FD_CNT_FD_BCNT_M GENMASK(30, 16)