Lines Matching +full:num +full:- +full:tx +full:- +full:queues
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2013 - 2021 Intel Corporation. */
28 #define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024)
37 (test_bit(I40E_HW_CAP_RSS_AQ, (pf)->hw.caps) ? 4 : 1)
41 (test_bit(I40E_HW_CAP_128_QP_RSS, (pf)->hw.caps) ? 128 : 64)
68 (&(((union i40e_rx_desc *)((R)->desc))[i]))
70 (&(((struct i40e_tx_desc *)((R)->desc))[i]))
72 (&(((struct i40e_tx_context_desc *)((R)->desc))[i]))
74 (&(((struct i40e_filter_program_desc *)((R)->desc))[i]))
180 * - LINK_DOWN_ON_CLOSE_ENA is configurable at host OS run-time and
182 * - TOTAL_PORT_SHUTDOWN_ENA may be enabled only before OS loads
184 * - when LINK_DOWN_ON_CLOSE_ENABLED is used, the link is being brought
186 * - when TOTAL_PORT_SHUTDOWN_ENA is used, phy_type is not altered,
206 #define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2)
233 /* The following structure contains the data parsed from the user-defined
247 /* TX packet view of src and dst */
332 u16 qcount; /* Total Queues */
453 return !!ch->fwd; in i40e_is_channel_macvlan()
459 return ch->fwd->netdev->dev_addr; in i40e_channel_mac()
472 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */
473 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */
474 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */
475 u16 num_req_vfs; /* num VFs requested for this PF */
476 u16 num_vf_qps; /* num queue pairs per VF */
477 u16 num_lan_qps; /* num lan queues this PF has set up */
478 u16 num_lan_msix; /* num queue vectors for the base PF vsi */
479 u16 num_fdsb_msix; /* num queue vectors for sideband Fdir */
480 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */
482 int queues_left; /* queues left unclaimed */
483 u16 alloc_rss_size; /* allocated RSS queues */
484 u16 rss_size_max; /* HW defined max RSS queues */
485 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */
486 u16 num_alloc_vsi; /* num VSIs this driver supports */
496 /* Book-keeping of side-band filter count per flow-type.
498 * respective flow-type.
554 u16 next_vsi; /* Next unallocated VSI - 0-based! */
569 /* sr-iov config info */
690 * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key
714 #define I40E_VLAN_ANY -1
795 /* These are containers of ring pointers, allocated at run-time */
798 struct i40e_ring **xdp_rings; /* XDP Tx rings */
807 u16 rss_size; /* Allocated RSS queues */
828 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */
830 u16 num_queue_pairs; /* Used tx and rx pairs */
852 u16 idx; /* index in pf->vsi[] */
859 u16 cnt_q_avail; /* num of queues available for channel usage */
870 #define I40E_MAX_MACVLANS 128 /* Max HW vectors - 1 on FVL */
894 u16 v_idx; /* index in the vsi->q_vector array. */
900 struct i40e_ring_container tx; member
921 * i40e_info_nvm_ver - format the NVM version string
932 struct i40e_nvm_info *nvm = &hw->nvm; in i40e_info_nvm_ver()
934 if (nvm->eetrack == I40E_OEM_EETRACK_ID) { in i40e_info_nvm_ver()
935 u32 full_ver = nvm->oem_ver; in i40e_info_nvm_ver()
946 major = FIELD_GET(I40E_NVM_VERSION_HI_MASK, nvm->version); in i40e_info_nvm_ver()
947 minor = FIELD_GET(I40E_NVM_VERSION_LO_MASK, nvm->version); in i40e_info_nvm_ver()
953 * i40e_info_eetrack - format the EETrackID string
963 struct i40e_nvm_info *nvm = &hw->nvm; in i40e_info_eetrack()
966 if (nvm->eetrack != I40E_OEM_EETRACK_ID) in i40e_info_eetrack()
967 snprintf(buf, len, "0x%08x", nvm->eetrack); in i40e_info_eetrack()
971 * i40e_info_civd_ver - format the NVM version strings
981 struct i40e_nvm_info *nvm = &hw->nvm; in i40e_info_civd_ver()
984 if (nvm->eetrack != I40E_OEM_EETRACK_ID) { in i40e_info_civd_ver()
985 u32 full_ver = nvm->oem_ver; in i40e_info_civd_ver()
997 * i40e_nvm_version_str - format the NVM version strings
1011 i40e_info_eetrack(hw, &ver[1], sizeof(ver) - 1); in i40e_nvm_version_str()
1016 i40e_info_civd_ver(hw, &ver[1], sizeof(ver) - 1); in i40e_nvm_version_str()
1032 struct i40e_vsi *vsi = np->vsi; in i40e_netdev_to_pf()
1034 return vsi->back; in i40e_netdev_to_pf()
1040 vsi->irq_handler = irq_handler; in i40e_vsi_setup_irqhandler()
1044 * i40e_get_fd_cnt_all - get the total FD filter space available
1049 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count; in i40e_get_fd_cnt_all()
1053 * i40e_read_fd_input_set - reads value of flow director input set register
1058 * specified by 'addr' (which is specific to flow-type)
1064 val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1)); in i40e_read_fd_input_set()
1066 val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0)); in i40e_read_fd_input_set()
1072 * i40e_write_fd_input_set - writes value into flow director input set register
1078 * This register is input set register based on flow-type.
1083 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1), in i40e_write_fd_input_set()
1085 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0), in i40e_write_fd_input_set()
1090 * i40e_get_pf_count - get PCI PF count.
1116 * i40e_find_vsi_by_type - Find and return Flow Director VSI
1125 for (i = 0; i < pf->num_alloc_vsi; i++) { in i40e_find_vsi_by_type()
1126 struct i40e_vsi *vsi = pf->vsi[i]; in i40e_find_vsi_by_type()
1128 if (vsi && vsi->type == type) in i40e_find_vsi_by_type()
1201 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
1207 struct i40e_pf *pf = vsi->back; in i40e_irq_dynamic_enable()
1208 struct i40e_hw *hw = &pf->hw; in i40e_irq_dynamic_enable()
1214 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val); in i40e_irq_dynamic_enable()
1238 return test_bit(I40E_FLAG_FW_LLDP_DIS, pf->flags); in i40e_is_sw_dcb()
1276 return !!READ_ONCE(vsi->xdp_prog); in i40e_enabled_xdp_vsi()
1289 * i40e_is_tc_mqprio_enabled - check if TC MQPRIO is enabled on PF
1298 return test_bit(I40E_FLAG_TC_MQPRIO_ENA, pf->flags); in i40e_is_tc_mqprio_enabled()
1302 * i40e_hw_to_pf - get pf pointer from the hardware structure