1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
5  * 82562G-2 10/100 Network Connection
7  * 82562GT-2 10/100 Network Connection
9  * 82562V-2 10/100 Network Connection
10  * 82566DC-2 Gigabit Network Connection
12  * 82566DM-2 Gigabit Network Connection
19  * 82567LM-2 Gigabit Network Connection
20  * 82567LF-2 Gigabit Network Connection
21  * 82567V-2 Gigabit Network Connection
22  * 82567LF-3 Gigabit Network Connection
23  * 82567LM-3 Gigabit Network Connection
24  * 82567LM-4 Gigabit Network Connection
31  * Ethernet Connection I217-LM
32  * Ethernet Connection I217-V
33  * Ethernet Connection I218-V
34  * Ethernet Connection I218-LM
35  * Ethernet Connection (2) I218-LM
36  * Ethernet Connection (2) I218-V
37  * Ethernet Connection (3) I218-LM
38  * Ethernet Connection (3) I218-V
55 		u16 flockdn:1;	/* bit 15 Flash Config Lock-Down */
97 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
98 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
99 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
100 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
102 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
104 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
106 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
108 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
110 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
112 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
114 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
116 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
117 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
118 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
119 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
120 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
121 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
122 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
123 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
124 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
125 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
126 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
127 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
128 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
129 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
130 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
131 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
132 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
133 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
134 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw);
135 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
136 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
137 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
138 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
139 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
141 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)  in __er16flash()  argument
143 	return readw(hw->flash_address + reg);  in __er16flash()
146 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)  in __er32flash()  argument
148 	return readl(hw->flash_address + reg);  in __er32flash()
151 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)  in __ew16flash()  argument
153 	writew(val, hw->flash_address + reg);  in __ew16flash()
156 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)  in __ew32flash()  argument
158 	writel(val, hw->flash_address + reg);  in __ew32flash()
161 #define er16flash(reg)		__er16flash(hw, (reg))
162 #define er32flash(reg)		__er32flash(hw, (reg))
163 #define ew16flash(reg, val)	__ew16flash(hw, (reg), (val))
164 #define ew32flash(reg, val)	__ew32flash(hw, (reg), (val))
167  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
168  *  @hw: pointer to the HW structure
174  *  Assumes the sw/fw/hw semaphore is already acquired.
176 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)  in e1000_phy_is_accessible_pchlan()  argument
185 		ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);  in e1000_phy_is_accessible_pchlan()
190 		ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);  in e1000_phy_is_accessible_pchlan()
199 	if (hw->phy.id) {  in e1000_phy_is_accessible_pchlan()
200 		if (hw->phy.id == phy_id)  in e1000_phy_is_accessible_pchlan()
203 		hw->phy.id = phy_id;  in e1000_phy_is_accessible_pchlan()
204 		hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);  in e1000_phy_is_accessible_pchlan()
211 	if (hw->mac.type < e1000_pch_lpt) {  in e1000_phy_is_accessible_pchlan()
212 		hw->phy.ops.release(hw);  in e1000_phy_is_accessible_pchlan()
213 		ret_val = e1000_set_mdio_slow_mode_hv(hw);  in e1000_phy_is_accessible_pchlan()
215 			ret_val = e1000e_get_phy_id(hw);  in e1000_phy_is_accessible_pchlan()
216 		hw->phy.ops.acquire(hw);  in e1000_phy_is_accessible_pchlan()
222 	if (hw->mac.type >= e1000_pch_lpt) {  in e1000_phy_is_accessible_pchlan()
226 			e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);  in e1000_phy_is_accessible_pchlan()
228 			e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);  in e1000_phy_is_accessible_pchlan()
241  *  e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
242  *  @hw: pointer to the HW structure
244  *  Toggling the LANPHYPC pin value fully power-cycles the PHY and is
247 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)  in e1000_toggle_lanphypc_pch_lpt()  argument
258 	mac_reg = er32(CTRL);  in e1000_toggle_lanphypc_pch_lpt()
261 	ew32(CTRL, mac_reg);  in e1000_toggle_lanphypc_pch_lpt()
265 	ew32(CTRL, mac_reg);  in e1000_toggle_lanphypc_pch_lpt()
268 	if (hw->mac.type < e1000_pch_lpt) {  in e1000_toggle_lanphypc_pch_lpt()
275 		} while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--);  in e1000_toggle_lanphypc_pch_lpt()
282  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
283  *  @hw: pointer to the HW structure
285  *  Workarounds/flow necessary for PHY initialization during driver load
288 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)  in e1000_init_phy_workarounds_pchlan()  argument
290 	struct e1000_adapter *adapter = hw->adapter;  in e1000_init_phy_workarounds_pchlan()
295 	 * non-managed 82579 and newer adapters.  in e1000_init_phy_workarounds_pchlan()
297 	e1000_gate_hw_phy_config_ich8lan(hw, true);  in e1000_init_phy_workarounds_pchlan()
302 	hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;  in e1000_init_phy_workarounds_pchlan()
303 	ret_val = e1000_disable_ulp_lpt_lp(hw, true);  in e1000_init_phy_workarounds_pchlan()
307 	ret_val = hw->phy.ops.acquire(hw);  in e1000_init_phy_workarounds_pchlan()
309 		e_dbg("Failed to initialize PHY flow\n");  in e1000_init_phy_workarounds_pchlan()
313 	/* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is  in e1000_init_phy_workarounds_pchlan()
317 	switch (hw->mac.type) {  in e1000_init_phy_workarounds_pchlan()
327 		if (e1000_phy_is_accessible_pchlan(hw))  in e1000_init_phy_workarounds_pchlan()
345 		if (e1000_phy_is_accessible_pchlan(hw))  in e1000_init_phy_workarounds_pchlan()
350 		if ((hw->mac.type == e1000_pchlan) &&  in e1000_init_phy_workarounds_pchlan()
354 		if (hw->phy.ops.check_reset_block(hw)) {  in e1000_init_phy_workarounds_pchlan()
356 			ret_val = -E1000_ERR_PHY;  in e1000_init_phy_workarounds_pchlan()
361 		e1000_toggle_lanphypc_pch_lpt(hw);  in e1000_init_phy_workarounds_pchlan()
362 		if (hw->mac.type >= e1000_pch_lpt) {  in e1000_init_phy_workarounds_pchlan()
363 			if (e1000_phy_is_accessible_pchlan(hw))  in e1000_init_phy_workarounds_pchlan()
373 			if (e1000_phy_is_accessible_pchlan(hw))  in e1000_init_phy_workarounds_pchlan()
376 			ret_val = -E1000_ERR_PHY;  in e1000_init_phy_workarounds_pchlan()
383 	hw->phy.ops.release(hw);  in e1000_init_phy_workarounds_pchlan()
387 		if (hw->phy.ops.check_reset_block(hw)) {  in e1000_init_phy_workarounds_pchlan()
397 		ret_val = e1000e_phy_hw_reset_generic(hw);  in e1000_init_phy_workarounds_pchlan()
407 		ret_val = hw->phy.ops.check_reset_block(hw);  in e1000_init_phy_workarounds_pchlan()
413 	/* Ungate automatic PHY configuration on non-managed 82579 */  in e1000_init_phy_workarounds_pchlan()
414 	if ((hw->mac.type == e1000_pch2lan) &&  in e1000_init_phy_workarounds_pchlan()
417 		e1000_gate_hw_phy_config_ich8lan(hw, false);  in e1000_init_phy_workarounds_pchlan()
424  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
425  *  @hw: pointer to the HW structure
427  *  Initialize family-specific PHY parameters and function pointers.
429 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)  in e1000_init_phy_params_pchlan()  argument
431 	struct e1000_phy_info *phy = &hw->phy;  in e1000_init_phy_params_pchlan()
434 	phy->addr = 1;  in e1000_init_phy_params_pchlan()
435 	phy->reset_delay_us = 100;  in e1000_init_phy_params_pchlan()
437 	phy->ops.set_page = e1000_set_page_igp;  in e1000_init_phy_params_pchlan()
438 	phy->ops.read_reg = e1000_read_phy_reg_hv;  in e1000_init_phy_params_pchlan()
439 	phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;  in e1000_init_phy_params_pchlan()
440 	phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;  in e1000_init_phy_params_pchlan()
441 	phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;  in e1000_init_phy_params_pchlan()
442 	phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;  in e1000_init_phy_params_pchlan()
443 	phy->ops.write_reg = e1000_write_phy_reg_hv;  in e1000_init_phy_params_pchlan()
444 	phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;  in e1000_init_phy_params_pchlan()
445 	phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;  in e1000_init_phy_params_pchlan()
446 	phy->ops.power_up = e1000_power_up_phy_copper;  in e1000_init_phy_params_pchlan()
447 	phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;  in e1000_init_phy_params_pchlan()
448 	phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;  in e1000_init_phy_params_pchlan()
450 	phy->id = e1000_phy_unknown;  in e1000_init_phy_params_pchlan()
452 	ret_val = e1000_init_phy_workarounds_pchlan(hw);  in e1000_init_phy_params_pchlan()
456 	if (phy->id == e1000_phy_unknown)  in e1000_init_phy_params_pchlan()
457 		switch (hw->mac.type) {  in e1000_init_phy_params_pchlan()
459 			ret_val = e1000e_get_phy_id(hw);  in e1000_init_phy_params_pchlan()
462 			if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))  in e1000_init_phy_params_pchlan()
478 			ret_val = e1000_set_mdio_slow_mode_hv(hw);  in e1000_init_phy_params_pchlan()
481 			ret_val = e1000e_get_phy_id(hw);  in e1000_init_phy_params_pchlan()
486 	phy->type = e1000e_get_phy_type_from_id(phy->id);  in e1000_init_phy_params_pchlan()
488 	switch (phy->type) {  in e1000_init_phy_params_pchlan()
492 		phy->ops.check_polarity = e1000_check_polarity_82577;  in e1000_init_phy_params_pchlan()
493 		phy->ops.force_speed_duplex =  in e1000_init_phy_params_pchlan()
495 		phy->ops.get_cable_length = e1000_get_cable_length_82577;  in e1000_init_phy_params_pchlan()
496 		phy->ops.get_info = e1000_get_phy_info_82577;  in e1000_init_phy_params_pchlan()
497 		phy->ops.commit = e1000e_phy_sw_reset;  in e1000_init_phy_params_pchlan()
500 		phy->ops.check_polarity = e1000_check_polarity_m88;  in e1000_init_phy_params_pchlan()
501 		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;  in e1000_init_phy_params_pchlan()
502 		phy->ops.get_cable_length = e1000e_get_cable_length_m88;  in e1000_init_phy_params_pchlan()
503 		phy->ops.get_info = e1000e_get_phy_info_m88;  in e1000_init_phy_params_pchlan()
506 		ret_val = -E1000_ERR_PHY;  in e1000_init_phy_params_pchlan()
514  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
515  *  @hw: pointer to the HW structure
517  *  Initialize family-specific PHY parameters and function pointers.
519 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)  in e1000_init_phy_params_ich8lan()  argument
521 	struct e1000_phy_info *phy = &hw->phy;  in e1000_init_phy_params_ich8lan()
525 	phy->addr = 1;  in e1000_init_phy_params_ich8lan()
526 	phy->reset_delay_us = 100;  in e1000_init_phy_params_ich8lan()
528 	phy->ops.power_up = e1000_power_up_phy_copper;  in e1000_init_phy_params_ich8lan()
529 	phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;  in e1000_init_phy_params_ich8lan()
531 	/* We may need to do this twice - once for IGP and if that fails,  in e1000_init_phy_params_ich8lan()
534 	ret_val = e1000e_determine_phy_address(hw);  in e1000_init_phy_params_ich8lan()
536 		phy->ops.write_reg = e1000e_write_phy_reg_bm;  in e1000_init_phy_params_ich8lan()
537 		phy->ops.read_reg = e1000e_read_phy_reg_bm;  in e1000_init_phy_params_ich8lan()
538 		ret_val = e1000e_determine_phy_address(hw);  in e1000_init_phy_params_ich8lan()
545 	phy->id = 0;  in e1000_init_phy_params_ich8lan()
546 	while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&  in e1000_init_phy_params_ich8lan()
549 		ret_val = e1000e_get_phy_id(hw);  in e1000_init_phy_params_ich8lan()
555 	switch (phy->id) {  in e1000_init_phy_params_ich8lan()
557 		phy->type = e1000_phy_igp_3;  in e1000_init_phy_params_ich8lan()
558 		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;  in e1000_init_phy_params_ich8lan()
559 		phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;  in e1000_init_phy_params_ich8lan()
560 		phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;  in e1000_init_phy_params_ich8lan()
561 		phy->ops.get_info = e1000e_get_phy_info_igp;  in e1000_init_phy_params_ich8lan()
562 		phy->ops.check_polarity = e1000_check_polarity_igp;  in e1000_init_phy_params_ich8lan()
563 		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;  in e1000_init_phy_params_ich8lan()
568 		phy->type = e1000_phy_ife;  in e1000_init_phy_params_ich8lan()
569 		phy->autoneg_mask = E1000_ALL_NOT_GIG;  in e1000_init_phy_params_ich8lan()
570 		phy->ops.get_info = e1000_get_phy_info_ife;  in e1000_init_phy_params_ich8lan()
571 		phy->ops.check_polarity = e1000_check_polarity_ife;  in e1000_init_phy_params_ich8lan()
572 		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;  in e1000_init_phy_params_ich8lan()
575 		phy->type = e1000_phy_bm;  in e1000_init_phy_params_ich8lan()
576 		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;  in e1000_init_phy_params_ich8lan()
577 		phy->ops.read_reg = e1000e_read_phy_reg_bm;  in e1000_init_phy_params_ich8lan()
578 		phy->ops.write_reg = e1000e_write_phy_reg_bm;  in e1000_init_phy_params_ich8lan()
579 		phy->ops.commit = e1000e_phy_sw_reset;  in e1000_init_phy_params_ich8lan()
580 		phy->ops.get_info = e1000e_get_phy_info_m88;  in e1000_init_phy_params_ich8lan()
581 		phy->ops.check_polarity = e1000_check_polarity_m88;  in e1000_init_phy_params_ich8lan()
582 		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;  in e1000_init_phy_params_ich8lan()
585 		return -E1000_ERR_PHY;  in e1000_init_phy_params_ich8lan()
592  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
593  *  @hw: pointer to the HW structure
595  *  Initialize family-specific NVM parameters and function
598 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)  in e1000_init_nvm_params_ich8lan()  argument
600 	struct e1000_nvm_info *nvm = &hw->nvm;  in e1000_init_nvm_params_ich8lan()
601 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;  in e1000_init_nvm_params_ich8lan()
606 	nvm->type = e1000_nvm_flash_sw;  in e1000_init_nvm_params_ich8lan()
608 	if (hw->mac.type >= e1000_pch_spt) {  in e1000_init_nvm_params_ich8lan()
615 		nvm->flash_base_addr = 0;  in e1000_init_nvm_params_ich8lan()
618 		nvm->flash_bank_size = nvm_size / 2;  in e1000_init_nvm_params_ich8lan()
620 		nvm->flash_bank_size /= sizeof(u16);  in e1000_init_nvm_params_ich8lan()
622 		hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;  in e1000_init_nvm_params_ich8lan()
625 		if (!hw->flash_address) {  in e1000_init_nvm_params_ich8lan()
627 			return -E1000_ERR_CONFIG;  in e1000_init_nvm_params_ich8lan()
632 		/* sector_X_addr is a "sector"-aligned address (4096 bytes)  in e1000_init_nvm_params_ich8lan()
639 		/* flash_base_addr is byte-aligned */  in e1000_init_nvm_params_ich8lan()
640 		nvm->flash_base_addr = sector_base_addr  in e1000_init_nvm_params_ich8lan()
646 		nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)  in e1000_init_nvm_params_ich8lan()
648 		nvm->flash_bank_size /= 2;  in e1000_init_nvm_params_ich8lan()
650 		nvm->flash_bank_size /= sizeof(u16);  in e1000_init_nvm_params_ich8lan()
653 	nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;  in e1000_init_nvm_params_ich8lan()
656 	for (i = 0; i < nvm->word_size; i++) {  in e1000_init_nvm_params_ich8lan()
657 		dev_spec->shadow_ram[i].modified = false;  in e1000_init_nvm_params_ich8lan()
658 		dev_spec->shadow_ram[i].value = 0xFFFF;  in e1000_init_nvm_params_ich8lan()
665  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
666  *  @hw: pointer to the HW structure
668  *  Initialize family-specific MAC parameters and function
671 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)  in e1000_init_mac_params_ich8lan()  argument
673 	struct e1000_mac_info *mac = &hw->mac;  in e1000_init_mac_params_ich8lan()
676 	hw->phy.media_type = e1000_media_type_copper;  in e1000_init_mac_params_ich8lan()
679 	mac->mta_reg_count = 32;  in e1000_init_mac_params_ich8lan()
681 	mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;  in e1000_init_mac_params_ich8lan()
682 	if (mac->type == e1000_ich8lan)  in e1000_init_mac_params_ich8lan()
683 		mac->rar_entry_count--;  in e1000_init_mac_params_ich8lan()
685 	mac->has_fwsm = true;  in e1000_init_mac_params_ich8lan()
687 	mac->arc_subsystem_valid = false;  in e1000_init_mac_params_ich8lan()
689 	mac->adaptive_ifs = true;  in e1000_init_mac_params_ich8lan()
692 	switch (mac->type) {  in e1000_init_mac_params_ich8lan()
697 		mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;  in e1000_init_mac_params_ich8lan()
699 		mac->ops.id_led_init = e1000e_id_led_init_generic;  in e1000_init_mac_params_ich8lan()
701 		mac->ops.blink_led = e1000e_blink_led_generic;  in e1000_init_mac_params_ich8lan()
703 		mac->ops.setup_led = e1000e_setup_led_generic;  in e1000_init_mac_params_ich8lan()
705 		mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;  in e1000_init_mac_params_ich8lan()
707 		mac->ops.led_on = e1000_led_on_ich8lan;  in e1000_init_mac_params_ich8lan()
708 		mac->ops.led_off = e1000_led_off_ich8lan;  in e1000_init_mac_params_ich8lan()
711 		mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;  in e1000_init_mac_params_ich8lan()
712 		mac->ops.rar_set = e1000_rar_set_pch2lan;  in e1000_init_mac_params_ich8lan()
725 		mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;  in e1000_init_mac_params_ich8lan()
727 		mac->ops.id_led_init = e1000_id_led_init_pchlan;  in e1000_init_mac_params_ich8lan()
729 		mac->ops.setup_led = e1000_setup_led_pchlan;  in e1000_init_mac_params_ich8lan()
731 		mac->ops.cleanup_led = e1000_cleanup_led_pchlan;  in e1000_init_mac_params_ich8lan()
733 		mac->ops.led_on = e1000_led_on_pchlan;  in e1000_init_mac_params_ich8lan()
734 		mac->ops.led_off = e1000_led_off_pchlan;  in e1000_init_mac_params_ich8lan()
740 	if (mac->type >= e1000_pch_lpt) {  in e1000_init_mac_params_ich8lan()
741 		mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;  in e1000_init_mac_params_ich8lan()
742 		mac->ops.rar_set = e1000_rar_set_pch_lpt;  in e1000_init_mac_params_ich8lan()
743 		mac->ops.setup_physical_interface =  in e1000_init_mac_params_ich8lan()
745 		mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt;  in e1000_init_mac_params_ich8lan()
748 	/* Enable PCS Lock-loss workaround for ICH8 */  in e1000_init_mac_params_ich8lan()
749 	if (mac->type == e1000_ich8lan)  in e1000_init_mac_params_ich8lan()
750 		e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);  in e1000_init_mac_params_ich8lan()
756  *  __e1000_access_emi_reg_locked - Read/write EMI register
757  *  @hw: pointer to the HW structure
762  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
764 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,  in __e1000_access_emi_reg_locked()  argument
769 	ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);  in __e1000_access_emi_reg_locked()
774 		ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);  in __e1000_access_emi_reg_locked()
776 		ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);  in __e1000_access_emi_reg_locked()
782  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
783  *  @hw: pointer to the HW structure
787  *  Assumes the SW/FW/HW Semaphore is already acquired.
789 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)  in e1000_read_emi_reg_locked()  argument
791 	return __e1000_access_emi_reg_locked(hw, addr, data, true);  in e1000_read_emi_reg_locked()
795  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
796  *  @hw: pointer to the HW structure
800  *  Assumes the SW/FW/HW Semaphore is already acquired.
802 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)  in e1000_write_emi_reg_locked()  argument
804 	return __e1000_access_emi_reg_locked(hw, addr, &data, false);  in e1000_write_emi_reg_locked()
808  *  e1000_set_eee_pchlan - Enable/disable EEE support
809  *  @hw: pointer to the HW structure
821 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)  in e1000_set_eee_pchlan()  argument
823 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;  in e1000_set_eee_pchlan()
827 	switch (hw->phy.type) {  in e1000_set_eee_pchlan()
842 	ret_val = hw->phy.ops.acquire(hw);  in e1000_set_eee_pchlan()
846 	ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);  in e1000_set_eee_pchlan()
854 	if (!dev_spec->eee_disable) {  in e1000_set_eee_pchlan()
856 		ret_val = e1000_read_emi_reg_locked(hw, lpa,  in e1000_set_eee_pchlan()
857 						    &dev_spec->eee_lp_ability);  in e1000_set_eee_pchlan()
862 		ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);  in e1000_set_eee_pchlan()
869 		if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)  in e1000_set_eee_pchlan()
872 		if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {  in e1000_set_eee_pchlan()
873 			e1e_rphy_locked(hw, MII_LPA, &data);  in e1000_set_eee_pchlan()
878 				 * partner's EEE in 100 ability if full-duplex  in e1000_set_eee_pchlan()
881 				dev_spec->eee_lp_ability &=  in e1000_set_eee_pchlan()
886 	if (hw->phy.type == e1000_phy_82579) {  in e1000_set_eee_pchlan()
887 		ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,  in e1000_set_eee_pchlan()
893 		ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,  in e1000_set_eee_pchlan()
897 	/* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */  in e1000_set_eee_pchlan()
898 	ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);  in e1000_set_eee_pchlan()
902 	ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);  in e1000_set_eee_pchlan()
904 	hw->phy.ops.release(hw);  in e1000_set_eee_pchlan()
910  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
911  *  @hw:   pointer to the HW structure
916  *  the de-assertion of the clock request when in 1Gpbs mode.
917  *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
920 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)  in e1000_k1_workaround_lpt_lp()  argument
928 		ret_val = hw->phy.ops.acquire(hw);  in e1000_k1_workaround_lpt_lp()
933 		    e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,  in e1000_k1_workaround_lpt_lp()
939 		    e1000e_write_kmrn_reg_locked(hw,  in e1000_k1_workaround_lpt_lp()
951 		    e1000e_write_kmrn_reg_locked(hw,  in e1000_k1_workaround_lpt_lp()
955 		hw->phy.ops.release(hw);  in e1000_k1_workaround_lpt_lp()
960 		if ((hw->phy.revision > 5) || !link ||  in e1000_k1_workaround_lpt_lp()
965 		ret_val = e1e_rphy(hw, I217_INBAND_CTRL, &reg);  in e1000_k1_workaround_lpt_lp()
987 		ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);  in e1000_k1_workaround_lpt_lp()
999  *  e1000_platform_pm_pch_lpt - Set platform power management values
1000  *  @hw: pointer to the HW structure
1003  *  Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
1007  *  Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
1010  *  equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1011  *  set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1014 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)  in e1000_platform_pm_pch_lpt()  argument
1029 		if (!hw->adapter->max_frame_size) {  in e1000_platform_pm_pch_lpt()
1031 			return -E1000_ERR_CONFIG;  in e1000_platform_pm_pch_lpt()
1034 		hw->mac.ops.get_link_up_info(hw, &speed, &duplex);  in e1000_platform_pm_pch_lpt()
1037 			return -E1000_ERR_CONFIG;  in e1000_platform_pm_pch_lpt()
1046 		 * a 3-bit encoded scale (only 0-5 are valid) multiplied by  in e1000_platform_pm_pch_lpt()
1047 		 * a 10-bit value (0-1023) to provide a range from 1 ns to  in e1000_platform_pm_pch_lpt()
1048 		 * 2^25*(2^10-1) ns.  The scale is encoded as 0=2^0ns,  in e1000_platform_pm_pch_lpt()
1052 		value = (rxa > hw->adapter->max_frame_size) ?  in e1000_platform_pm_pch_lpt()
1053 			(rxa - hw->adapter->max_frame_size) * (16000 / speed) :  in e1000_platform_pm_pch_lpt()
1062 			return -E1000_ERR_CONFIG;  in e1000_platform_pm_pch_lpt()
1067 		pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,  in e1000_platform_pm_pch_lpt()
1069 		pci_read_config_word(hw->adapter->pdev,  in e1000_platform_pm_pch_lpt()
1085 	/* Set Snoop and No-Snoop latencies the same */  in e1000_platform_pm_pch_lpt()
1093  *  e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1094  *  @hw: pointer to the HW structure
1102 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)  in e1000_enable_ulp_lpt_lp()  argument
1109 	if ((hw->mac.type < e1000_pch_lpt) ||  in e1000_enable_ulp_lpt_lp()
1110 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||  in e1000_enable_ulp_lpt_lp()
1111 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||  in e1000_enable_ulp_lpt_lp()
1112 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||  in e1000_enable_ulp_lpt_lp()
1113 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||  in e1000_enable_ulp_lpt_lp()
1114 	    (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))  in e1000_enable_ulp_lpt_lp()
1131 			/* Bail if link is re-acquired */  in e1000_enable_ulp_lpt_lp()
1133 				return -E1000_ERR_PHY;  in e1000_enable_ulp_lpt_lp()
1145 	ret_val = hw->phy.ops.acquire(hw);  in e1000_enable_ulp_lpt_lp()
1150 	ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);  in e1000_enable_ulp_lpt_lp()
1154 	e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);  in e1000_enable_ulp_lpt_lp()
1161 	/* Si workaround for ULP entry flow on i127/rev6 h/w.  Enable  in e1000_enable_ulp_lpt_lp()
1164 	if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {  in e1000_enable_ulp_lpt_lp()
1165 		ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,  in e1000_enable_ulp_lpt_lp()
1173 		ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,  in e1000_enable_ulp_lpt_lp()
1183 	ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);  in e1000_enable_ulp_lpt_lp()
1201 	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);  in e1000_enable_ulp_lpt_lp()
1210 	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);  in e1000_enable_ulp_lpt_lp()
1212 	if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&  in e1000_enable_ulp_lpt_lp()
1214 		ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,  in e1000_enable_ulp_lpt_lp()
1221 	hw->phy.ops.release(hw);  in e1000_enable_ulp_lpt_lp()
1224 		e_dbg("Error in ULP enable flow: %d\n", ret_val);  in e1000_enable_ulp_lpt_lp()
1226 		hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;  in e1000_enable_ulp_lpt_lp()
1232  *  e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1233  *  @hw: pointer to the HW structure
1236  *  Un-configure ULP mode when link is up, the system is transitioned from
1238  *  system, poll for an indication from ME that ULP has been un-configured.
1239  *  If not on an ME enabled system, un-configure the ULP mode by software.
1243  *  the driver or during Sx->S0 transitions, this is called with force=true
1246 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)  in e1000_disable_ulp_lpt_lp()  argument
1253 	if ((hw->mac.type < e1000_pch_lpt) ||  in e1000_disable_ulp_lpt_lp()
1254 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||  in e1000_disable_ulp_lpt_lp()
1255 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||  in e1000_disable_ulp_lpt_lp()
1256 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||  in e1000_disable_ulp_lpt_lp()
1257 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||  in e1000_disable_ulp_lpt_lp()
1258 	    (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))  in e1000_disable_ulp_lpt_lp()
1262 		struct e1000_adapter *adapter = hw->adapter;  in e1000_disable_ulp_lpt_lp()
1266 			/* Request ME un-configure ULP mode in the PHY */  in e1000_disable_ulp_lpt_lp()
1279 				ret_val = -E1000_ERR_PHY;  in e1000_disable_ulp_lpt_lp()
1308 	ret_val = hw->phy.ops.acquire(hw);  in e1000_disable_ulp_lpt_lp()
1314 		e1000_toggle_lanphypc_pch_lpt(hw);  in e1000_disable_ulp_lpt_lp()
1317 	ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);  in e1000_disable_ulp_lpt_lp()
1328 		ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,  in e1000_disable_ulp_lpt_lp()
1334 	e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);  in e1000_disable_ulp_lpt_lp()
1342 	 * hardware.  Re-Enable K1 in the PHY when exiting ULP.  in e1000_disable_ulp_lpt_lp()
1344 	ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);  in e1000_disable_ulp_lpt_lp()
1348 	e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);  in e1000_disable_ulp_lpt_lp()
1351 	ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);  in e1000_disable_ulp_lpt_lp()
1362 	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);  in e1000_disable_ulp_lpt_lp()
1366 	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);  in e1000_disable_ulp_lpt_lp()
1374 	hw->phy.ops.release(hw);  in e1000_disable_ulp_lpt_lp()
1376 		e1000_phy_hw_reset(hw);  in e1000_disable_ulp_lpt_lp()
1381 		e_dbg("Error in ULP disable flow: %d\n", ret_val);  in e1000_disable_ulp_lpt_lp()
1383 		hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;  in e1000_disable_ulp_lpt_lp()
1389  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1390  *  @hw: pointer to the HW structure
1396 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)  in e1000_check_for_copper_link_ich8lan()  argument
1398 	struct e1000_mac_info *mac = &hw->mac;  in e1000_check_for_copper_link_ich8lan()
1404 	/* We only want to go out to the PHY registers to see if Auto-Neg  in e1000_check_for_copper_link_ich8lan()
1409 	if (!mac->get_link_status)  in e1000_check_for_copper_link_ich8lan()
1411 	mac->get_link_status = false;  in e1000_check_for_copper_link_ich8lan()
1417 	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);  in e1000_check_for_copper_link_ich8lan()
1421 	if (hw->mac.type == e1000_pchlan) {  in e1000_check_for_copper_link_ich8lan()
1422 		ret_val = e1000_k1_gig_workaround_hv(hw, link);  in e1000_check_for_copper_link_ich8lan()
1427 	/* When connected at 10Mbps half-duplex, some parts are excessively  in e1000_check_for_copper_link_ich8lan()
1431 	if ((hw->mac.type >= e1000_pch2lan) && link) {  in e1000_check_for_copper_link_ich8lan()
1434 		e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex);  in e1000_check_for_copper_link_ich8lan()
1442 		} else if (hw->mac.type >= e1000_pch_spt &&  in e1000_check_for_copper_link_ich8lan()
1455 		ret_val = hw->phy.ops.acquire(hw);  in e1000_check_for_copper_link_ich8lan()
1459 		if (hw->mac.type == e1000_pch2lan)  in e1000_check_for_copper_link_ich8lan()
1463 		ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);  in e1000_check_for_copper_link_ich8lan()
1465 		if (hw->mac.type >= e1000_pch_lpt) {  in e1000_check_for_copper_link_ich8lan()
1468 			e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg);  in e1000_check_for_copper_link_ich8lan()
1474 			e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg);  in e1000_check_for_copper_link_ich8lan()
1477 				hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,  in e1000_check_for_copper_link_ich8lan()
1482 				hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,  in e1000_check_for_copper_link_ich8lan()
1486 		hw->phy.ops.release(hw);  in e1000_check_for_copper_link_ich8lan()
1491 		if (hw->mac.type >= e1000_pch_spt) {  in e1000_check_for_copper_link_ich8lan()
1496 				ret_val = hw->phy.ops.acquire(hw);  in e1000_check_for_copper_link_ich8lan()
1500 				ret_val = e1e_rphy_locked(hw,  in e1000_check_for_copper_link_ich8lan()
1504 					hw->phy.ops.release(hw);  in e1000_check_for_copper_link_ich8lan()
1513 					    e1e_wphy_locked(hw,  in e1000_check_for_copper_link_ich8lan()
1517 				hw->phy.ops.release(hw);  in e1000_check_for_copper_link_ich8lan()
1521 				ret_val = hw->phy.ops.acquire(hw);  in e1000_check_for_copper_link_ich8lan()
1525 				ret_val = e1e_wphy_locked(hw,  in e1000_check_for_copper_link_ich8lan()
1528 				hw->phy.ops.release(hw);  in e1000_check_for_copper_link_ich8lan()
1541 	if (hw->mac.type >= e1000_pch_lpt) {  in e1000_check_for_copper_link_ich8lan()
1550 	/* Work-around I218 hang issue */  in e1000_check_for_copper_link_ich8lan()
1551 	if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||  in e1000_check_for_copper_link_ich8lan()
1552 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||  in e1000_check_for_copper_link_ich8lan()
1553 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||  in e1000_check_for_copper_link_ich8lan()
1554 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {  in e1000_check_for_copper_link_ich8lan()
1555 		ret_val = e1000_k1_workaround_lpt_lp(hw, link);  in e1000_check_for_copper_link_ich8lan()
1559 	if (hw->mac.type >= e1000_pch_lpt) {  in e1000_check_for_copper_link_ich8lan()
1563 		ret_val = e1000_platform_pm_pch_lpt(hw, link);  in e1000_check_for_copper_link_ich8lan()
1569 	hw->dev_spec.ich8lan.eee_lp_ability = 0;  in e1000_check_for_copper_link_ich8lan()
1571 	if (hw->mac.type >= e1000_pch_lpt) {  in e1000_check_for_copper_link_ich8lan()
1574 		if (hw->mac.type == e1000_pch_spt) {  in e1000_check_for_copper_link_ich8lan()
1575 			/* FEXTNVM6 K1-off workaround - for SPT only */  in e1000_check_for_copper_link_ich8lan()
1590 	switch (hw->mac.type) {  in e1000_check_for_copper_link_ich8lan()
1592 		ret_val = e1000_k1_workaround_lv(hw);  in e1000_check_for_copper_link_ich8lan()
1597 		if (hw->phy.type == e1000_phy_82578) {  in e1000_check_for_copper_link_ich8lan()
1598 			ret_val = e1000_link_stall_workaround_hv(hw);  in e1000_check_for_copper_link_ich8lan()
1603 		/* Workaround for PCHx parts in half-duplex:  in e1000_check_for_copper_link_ich8lan()
1608 		e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);  in e1000_check_for_copper_link_ich8lan()
1614 		e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);  in e1000_check_for_copper_link_ich8lan()
1621 	 * immediately after link-up  in e1000_check_for_copper_link_ich8lan()
1623 	e1000e_check_downshift(hw);  in e1000_check_for_copper_link_ich8lan()
1626 	if (hw->phy.type > e1000_phy_82579) {  in e1000_check_for_copper_link_ich8lan()
1627 		ret_val = e1000_set_eee_pchlan(hw);  in e1000_check_for_copper_link_ich8lan()
1635 	if (!mac->autoneg)  in e1000_check_for_copper_link_ich8lan()
1636 		return -E1000_ERR_CONFIG;  in e1000_check_for_copper_link_ich8lan()
1638 	/* Auto-Neg is enabled.  Auto Speed Detection takes care  in e1000_check_for_copper_link_ich8lan()
1642 	mac->ops.config_collision_dist(hw);  in e1000_check_for_copper_link_ich8lan()
1644 	/* Configure Flow Control now that Auto-Neg has completed.  in e1000_check_for_copper_link_ich8lan()
1645 	 * First, we need to restore the desired flow control  in e1000_check_for_copper_link_ich8lan()
1646 	 * settings because we may have had to re-autoneg with a  in e1000_check_for_copper_link_ich8lan()
1649 	ret_val = e1000e_config_fc_after_link_up(hw);  in e1000_check_for_copper_link_ich8lan()
1651 		e_dbg("Error configuring flow control\n");  in e1000_check_for_copper_link_ich8lan()
1656 	mac->get_link_status = true;  in e1000_check_for_copper_link_ich8lan()
1662 	struct e1000_hw *hw = &adapter->hw;  in e1000_get_variants_ich8lan()  local
1665 	rc = e1000_init_mac_params_ich8lan(hw);  in e1000_get_variants_ich8lan()
1669 	rc = e1000_init_nvm_params_ich8lan(hw);  in e1000_get_variants_ich8lan()
1673 	switch (hw->mac.type) {  in e1000_get_variants_ich8lan()
1677 		rc = e1000_init_phy_params_ich8lan(hw);  in e1000_get_variants_ich8lan()
1690 		rc = e1000_init_phy_params_pchlan(hw);  in e1000_get_variants_ich8lan()
1701 	if ((adapter->hw.phy.type == e1000_phy_ife) ||  in e1000_get_variants_ich8lan()
1702 	    ((adapter->hw.mac.type >= e1000_pch2lan) &&  in e1000_get_variants_ich8lan()
1704 		adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;  in e1000_get_variants_ich8lan()
1705 		adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;  in e1000_get_variants_ich8lan()
1707 		hw->mac.ops.blink_led = NULL;  in e1000_get_variants_ich8lan()
1710 	if ((adapter->hw.mac.type == e1000_ich8lan) &&  in e1000_get_variants_ich8lan()
1711 	    (adapter->hw.phy.type != e1000_phy_ife))  in e1000_get_variants_ich8lan()
1712 		adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;  in e1000_get_variants_ich8lan()
1715 	if ((adapter->hw.mac.type == e1000_pch2lan) &&  in e1000_get_variants_ich8lan()
1717 		adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;  in e1000_get_variants_ich8lan()
1725  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1726  *  @hw: pointer to the HW structure
1730 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)  in e1000_acquire_nvm_ich8lan()  argument
1738  *  e1000_release_nvm_ich8lan - Release NVM mutex
1739  *  @hw: pointer to the HW structure
1743 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)  in e1000_release_nvm_ich8lan()  argument
1749  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
1750  *  @hw: pointer to the HW structure
1755 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)  in e1000_acquire_swflag_ich8lan()  argument
1761 			     &hw->adapter->state)) {  in e1000_acquire_swflag_ich8lan()
1763 		return -E1000_ERR_PHY;  in e1000_acquire_swflag_ich8lan()
1772 		timeout--;  in e1000_acquire_swflag_ich8lan()
1777 		ret_val = -E1000_ERR_CONFIG;  in e1000_acquire_swflag_ich8lan()
1792 		timeout--;  in e1000_acquire_swflag_ich8lan()
1796 		e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",  in e1000_acquire_swflag_ich8lan()
1800 		ret_val = -E1000_ERR_CONFIG;  in e1000_acquire_swflag_ich8lan()
1806 		clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);  in e1000_acquire_swflag_ich8lan()
1812  *  e1000_release_swflag_ich8lan - Release software control flag
1813  *  @hw: pointer to the HW structure
1818 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)  in e1000_release_swflag_ich8lan()  argument
1828 		e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");  in e1000_release_swflag_ich8lan()
1831 	clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);  in e1000_release_swflag_ich8lan()
1835  *  e1000_check_mng_mode_ich8lan - Checks management mode
1836  *  @hw: pointer to the HW structure
1842 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)  in e1000_check_mng_mode_ich8lan()  argument
1853  *  e1000_check_mng_mode_pchlan - Checks management mode
1854  *  @hw: pointer to the HW structure
1860 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)  in e1000_check_mng_mode_pchlan()  argument
1870  *  e1000_rar_set_pch2lan - Set receive address register
1871  *  @hw: pointer to the HW structure
1877  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1878  *  Use SHRA[0-3] in place of those reserved for ME.
1880 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)  in e1000_rar_set_pch2lan()  argument
1884 	/* HW expects these in little endian so we reverse the byte order  in e1000_rar_set_pch2lan()
1905 	/* RAR[1-6] are owned by manageability.  Skip those and program the  in e1000_rar_set_pch2lan()
1908 	if (index < (u32)(hw->mac.rar_entry_count)) {  in e1000_rar_set_pch2lan()
1911 		ret_val = e1000_acquire_swflag_ich8lan(hw);  in e1000_rar_set_pch2lan()
1915 		ew32(SHRAL(index - 1), rar_low);  in e1000_rar_set_pch2lan()
1917 		ew32(SHRAH(index - 1), rar_high);  in e1000_rar_set_pch2lan()
1920 		e1000_release_swflag_ich8lan(hw);  in e1000_rar_set_pch2lan()
1923 		if ((er32(SHRAL(index - 1)) == rar_low) &&  in e1000_rar_set_pch2lan()
1924 		    (er32(SHRAH(index - 1)) == rar_high))  in e1000_rar_set_pch2lan()
1927 		e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",  in e1000_rar_set_pch2lan()
1928 		      (index - 1), er32(FWSM));  in e1000_rar_set_pch2lan()
1933 	return -E1000_ERR_CONFIG;  in e1000_rar_set_pch2lan()
1937  *  e1000_rar_get_count_pch_lpt - Get the number of available SHRA
1938  *  @hw: pointer to the HW structure
1941  *  program. SHRA[0-10] are the shared receive address registers
1946 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw)  in e1000_rar_get_count_pch_lpt()  argument
1957 		num_entries = hw->mac.rar_entry_count;  in e1000_rar_get_count_pch_lpt()
1964 		/* SHRA[0..(wlock_mac - 1)] available + RAR[0] */  in e1000_rar_get_count_pch_lpt()
1973  *  e1000_rar_set_pch_lpt - Set receive address registers
1974  *  @hw: pointer to the HW structure
1980  *  contain the MAC address. SHRA[0-10] are the shared receive address
1983 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)  in e1000_rar_set_pch_lpt()  argument
1988 	/* HW expects these in little endian so we reverse the byte order  in e1000_rar_set_pch_lpt()
2009 	 * it is using - those registers are unavailable for use.  in e1000_rar_set_pch_lpt()
2011 	if (index < hw->mac.rar_entry_count) {  in e1000_rar_set_pch_lpt()
2022 			ret_val = e1000_acquire_swflag_ich8lan(hw);  in e1000_rar_set_pch_lpt()
2027 			ew32(SHRAL_PCH_LPT(index - 1), rar_low);  in e1000_rar_set_pch_lpt()
2029 			ew32(SHRAH_PCH_LPT(index - 1), rar_high);  in e1000_rar_set_pch_lpt()
2032 			e1000_release_swflag_ich8lan(hw);  in e1000_rar_set_pch_lpt()
2035 			if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&  in e1000_rar_set_pch_lpt()
2036 			    (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))  in e1000_rar_set_pch_lpt()
2043 	return -E1000_ERR_CONFIG;  in e1000_rar_set_pch_lpt()
2047  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2048  *  @hw: pointer to the HW structure
2054 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)  in e1000_check_reset_block_ich8lan()  argument
2066  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2067  *  @hw: pointer to the HW structure
2072 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)  in e1000_write_smbus_addr()  argument
2081 	ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);  in e1000_write_smbus_addr()
2089 	if (hw->phy.type == e1000_phy_i217) {  in e1000_write_smbus_addr()
2091 		if (freq--) {  in e1000_write_smbus_addr()
2096 			    (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);  in e1000_write_smbus_addr()
2102 	return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);  in e1000_write_smbus_addr()
2106  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2107  *  @hw:   pointer to the HW structure
2112 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)  in e1000_sw_lcd_config_ich8lan()  argument
2114 	struct e1000_phy_info *phy = &hw->phy;  in e1000_sw_lcd_config_ich8lan()
2125 	switch (hw->mac.type) {  in e1000_sw_lcd_config_ich8lan()
2127 		if (phy->type != e1000_phy_igp_3)  in e1000_sw_lcd_config_ich8lan()
2130 		if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||  in e1000_sw_lcd_config_ich8lan()
2131 		    (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {  in e1000_sw_lcd_config_ich8lan()
2153 	ret_val = hw->phy.ops.acquire(hw);  in e1000_sw_lcd_config_ich8lan()
2161 	/* Make sure HW does not configure LCD from PHY  in e1000_sw_lcd_config_ich8lan()
2165 	if ((hw->mac.type < e1000_pch2lan) &&  in e1000_sw_lcd_config_ich8lan()
2178 	if (((hw->mac.type == e1000_pchlan) &&  in e1000_sw_lcd_config_ich8lan()
2180 	    (hw->mac.type > e1000_pchlan)) {  in e1000_sw_lcd_config_ich8lan()
2181 		/* HW configures the SMBus address and LEDs when the  in e1000_sw_lcd_config_ich8lan()
2186 		ret_val = e1000_write_smbus_addr(hw);  in e1000_sw_lcd_config_ich8lan()
2191 		ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,  in e1000_sw_lcd_config_ich8lan()
2203 		ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, &reg_data);  in e1000_sw_lcd_config_ich8lan()
2207 		ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),  in e1000_sw_lcd_config_ich8lan()
2221 		ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);  in e1000_sw_lcd_config_ich8lan()
2227 	hw->phy.ops.release(hw);  in e1000_sw_lcd_config_ich8lan()
2232  *  e1000_k1_gig_workaround_hv - K1 Si workaround
2233  *  @hw:   pointer to the HW structure
2241 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)  in e1000_k1_gig_workaround_hv()  argument
2245 	bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;  in e1000_k1_gig_workaround_hv()
2247 	if (hw->mac.type != e1000_pchlan)  in e1000_k1_gig_workaround_hv()
2250 	/* Wrap the whole flow with the sw flag */  in e1000_k1_gig_workaround_hv()
2251 	ret_val = hw->phy.ops.acquire(hw);  in e1000_k1_gig_workaround_hv()
2257 		if (hw->phy.type == e1000_phy_82578) {  in e1000_k1_gig_workaround_hv()
2258 			ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,  in e1000_k1_gig_workaround_hv()
2273 		if (hw->phy.type == e1000_phy_82577) {  in e1000_k1_gig_workaround_hv()
2274 			ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);  in e1000_k1_gig_workaround_hv()
2289 		ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);  in e1000_k1_gig_workaround_hv()
2295 		ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);  in e1000_k1_gig_workaround_hv()
2300 	ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);  in e1000_k1_gig_workaround_hv()
2303 	hw->phy.ops.release(hw);  in e1000_k1_gig_workaround_hv()
2309  *  e1000_configure_k1_ich8lan - Configure K1 power state
2310  *  @hw: pointer to the HW structure
2316  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2318 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)  in e1000_configure_k1_ich8lan()  argument
2326 	ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,  in e1000_configure_k1_ich8lan()
2336 	ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,  in e1000_configure_k1_ich8lan()
2343 	ctrl_reg = er32(CTRL);  in e1000_configure_k1_ich8lan()
2347 	ew32(CTRL, reg);  in e1000_configure_k1_ich8lan()
2352 	ew32(CTRL, ctrl_reg);  in e1000_configure_k1_ich8lan()
2361  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2362  *  @hw:       pointer to the HW structure
2367  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
2369 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)  in e1000_oem_bits_config_ich8lan()  argument
2375 	if (hw->mac.type < e1000_pchlan)  in e1000_oem_bits_config_ich8lan()
2378 	ret_val = hw->phy.ops.acquire(hw);  in e1000_oem_bits_config_ich8lan()
2382 	if (hw->mac.type == e1000_pchlan) {  in e1000_oem_bits_config_ich8lan()
2394 	ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);  in e1000_oem_bits_config_ich8lan()
2416 	/* Set Restart auto-neg to activate the bits */  in e1000_oem_bits_config_ich8lan()
2417 	if ((d0_state || (hw->mac.type != e1000_pchlan)) &&  in e1000_oem_bits_config_ich8lan()
2418 	    !hw->phy.ops.check_reset_block(hw))  in e1000_oem_bits_config_ich8lan()
2421 	ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);  in e1000_oem_bits_config_ich8lan()
2424 	hw->phy.ops.release(hw);  in e1000_oem_bits_config_ich8lan()
2430  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2431  *  @hw:   pointer to the HW structure
2433 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)  in e1000_set_mdio_slow_mode_hv()  argument
2438 	ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);  in e1000_set_mdio_slow_mode_hv()
2444 	ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);  in e1000_set_mdio_slow_mode_hv()
2450  *  e1000_hv_phy_workarounds_ich8lan - apply PHY workarounds
2451  *  @hw: pointer to the HW structure
2455 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)  in e1000_hv_phy_workarounds_ich8lan()  argument
2460 	if (hw->mac.type != e1000_pchlan)  in e1000_hv_phy_workarounds_ich8lan()
2464 	if (hw->phy.type == e1000_phy_82577) {  in e1000_hv_phy_workarounds_ich8lan()
2465 		ret_val = e1000_set_mdio_slow_mode_hv(hw);  in e1000_hv_phy_workarounds_ich8lan()
2470 	if (((hw->phy.type == e1000_phy_82577) &&  in e1000_hv_phy_workarounds_ich8lan()
2471 	     ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||  in e1000_hv_phy_workarounds_ich8lan()
2472 	    ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {  in e1000_hv_phy_workarounds_ich8lan()
2474 		ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);  in e1000_hv_phy_workarounds_ich8lan()
2479 		ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);  in e1000_hv_phy_workarounds_ich8lan()
2484 	if (hw->phy.type == e1000_phy_82578) {  in e1000_hv_phy_workarounds_ich8lan()
2488 		if (hw->phy.revision < 2) {  in e1000_hv_phy_workarounds_ich8lan()
2489 			e1000e_phy_sw_reset(hw);  in e1000_hv_phy_workarounds_ich8lan()
2490 			ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);  in e1000_hv_phy_workarounds_ich8lan()
2497 	ret_val = hw->phy.ops.acquire(hw);  in e1000_hv_phy_workarounds_ich8lan()
2501 	hw->phy.addr = 1;  in e1000_hv_phy_workarounds_ich8lan()
2502 	ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);  in e1000_hv_phy_workarounds_ich8lan()
2503 	hw->phy.ops.release(hw);  in e1000_hv_phy_workarounds_ich8lan()
2510 	ret_val = e1000_k1_gig_workaround_hv(hw, true);  in e1000_hv_phy_workarounds_ich8lan()
2515 	ret_val = hw->phy.ops.acquire(hw);  in e1000_hv_phy_workarounds_ich8lan()
2518 	ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);  in e1000_hv_phy_workarounds_ich8lan()
2521 	ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);  in e1000_hv_phy_workarounds_ich8lan()
2526 	ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);  in e1000_hv_phy_workarounds_ich8lan()
2528 	hw->phy.ops.release(hw);  in e1000_hv_phy_workarounds_ich8lan()
2534  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2535  *  @hw:   pointer to the HW structure
2537 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)  in e1000_copy_rx_addrs_to_phy_ich8lan()  argument
2543 	ret_val = hw->phy.ops.acquire(hw);  in e1000_copy_rx_addrs_to_phy_ich8lan()
2546 	ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);  in e1000_copy_rx_addrs_to_phy_ich8lan()
2551 	for (i = 0; i < (hw->mac.rar_entry_count); i++) {  in e1000_copy_rx_addrs_to_phy_ich8lan()
2553 		hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),  in e1000_copy_rx_addrs_to_phy_ich8lan()
2555 		hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),  in e1000_copy_rx_addrs_to_phy_ich8lan()
2559 		hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),  in e1000_copy_rx_addrs_to_phy_ich8lan()
2561 		hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),  in e1000_copy_rx_addrs_to_phy_ich8lan()
2565 	e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);  in e1000_copy_rx_addrs_to_phy_ich8lan()
2568 	hw->phy.ops.release(hw);  in e1000_copy_rx_addrs_to_phy_ich8lan()
2572  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2574  *  @hw: pointer to the HW structure
2577 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)  in e1000_lv_jumbo_workaround_ich8lan()  argument
2584 	if (hw->mac.type < e1000_pch2lan)  in e1000_lv_jumbo_workaround_ich8lan()
2588 	e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);  in e1000_lv_jumbo_workaround_ich8lan()
2589 	ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14));  in e1000_lv_jumbo_workaround_ich8lan()
2597 		for (i = 0; i < hw->mac.rar_entry_count; i++) {  in e1000_lv_jumbo_workaround_ich8lan()
2616 		e1000_copy_rx_addrs_to_phy_ich8lan(hw);  in e1000_lv_jumbo_workaround_ich8lan()
2628 		ret_val = e1000e_read_kmrn_reg(hw,  in e1000_lv_jumbo_workaround_ich8lan()
2633 		ret_val = e1000e_write_kmrn_reg(hw,  in e1000_lv_jumbo_workaround_ich8lan()
2638 		ret_val = e1000e_read_kmrn_reg(hw,  in e1000_lv_jumbo_workaround_ich8lan()
2645 		ret_val = e1000e_write_kmrn_reg(hw,  in e1000_lv_jumbo_workaround_ich8lan()
2652 		e1e_rphy(hw, PHY_REG(769, 23), &data);  in e1000_lv_jumbo_workaround_ich8lan()
2655 		ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);  in e1000_lv_jumbo_workaround_ich8lan()
2658 		e1e_rphy(hw, PHY_REG(769, 16), &data);  in e1000_lv_jumbo_workaround_ich8lan()
2660 		ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);  in e1000_lv_jumbo_workaround_ich8lan()
2663 		e1e_rphy(hw, PHY_REG(776, 20), &data);  in e1000_lv_jumbo_workaround_ich8lan()
2666 		ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);  in e1000_lv_jumbo_workaround_ich8lan()
2669 		ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);  in e1000_lv_jumbo_workaround_ich8lan()
2672 		e1e_rphy(hw, HV_PM_CTRL, &data);  in e1000_lv_jumbo_workaround_ich8lan()
2673 		ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10));  in e1000_lv_jumbo_workaround_ich8lan()
2686 		ret_val = e1000e_read_kmrn_reg(hw,  in e1000_lv_jumbo_workaround_ich8lan()
2691 		ret_val = e1000e_write_kmrn_reg(hw,  in e1000_lv_jumbo_workaround_ich8lan()
2696 		ret_val = e1000e_read_kmrn_reg(hw,  in e1000_lv_jumbo_workaround_ich8lan()
2703 		ret_val = e1000e_write_kmrn_reg(hw,  in e1000_lv_jumbo_workaround_ich8lan()
2710 		e1e_rphy(hw, PHY_REG(769, 23), &data);  in e1000_lv_jumbo_workaround_ich8lan()
2712 		ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);  in e1000_lv_jumbo_workaround_ich8lan()
2715 		e1e_rphy(hw, PHY_REG(769, 16), &data);  in e1000_lv_jumbo_workaround_ich8lan()
2717 		ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);  in e1000_lv_jumbo_workaround_ich8lan()
2720 		e1e_rphy(hw, PHY_REG(776, 20), &data);  in e1000_lv_jumbo_workaround_ich8lan()
2723 		ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);  in e1000_lv_jumbo_workaround_ich8lan()
2726 		ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);  in e1000_lv_jumbo_workaround_ich8lan()
2729 		e1e_rphy(hw, HV_PM_CTRL, &data);  in e1000_lv_jumbo_workaround_ich8lan()
2730 		ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10));  in e1000_lv_jumbo_workaround_ich8lan()
2735 	/* re-enable Rx path after enabling/disabling workaround */  in e1000_lv_jumbo_workaround_ich8lan()
2736 	return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14));  in e1000_lv_jumbo_workaround_ich8lan()
2740  *  e1000_lv_phy_workarounds_ich8lan - apply ich8 specific workarounds
2741  *  @hw: pointer to the HW structure
2745 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)  in e1000_lv_phy_workarounds_ich8lan()  argument
2749 	if (hw->mac.type != e1000_pch2lan)  in e1000_lv_phy_workarounds_ich8lan()
2753 	ret_val = e1000_set_mdio_slow_mode_hv(hw);  in e1000_lv_phy_workarounds_ich8lan()
2757 	ret_val = hw->phy.ops.acquire(hw);  in e1000_lv_phy_workarounds_ich8lan()
2761 	ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);  in e1000_lv_phy_workarounds_ich8lan()
2765 	ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);  in e1000_lv_phy_workarounds_ich8lan()
2767 	hw->phy.ops.release(hw);  in e1000_lv_phy_workarounds_ich8lan()
2773  *  e1000_k1_workaround_lv - K1 Si workaround
2774  *  @hw:   pointer to the HW structure
2779 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)  in e1000_k1_workaround_lv()  argument
2784 	if (hw->mac.type != e1000_pch2lan)  in e1000_k1_workaround_lv()
2788 	ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);  in e1000_k1_workaround_lv()
2799 			ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);  in e1000_k1_workaround_lv()
2803 			ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);  in e1000_k1_workaround_lv()
2820  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2821  *  @hw:   pointer to the HW structure
2827 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)  in e1000_gate_hw_phy_config_ich8lan()  argument
2831 	if (hw->mac.type < e1000_pch2lan)  in e1000_gate_hw_phy_config_ich8lan()
2845  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
2846  *  @hw: pointer to the HW structure
2851 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)  in e1000_lan_init_done_ich8lan()  argument
2860 	} while ((!data) && --loop);  in e1000_lan_init_done_ich8lan()
2876  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2877  *  @hw: pointer to the HW structure
2879 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)  in e1000_post_phy_reset_ich8lan()  argument
2884 	if (hw->phy.ops.check_reset_block(hw))  in e1000_post_phy_reset_ich8lan()
2890 	/* Perform any necessary post-reset workarounds */  in e1000_post_phy_reset_ich8lan()
2891 	switch (hw->mac.type) {  in e1000_post_phy_reset_ich8lan()
2893 		ret_val = e1000_hv_phy_workarounds_ich8lan(hw);  in e1000_post_phy_reset_ich8lan()
2898 		ret_val = e1000_lv_phy_workarounds_ich8lan(hw);  in e1000_post_phy_reset_ich8lan()
2907 	if (hw->mac.type >= e1000_pchlan) {  in e1000_post_phy_reset_ich8lan()
2908 		e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);  in e1000_post_phy_reset_ich8lan()
2910 		e1e_wphy(hw, BM_PORT_GEN_CFG, reg);  in e1000_post_phy_reset_ich8lan()
2914 	ret_val = e1000_sw_lcd_config_ich8lan(hw);  in e1000_post_phy_reset_ich8lan()
2919 	ret_val = e1000_oem_bits_config_ich8lan(hw, true);  in e1000_post_phy_reset_ich8lan()
2921 	if (hw->mac.type == e1000_pch2lan) {  in e1000_post_phy_reset_ich8lan()
2922 		/* Ungate automatic PHY configuration on non-managed 82579 */  in e1000_post_phy_reset_ich8lan()
2925 			e1000_gate_hw_phy_config_ich8lan(hw, false);  in e1000_post_phy_reset_ich8lan()
2929 		ret_val = hw->phy.ops.acquire(hw);  in e1000_post_phy_reset_ich8lan()
2932 		ret_val = e1000_write_emi_reg_locked(hw,  in e1000_post_phy_reset_ich8lan()
2935 		hw->phy.ops.release(hw);  in e1000_post_phy_reset_ich8lan()
2942  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2943  *  @hw: pointer to the HW structure
2949 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)  in e1000_phy_hw_reset_ich8lan()  argument
2953 	/* Gate automatic PHY configuration by hardware on non-managed 82579 */  in e1000_phy_hw_reset_ich8lan()
2954 	if ((hw->mac.type == e1000_pch2lan) &&  in e1000_phy_hw_reset_ich8lan()
2956 		e1000_gate_hw_phy_config_ich8lan(hw, true);  in e1000_phy_hw_reset_ich8lan()
2958 	ret_val = e1000e_phy_hw_reset_generic(hw);  in e1000_phy_hw_reset_ich8lan()
2962 	return e1000_post_phy_reset_ich8lan(hw);  in e1000_phy_hw_reset_ich8lan()
2966  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2967  *  @hw: pointer to the HW structure
2973  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
2976 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)  in e1000_set_lplu_state_pchlan()  argument
2981 	ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);  in e1000_set_lplu_state_pchlan()
2990 	if (!hw->phy.ops.check_reset_block(hw))  in e1000_set_lplu_state_pchlan()
2993 	return e1e_wphy(hw, HV_OEM_BITS, oem_reg);  in e1000_set_lplu_state_pchlan()
2997  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2998  *  @hw: pointer to the HW structure
3009 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)  in e1000_set_d0_lplu_state_ich8lan()  argument
3011 	struct e1000_phy_info *phy = &hw->phy;  in e1000_set_d0_lplu_state_ich8lan()
3016 	if (phy->type == e1000_phy_ife)  in e1000_set_d0_lplu_state_ich8lan()
3025 		if (phy->type != e1000_phy_igp_3)  in e1000_set_d0_lplu_state_ich8lan()
3031 		if (hw->mac.type == e1000_ich8lan)  in e1000_set_d0_lplu_state_ich8lan()
3032 			e1000e_gig_downshift_workaround_ich8lan(hw);  in e1000_set_d0_lplu_state_ich8lan()
3035 		ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);  in e1000_set_d0_lplu_state_ich8lan()
3039 		ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);  in e1000_set_d0_lplu_state_ich8lan()
3046 		if (phy->type != e1000_phy_igp_3)  in e1000_set_d0_lplu_state_ich8lan()
3054 		if (phy->smart_speed == e1000_smart_speed_on) {  in e1000_set_d0_lplu_state_ich8lan()
3055 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,  in e1000_set_d0_lplu_state_ich8lan()
3061 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,  in e1000_set_d0_lplu_state_ich8lan()
3065 		} else if (phy->smart_speed == e1000_smart_speed_off) {  in e1000_set_d0_lplu_state_ich8lan()
3066 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,  in e1000_set_d0_lplu_state_ich8lan()
3072 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,  in e1000_set_d0_lplu_state_ich8lan()
3083  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3084  *  @hw: pointer to the HW structure
3095 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)  in e1000_set_d3_lplu_state_ich8lan()  argument
3097 	struct e1000_phy_info *phy = &hw->phy;  in e1000_set_d3_lplu_state_ich8lan()
3108 		if (phy->type != e1000_phy_igp_3)  in e1000_set_d3_lplu_state_ich8lan()
3116 		if (phy->smart_speed == e1000_smart_speed_on) {  in e1000_set_d3_lplu_state_ich8lan()
3117 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,  in e1000_set_d3_lplu_state_ich8lan()
3123 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,  in e1000_set_d3_lplu_state_ich8lan()
3127 		} else if (phy->smart_speed == e1000_smart_speed_off) {  in e1000_set_d3_lplu_state_ich8lan()
3128 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,  in e1000_set_d3_lplu_state_ich8lan()
3134 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,  in e1000_set_d3_lplu_state_ich8lan()
3139 	} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||  in e1000_set_d3_lplu_state_ich8lan()
3140 		   (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||  in e1000_set_d3_lplu_state_ich8lan()
3141 		   (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {  in e1000_set_d3_lplu_state_ich8lan()
3145 		if (phy->type != e1000_phy_igp_3)  in e1000_set_d3_lplu_state_ich8lan()
3151 		if (hw->mac.type == e1000_ich8lan)  in e1000_set_d3_lplu_state_ich8lan()
3152 			e1000e_gig_downshift_workaround_ich8lan(hw);  in e1000_set_d3_lplu_state_ich8lan()
3155 		ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);  in e1000_set_d3_lplu_state_ich8lan()
3160 		ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);  in e1000_set_d3_lplu_state_ich8lan()
3167  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3168  *  @hw: pointer to the HW structure
3174 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)  in e1000_valid_nvm_bank_detect_ich8lan()  argument
3177 	struct e1000_nvm_info *nvm = &hw->nvm;  in e1000_valid_nvm_bank_detect_ich8lan()
3178 	u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);  in e1000_valid_nvm_bank_detect_ich8lan()
3184 	switch (hw->mac.type) {  in e1000_valid_nvm_bank_detect_ich8lan()
3193 		bank1_offset = nvm->flash_bank_size;  in e1000_valid_nvm_bank_detect_ich8lan()
3200 		ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,  in e1000_valid_nvm_bank_detect_ich8lan()
3212 		ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +  in e1000_valid_nvm_bank_detect_ich8lan()
3225 		return -E1000_ERR_NVM;  in e1000_valid_nvm_bank_detect_ich8lan()
3238 		e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");  in e1000_valid_nvm_bank_detect_ich8lan()
3245 		ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,  in e1000_valid_nvm_bank_detect_ich8lan()
3256 		ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +  in e1000_valid_nvm_bank_detect_ich8lan()
3268 		return -E1000_ERR_NVM;  in e1000_valid_nvm_bank_detect_ich8lan()
3273  *  e1000_read_nvm_spt - NVM access for SPT
3274  *  @hw: pointer to the HW structure
3281 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,  in e1000_read_nvm_spt()  argument
3284 	struct e1000_nvm_info *nvm = &hw->nvm;  in e1000_read_nvm_spt()
3285 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;  in e1000_read_nvm_spt()
3293 	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||  in e1000_read_nvm_spt()
3296 		ret_val = -E1000_ERR_NVM;  in e1000_read_nvm_spt()
3300 	nvm->ops.acquire(hw);  in e1000_read_nvm_spt()
3302 	ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);  in e1000_read_nvm_spt()
3308 	act_offset = (bank) ? nvm->flash_bank_size : 0;  in e1000_read_nvm_spt()
3314 		if (words - i == 1) {  in e1000_read_nvm_spt()
3315 			if (dev_spec->shadow_ram[offset + i].modified) {  in e1000_read_nvm_spt()
3317 				    dev_spec->shadow_ram[offset + i].value;  in e1000_read_nvm_spt()
3319 				offset_to_read = act_offset + i -  in e1000_read_nvm_spt()
3322 				  e1000_read_flash_dword_ich8lan(hw,  in e1000_read_nvm_spt()
3334 			if (!(dev_spec->shadow_ram[offset + i].modified) ||  in e1000_read_nvm_spt()
3335 			    !(dev_spec->shadow_ram[offset + i + 1].modified)) {  in e1000_read_nvm_spt()
3337 				  e1000_read_flash_dword_ich8lan(hw,  in e1000_read_nvm_spt()
3343 			if (dev_spec->shadow_ram[offset + i].modified)  in e1000_read_nvm_spt()
3345 				    dev_spec->shadow_ram[offset + i].value;  in e1000_read_nvm_spt()
3348 			if (dev_spec->shadow_ram[offset + i].modified)  in e1000_read_nvm_spt()
3350 				    dev_spec->shadow_ram[offset + i + 1].value;  in e1000_read_nvm_spt()
3356 	nvm->ops.release(hw);  in e1000_read_nvm_spt()
3366  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
3367  *  @hw: pointer to the HW structure
3374 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,  in e1000_read_nvm_ich8lan()  argument
3377 	struct e1000_nvm_info *nvm = &hw->nvm;  in e1000_read_nvm_ich8lan()
3378 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;  in e1000_read_nvm_ich8lan()
3384 	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||  in e1000_read_nvm_ich8lan()
3387 		ret_val = -E1000_ERR_NVM;  in e1000_read_nvm_ich8lan()
3391 	nvm->ops.acquire(hw);  in e1000_read_nvm_ich8lan()
3393 	ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);  in e1000_read_nvm_ich8lan()
3399 	act_offset = (bank) ? nvm->flash_bank_size : 0;  in e1000_read_nvm_ich8lan()
3404 		if (dev_spec->shadow_ram[offset + i].modified) {  in e1000_read_nvm_ich8lan()
3405 			data[i] = dev_spec->shadow_ram[offset + i].value;  in e1000_read_nvm_ich8lan()
3407 			ret_val = e1000_read_flash_word_ich8lan(hw,  in e1000_read_nvm_ich8lan()
3416 	nvm->ops.release(hw);  in e1000_read_nvm_ich8lan()
3426  *  e1000_flash_cycle_init_ich8lan - Initialize flash
3427  *  @hw: pointer to the HW structure
3432 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)  in e1000_flash_cycle_init_ich8lan()  argument
3435 	s32 ret_val = -E1000_ERR_NVM;  in e1000_flash_cycle_init_ich8lan()
3442 		return -E1000_ERR_NVM;  in e1000_flash_cycle_init_ich8lan()
3445 	/* Clear FCERR and DAEL in hw status by writing 1 */  in e1000_flash_cycle_init_ich8lan()
3448 	if (hw->mac.type >= e1000_pch_spt)  in e1000_flash_cycle_init_ich8lan()
3467 		if (hw->mac.type >= e1000_pch_spt)  in e1000_flash_cycle_init_ich8lan()
3491 			if (hw->mac.type >= e1000_pch_spt)  in e1000_flash_cycle_init_ich8lan()
3505  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3506  *  @hw: pointer to the HW structure
3511 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)  in e1000_flash_cycle_ich8lan()  argument
3517 	/* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */  in e1000_flash_cycle_ich8lan()
3518 	if (hw->mac.type >= e1000_pch_spt)  in e1000_flash_cycle_ich8lan()
3524 	if (hw->mac.type >= e1000_pch_spt)  in e1000_flash_cycle_ich8lan()
3540 	return -E1000_ERR_NVM;  in e1000_flash_cycle_ich8lan()
3544  *  e1000_read_flash_dword_ich8lan - Read dword from flash
3545  *  @hw: pointer to the HW structure
3552 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,  in e1000_read_flash_dword_ich8lan()  argument
3557 	return e1000_read_flash_data32_ich8lan(hw, offset, data);  in e1000_read_flash_dword_ich8lan()
3561  *  e1000_read_flash_word_ich8lan - Read word from flash
3562  *  @hw: pointer to the HW structure
3569 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,  in e1000_read_flash_word_ich8lan()  argument
3575 	return e1000_read_flash_data_ich8lan(hw, offset, 2, data);  in e1000_read_flash_word_ich8lan()
3579  *  e1000_read_flash_byte_ich8lan - Read byte from flash
3580  *  @hw: pointer to the HW structure
3586 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,  in e1000_read_flash_byte_ich8lan()  argument
3595 	if (hw->mac.type >= e1000_pch_spt)  in e1000_read_flash_byte_ich8lan()
3596 		return -E1000_ERR_NVM;  in e1000_read_flash_byte_ich8lan()
3598 		ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);  in e1000_read_flash_byte_ich8lan()
3609  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
3610  *  @hw: pointer to the HW structure
3617 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,  in e1000_read_flash_data_ich8lan()  argument
3624 	s32 ret_val = -E1000_ERR_NVM;  in e1000_read_flash_data_ich8lan()
3628 		return -E1000_ERR_NVM;  in e1000_read_flash_data_ich8lan()
3631 			     hw->nvm.flash_base_addr);  in e1000_read_flash_data_ich8lan()
3636 		ret_val = e1000_flash_cycle_init_ich8lan(hw);  in e1000_read_flash_data_ich8lan()
3642 		hsflctl.hsf_ctrl.fldbcount = size - 1;  in e1000_read_flash_data_ich8lan()
3649 		    e1000_flash_cycle_ich8lan(hw,  in e1000_read_flash_data_ich8lan()
3675 				e_dbg("Timeout error - flash cycle did not complete.\n");  in e1000_read_flash_data_ich8lan()
3685  *  e1000_read_flash_data32_ich8lan - Read dword from NVM
3686  *  @hw: pointer to the HW structure
3693 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,  in e1000_read_flash_data32_ich8lan()  argument
3699 	s32 ret_val = -E1000_ERR_NVM;  in e1000_read_flash_data32_ich8lan()
3702 	if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt)  in e1000_read_flash_data32_ich8lan()
3703 		return -E1000_ERR_NVM;  in e1000_read_flash_data32_ich8lan()
3705 			     hw->nvm.flash_base_addr);  in e1000_read_flash_data32_ich8lan()
3710 		ret_val = e1000_flash_cycle_init_ich8lan(hw);  in e1000_read_flash_data32_ich8lan()
3719 		hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;  in e1000_read_flash_data32_ich8lan()
3728 		   e1000_flash_cycle_ich8lan(hw,  in e1000_read_flash_data32_ich8lan()
3750 				e_dbg("Timeout error - flash cycle did not complete.\n");  in e1000_read_flash_data32_ich8lan()
3760  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
3761  *  @hw: pointer to the HW structure
3768 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,  in e1000_write_nvm_ich8lan()  argument
3771 	struct e1000_nvm_info *nvm = &hw->nvm;  in e1000_write_nvm_ich8lan()
3772 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;  in e1000_write_nvm_ich8lan()
3775 	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||  in e1000_write_nvm_ich8lan()
3778 		return -E1000_ERR_NVM;  in e1000_write_nvm_ich8lan()
3781 	nvm->ops.acquire(hw);  in e1000_write_nvm_ich8lan()
3784 		dev_spec->shadow_ram[offset + i].modified = true;  in e1000_write_nvm_ich8lan()
3785 		dev_spec->shadow_ram[offset + i].value = data[i];  in e1000_write_nvm_ich8lan()
3788 	nvm->ops.release(hw);  in e1000_write_nvm_ich8lan()
3794  *  e1000_update_nvm_checksum_spt - Update the checksum for NVM
3795  *  @hw: pointer to the HW structure
3804 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)  in e1000_update_nvm_checksum_spt()  argument
3806 	struct e1000_nvm_info *nvm = &hw->nvm;  in e1000_update_nvm_checksum_spt()
3807 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;  in e1000_update_nvm_checksum_spt()
3812 	ret_val = e1000e_update_nvm_checksum_generic(hw);  in e1000_update_nvm_checksum_spt()
3816 	if (nvm->type != e1000_nvm_flash_sw)  in e1000_update_nvm_checksum_spt()
3819 	nvm->ops.acquire(hw);  in e1000_update_nvm_checksum_spt()
3825 	ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);  in e1000_update_nvm_checksum_spt()
3832 		new_bank_offset = nvm->flash_bank_size;  in e1000_update_nvm_checksum_spt()
3834 		ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);  in e1000_update_nvm_checksum_spt()
3838 		old_bank_offset = nvm->flash_bank_size;  in e1000_update_nvm_checksum_spt()
3840 		ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);  in e1000_update_nvm_checksum_spt()
3849 		ret_val = e1000_read_flash_dword_ich8lan(hw,  in e1000_update_nvm_checksum_spt()
3853 		if (dev_spec->shadow_ram[i].modified) {  in e1000_update_nvm_checksum_spt()
3855 			dword |= (dev_spec->shadow_ram[i].value & 0xffff);  in e1000_update_nvm_checksum_spt()
3857 		if (dev_spec->shadow_ram[i + 1].modified) {  in e1000_update_nvm_checksum_spt()
3859 			dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)  in e1000_update_nvm_checksum_spt()
3872 		if (i == E1000_ICH_NVM_SIG_WORD - 1)  in e1000_update_nvm_checksum_spt()
3882 		ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,  in e1000_update_nvm_checksum_spt()
3892 		/* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */  in e1000_update_nvm_checksum_spt()
3905 	--act_offset;  in e1000_update_nvm_checksum_spt()
3906 	ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);  in e1000_update_nvm_checksum_spt()
3912 	ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);  in e1000_update_nvm_checksum_spt()
3918 	act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;  in e1000_update_nvm_checksum_spt()
3919 	ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);  in e1000_update_nvm_checksum_spt()
3925 	ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);  in e1000_update_nvm_checksum_spt()
3932 		dev_spec->shadow_ram[i].modified = false;  in e1000_update_nvm_checksum_spt()
3933 		dev_spec->shadow_ram[i].value = 0xFFFF;  in e1000_update_nvm_checksum_spt()
3937 	nvm->ops.release(hw);  in e1000_update_nvm_checksum_spt()
3943 		nvm->ops.reload(hw);  in e1000_update_nvm_checksum_spt()
3955  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3956  *  @hw: pointer to the HW structure
3965 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)  in e1000_update_nvm_checksum_ich8lan()  argument
3967 	struct e1000_nvm_info *nvm = &hw->nvm;  in e1000_update_nvm_checksum_ich8lan()
3968 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;  in e1000_update_nvm_checksum_ich8lan()
3973 	ret_val = e1000e_update_nvm_checksum_generic(hw);  in e1000_update_nvm_checksum_ich8lan()
3977 	if (nvm->type != e1000_nvm_flash_sw)  in e1000_update_nvm_checksum_ich8lan()
3980 	nvm->ops.acquire(hw);  in e1000_update_nvm_checksum_ich8lan()
3986 	ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);  in e1000_update_nvm_checksum_ich8lan()
3993 		new_bank_offset = nvm->flash_bank_size;  in e1000_update_nvm_checksum_ich8lan()
3995 		ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);  in e1000_update_nvm_checksum_ich8lan()
3999 		old_bank_offset = nvm->flash_bank_size;  in e1000_update_nvm_checksum_ich8lan()
4001 		ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);  in e1000_update_nvm_checksum_ich8lan()
4006 		if (dev_spec->shadow_ram[i].modified) {  in e1000_update_nvm_checksum_ich8lan()
4007 			data = dev_spec->shadow_ram[i].value;  in e1000_update_nvm_checksum_ich8lan()
4009 			ret_val = e1000_read_flash_word_ich8lan(hw, i +  in e1000_update_nvm_checksum_ich8lan()
4031 		ret_val = e1000_retry_write_flash_byte_ich8lan(hw,  in e1000_update_nvm_checksum_ich8lan()
4038 		ret_val = e1000_retry_write_flash_byte_ich8lan(hw,  in e1000_update_nvm_checksum_ich8lan()
4049 		/* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */  in e1000_update_nvm_checksum_ich8lan()
4060 	ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);  in e1000_update_nvm_checksum_ich8lan()
4065 	ret_val = e1000_retry_write_flash_byte_ich8lan(hw,  in e1000_update_nvm_checksum_ich8lan()
4077 	ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);  in e1000_update_nvm_checksum_ich8lan()
4083 		dev_spec->shadow_ram[i].modified = false;  in e1000_update_nvm_checksum_ich8lan()
4084 		dev_spec->shadow_ram[i].value = 0xFFFF;  in e1000_update_nvm_checksum_ich8lan()
4088 	nvm->ops.release(hw);  in e1000_update_nvm_checksum_ich8lan()
4094 		nvm->ops.reload(hw);  in e1000_update_nvm_checksum_ich8lan()
4106  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4107  *  @hw: pointer to the HW structure
4113 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)  in e1000_validate_nvm_checksum_ich8lan()  argument
4125 	switch (hw->mac.type) {  in e1000_validate_nvm_checksum_ich8lan()
4144 	ret_val = e1000_read_nvm(hw, word, 1, &data);  in e1000_validate_nvm_checksum_ich8lan()
4151 		if (hw->mac.type < e1000_pch_tgp) {  in e1000_validate_nvm_checksum_ich8lan()
4153 			ret_val = e1000_write_nvm(hw, word, 1, &data);  in e1000_validate_nvm_checksum_ich8lan()
4156 			ret_val = e1000e_update_nvm_checksum(hw);  in e1000_validate_nvm_checksum_ich8lan()
4162 	return e1000e_validate_nvm_checksum_generic(hw);  in e1000_validate_nvm_checksum_ich8lan()
4166  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
4167  *  @hw: pointer to the HW structure
4169  *  To prevent malicious write/erase of the NVM, set it to be read-only
4171  *  the flash control registers.  The shadow-ram copy of the NVM will
4175 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)  in e1000e_write_protect_nvm_ich8lan()  argument
4177 	struct e1000_nvm_info *nvm = &hw->nvm;  in e1000e_write_protect_nvm_ich8lan()
4182 	nvm->ops.acquire(hw);  in e1000e_write_protect_nvm_ich8lan()
4186 	/* Write-protect GbE Sector of NVM */  in e1000e_write_protect_nvm_ich8lan()
4194 	 * PR0 to prevent the write-protection from being lifted.  in e1000e_write_protect_nvm_ich8lan()
4202 	nvm->ops.release(hw);  in e1000e_write_protect_nvm_ich8lan()
4206  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4207  *  @hw: pointer to the HW structure
4214 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,  in e1000_write_flash_data_ich8lan()  argument
4224 	if (hw->mac.type >= e1000_pch_spt) {  in e1000_write_flash_data_ich8lan()
4226 			return -E1000_ERR_NVM;  in e1000_write_flash_data_ich8lan()
4229 			return -E1000_ERR_NVM;  in e1000_write_flash_data_ich8lan()
4233 			     hw->nvm.flash_base_addr);  in e1000_write_flash_data_ich8lan()
4238 		ret_val = e1000_flash_cycle_init_ich8lan(hw);  in e1000_write_flash_data_ich8lan()
4244 		if (hw->mac.type >= e1000_pch_spt)  in e1000_write_flash_data_ich8lan()
4250 		hsflctl.hsf_ctrl.fldbcount = size - 1;  in e1000_write_flash_data_ich8lan()
4256 		if (hw->mac.type >= e1000_pch_spt)  in e1000_write_flash_data_ich8lan()
4274 		    e1000_flash_cycle_ich8lan(hw,  in e1000_write_flash_data_ich8lan()
4289 			e_dbg("Timeout error - flash cycle did not complete.\n");  in e1000_write_flash_data_ich8lan()
4298 *  e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4299 *  @hw: pointer to the HW structure
4305 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,  in e1000_write_flash_data32_ich8lan()  argument
4314 	if (hw->mac.type >= e1000_pch_spt) {  in e1000_write_flash_data32_ich8lan()
4316 			return -E1000_ERR_NVM;  in e1000_write_flash_data32_ich8lan()
4319 			     hw->nvm.flash_base_addr);  in e1000_write_flash_data32_ich8lan()
4323 		ret_val = e1000_flash_cycle_init_ich8lan(hw);  in e1000_write_flash_data32_ich8lan()
4330 		if (hw->mac.type >= e1000_pch_spt)  in e1000_write_flash_data32_ich8lan()
4336 		hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;  in e1000_write_flash_data32_ich8lan()
4343 		if (hw->mac.type >= e1000_pch_spt)  in e1000_write_flash_data32_ich8lan()
4356 		   e1000_flash_cycle_ich8lan(hw,  in e1000_write_flash_data32_ich8lan()
4373 			e_dbg("Timeout error - flash cycle did not complete.\n");  in e1000_write_flash_data32_ich8lan()
4382  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4383  *  @hw: pointer to the HW structure
4389 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,  in e1000_write_flash_byte_ich8lan()  argument
4394 	return e1000_write_flash_data_ich8lan(hw, offset, 1, word);  in e1000_write_flash_byte_ich8lan()
4398 *  e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4399 *  @hw: pointer to the HW structure
4406 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,  in e1000_retry_write_flash_dword_ich8lan()  argument
4414 	ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);  in e1000_retry_write_flash_dword_ich8lan()
4421 		ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);  in e1000_retry_write_flash_dword_ich8lan()
4426 		return -E1000_ERR_NVM;  in e1000_retry_write_flash_dword_ich8lan()
4432  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4433  *  @hw: pointer to the HW structure
4440 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,  in e1000_retry_write_flash_byte_ich8lan()  argument
4446 	ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);  in e1000_retry_write_flash_byte_ich8lan()
4453 		ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);  in e1000_retry_write_flash_byte_ich8lan()
4458 		return -E1000_ERR_NVM;  in e1000_retry_write_flash_byte_ich8lan()
4464  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4465  *  @hw: pointer to the HW structure
4471 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)  in e1000_erase_flash_bank_ich8lan()  argument
4473 	struct e1000_nvm_info *nvm = &hw->nvm;  in e1000_erase_flash_bank_ich8lan()
4477 	/* bank size is in 16bit words - adjust to bytes */  in e1000_erase_flash_bank_ich8lan()
4478 	u32 flash_bank_size = nvm->flash_bank_size * 2;  in e1000_erase_flash_bank_ich8lan()
4485 	/* Determine HW Sector size: Read BERASE bits of hw flash status  in e1000_erase_flash_bank_ich8lan()
4487 	 * 00: The Hw sector is 256 bytes, hence we need to erase 16  in e1000_erase_flash_bank_ich8lan()
4488 	 *     consecutive sectors.  The start index for the nth Hw sector  in e1000_erase_flash_bank_ich8lan()
4490 	 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.  in e1000_erase_flash_bank_ich8lan()
4491 	 *     The start index for the nth Hw sector can be calculated  in e1000_erase_flash_bank_ich8lan()
4493 	 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192  in e1000_erase_flash_bank_ich8lan()
4495 	 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536  in e1000_erase_flash_bank_ich8lan()
4499 		/* Hw sector size 256 */  in e1000_erase_flash_bank_ich8lan()
4516 		return -E1000_ERR_NVM;  in e1000_erase_flash_bank_ich8lan()
4520 	flash_linear_addr = hw->nvm.flash_base_addr;  in e1000_erase_flash_bank_ich8lan()
4528 			ret_val = e1000_flash_cycle_init_ich8lan(hw);  in e1000_erase_flash_bank_ich8lan()
4533 			 * Cycle field in hw flash control  in e1000_erase_flash_bank_ich8lan()
4535 			if (hw->mac.type >= e1000_pch_spt)  in e1000_erase_flash_bank_ich8lan()
4542 			if (hw->mac.type >= e1000_pch_spt)  in e1000_erase_flash_bank_ich8lan()
4555 			ret_val = e1000_flash_cycle_ich8lan(hw, timeout);  in e1000_erase_flash_bank_ich8lan()
4576  *  e1000_valid_led_default_ich8lan - Set the default LED settings
4577  *  @hw: pointer to the HW structure
4584 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)  in e1000_valid_led_default_ich8lan()  argument
4588 	ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);  in e1000_valid_led_default_ich8lan()
4601  *  e1000_id_led_init_pchlan - store LED configurations
4602  *  @hw: pointer to the HW structure
4613 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)  in e1000_id_led_init_pchlan()  argument
4615 	struct e1000_mac_info *mac = &hw->mac;  in e1000_id_led_init_pchlan()
4622 	ret_val = hw->nvm.ops.valid_led_default(hw, &data);  in e1000_id_led_init_pchlan()
4626 	mac->ledctl_default = er32(LEDCTL);  in e1000_id_led_init_pchlan()
4627 	mac->ledctl_mode1 = mac->ledctl_default;  in e1000_id_led_init_pchlan()
4628 	mac->ledctl_mode2 = mac->ledctl_default;  in e1000_id_led_init_pchlan()
4637 			mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);  in e1000_id_led_init_pchlan()
4638 			mac->ledctl_mode1 |= (ledctl_on << shift);  in e1000_id_led_init_pchlan()
4643 			mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);  in e1000_id_led_init_pchlan()
4644 			mac->ledctl_mode1 |= (ledctl_off << shift);  in e1000_id_led_init_pchlan()
4654 			mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);  in e1000_id_led_init_pchlan()
4655 			mac->ledctl_mode2 |= (ledctl_on << shift);  in e1000_id_led_init_pchlan()
4660 			mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);  in e1000_id_led_init_pchlan()
4661 			mac->ledctl_mode2 |= (ledctl_off << shift);  in e1000_id_led_init_pchlan()
4673  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4674  *  @hw: pointer to the HW structure
4679 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)  in e1000_get_bus_info_ich8lan()  argument
4681 	struct e1000_bus_info *bus = &hw->bus;  in e1000_get_bus_info_ich8lan()
4684 	ret_val = e1000e_get_bus_info_pcie(hw);  in e1000_get_bus_info_ich8lan()
4686 	/* ICH devices are "PCI Express"-ish.  They have  in e1000_get_bus_info_ich8lan()
4691 	if (bus->width == e1000_bus_width_unknown)  in e1000_get_bus_info_ich8lan()
4692 		bus->width = e1000_bus_width_pcie_x1;  in e1000_get_bus_info_ich8lan()
4698  *  e1000_reset_hw_ich8lan - Reset the hardware
4699  *  @hw: pointer to the HW structure
4704 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)  in e1000_reset_hw_ich8lan()  argument
4706 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;  in e1000_reset_hw_ich8lan()
4708 	u32 ctrl, reg;  in e1000_reset_hw_ich8lan()  local
4711 	/* Prevent the PCI-E bus from sticking if there is no TLP connection  in e1000_reset_hw_ich8lan()
4714 	ret_val = e1000e_disable_pcie_master(hw);  in e1000_reset_hw_ich8lan()
4716 		e_dbg("PCI-E Master disable polling has failed.\n");  in e1000_reset_hw_ich8lan()
4732 	if (hw->mac.type == e1000_ich8lan) {  in e1000_reset_hw_ich8lan()
4739 	if (hw->mac.type == e1000_pchlan) {  in e1000_reset_hw_ich8lan()
4741 		ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);  in e1000_reset_hw_ich8lan()
4746 			dev_spec->nvm_k1_enabled = true;  in e1000_reset_hw_ich8lan()
4748 			dev_spec->nvm_k1_enabled = false;  in e1000_reset_hw_ich8lan()
4751 	ctrl = er32(CTRL);  in e1000_reset_hw_ich8lan()
4753 	if (!hw->phy.ops.check_reset_block(hw)) {  in e1000_reset_hw_ich8lan()
4754 		/* Full-chip reset requires MAC and PHY reset at the same  in e1000_reset_hw_ich8lan()
4758 		ctrl |= E1000_CTRL_PHY_RST;  in e1000_reset_hw_ich8lan()
4761 		 * non-managed 82579  in e1000_reset_hw_ich8lan()
4763 		if ((hw->mac.type == e1000_pch2lan) &&  in e1000_reset_hw_ich8lan()
4765 			e1000_gate_hw_phy_config_ich8lan(hw, true);  in e1000_reset_hw_ich8lan()
4767 	ret_val = e1000_acquire_swflag_ich8lan(hw);  in e1000_reset_hw_ich8lan()
4769 	ew32(CTRL, (ctrl | E1000_CTRL_RST));  in e1000_reset_hw_ich8lan()
4774 	if (hw->mac.type == e1000_pch2lan) {  in e1000_reset_hw_ich8lan()
4782 		clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);  in e1000_reset_hw_ich8lan()
4784 	if (ctrl & E1000_CTRL_PHY_RST) {  in e1000_reset_hw_ich8lan()
4785 		ret_val = hw->phy.ops.get_cfg_done(hw);  in e1000_reset_hw_ich8lan()
4789 		ret_val = e1000_post_phy_reset_ich8lan(hw);  in e1000_reset_hw_ich8lan()
4798 	if (hw->mac.type == e1000_pchlan)  in e1000_reset_hw_ich8lan()
4812  *  e1000_init_hw_ich8lan - Initialize the hardware
4813  *  @hw: pointer to the HW structure
4816  *   - initialize hardware bits
4817  *   - initialize LED identification
4818  *   - setup receive address registers
4819  *   - setup flow control
4820  *   - setup transmit descriptors
4821  *   - clear statistics
4823 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)  in e1000_init_hw_ich8lan()  argument
4825 	struct e1000_mac_info *mac = &hw->mac;  in e1000_init_hw_ich8lan()
4830 	e1000_initialize_hw_bits_ich8lan(hw);  in e1000_init_hw_ich8lan()
4833 	ret_val = mac->ops.id_led_init(hw);  in e1000_init_hw_ich8lan()
4839 	e1000e_init_rx_addrs(hw, mac->rar_entry_count);  in e1000_init_hw_ich8lan()
4843 	for (i = 0; i < mac->mta_reg_count; i++)  in e1000_init_hw_ich8lan()
4844 		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);  in e1000_init_hw_ich8lan()
4850 	if (hw->phy.type == e1000_phy_82578) {  in e1000_init_hw_ich8lan()
4851 		e1e_rphy(hw, BM_PORT_GEN_CFG, &i);  in e1000_init_hw_ich8lan()
4853 		e1e_wphy(hw, BM_PORT_GEN_CFG, i);  in e1000_init_hw_ich8lan()
4854 		ret_val = e1000_phy_hw_reset_ich8lan(hw);  in e1000_init_hw_ich8lan()
4859 	/* Setup link and flow control */  in e1000_init_hw_ich8lan()
4860 	ret_val = mac->ops.setup_link(hw);  in e1000_init_hw_ich8lan()
4862 	/* Set the transmit descriptor write-back policy for both queues */  in e1000_init_hw_ich8lan()
4879 	if (mac->type == e1000_ich8lan)  in e1000_init_hw_ich8lan()
4883 	e1000e_set_pcie_no_snoop(hw, snoop);  in e1000_init_hw_ich8lan()
4888 	if (mac->type >= e1000_pch_tgp) {  in e1000_init_hw_ich8lan()
4903 	e1000_clear_hw_cntrs_ich8lan(hw);  in e1000_init_hw_ich8lan()
4909  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4910  *  @hw: pointer to the HW structure
4915 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)  in e1000_initialize_hw_bits_ich8lan()  argument
4922 	/* Enable PHY low-power state when MAC is at D3 w/o WoL */  in e1000_initialize_hw_bits_ich8lan()
4923 	if (hw->mac.type >= e1000_pchlan)  in e1000_initialize_hw_bits_ich8lan()
4939 	if (hw->mac.type == e1000_ich8lan)  in e1000_initialize_hw_bits_ich8lan()
4954 	if (hw->mac.type == e1000_ich8lan) {  in e1000_initialize_hw_bits_ich8lan()
4960 	/* work-around descriptor data corruption issue during nfs v2 udp  in e1000_initialize_hw_bits_ich8lan()
4969 	if (hw->mac.type == e1000_ich8lan)  in e1000_initialize_hw_bits_ich8lan()
4974 	if (hw->mac.type >= e1000_pch_lpt) {  in e1000_initialize_hw_bits_ich8lan()
4979 		reg = er32(CTRL);  in e1000_initialize_hw_bits_ich8lan()
4981 		ew32(CTRL, reg);  in e1000_initialize_hw_bits_ich8lan()
4986  *  e1000_setup_link_ich8lan - Setup flow control and link settings
4987  *  @hw: pointer to the HW structure
4989  *  Determines which flow control settings to use, then configures flow
4990  *  control.  Calls the appropriate media-specific link configuration
4995 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)  in e1000_setup_link_ich8lan()  argument
4999 	if (hw->phy.ops.check_reset_block(hw))  in e1000_setup_link_ich8lan()
5003 	 * the default flow control setting, so we explicitly  in e1000_setup_link_ich8lan()
5006 	if (hw->fc.requested_mode == e1000_fc_default) {  in e1000_setup_link_ich8lan()
5007 		/* Workaround h/w hang when Tx flow control enabled */  in e1000_setup_link_ich8lan()
5008 		if (hw->mac.type == e1000_pchlan)  in e1000_setup_link_ich8lan()
5009 			hw->fc.requested_mode = e1000_fc_rx_pause;  in e1000_setup_link_ich8lan()
5011 			hw->fc.requested_mode = e1000_fc_full;  in e1000_setup_link_ich8lan()
5014 	/* Save off the requested flow control mode for use later.  Depending  in e1000_setup_link_ich8lan()
5017 	hw->fc.current_mode = hw->fc.requested_mode;  in e1000_setup_link_ich8lan()
5019 	e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);  in e1000_setup_link_ich8lan()
5022 	ret_val = hw->mac.ops.setup_physical_interface(hw);  in e1000_setup_link_ich8lan()
5026 	ew32(FCTTV, hw->fc.pause_time);  in e1000_setup_link_ich8lan()
5027 	if ((hw->phy.type == e1000_phy_82578) ||  in e1000_setup_link_ich8lan()
5028 	    (hw->phy.type == e1000_phy_82579) ||  in e1000_setup_link_ich8lan()
5029 	    (hw->phy.type == e1000_phy_i217) ||  in e1000_setup_link_ich8lan()
5030 	    (hw->phy.type == e1000_phy_82577)) {  in e1000_setup_link_ich8lan()
5031 		ew32(FCRTV_PCH, hw->fc.refresh_time);  in e1000_setup_link_ich8lan()
5033 		ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),  in e1000_setup_link_ich8lan()
5034 				   hw->fc.pause_time);  in e1000_setup_link_ich8lan()
5039 	return e1000e_set_fc_watermarks(hw);  in e1000_setup_link_ich8lan()
5043  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
5044  *  @hw: pointer to the HW structure
5050 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)  in e1000_setup_copper_link_ich8lan()  argument
5052 	u32 ctrl;  in e1000_setup_copper_link_ich8lan()  local
5056 	ctrl = er32(CTRL);  in e1000_setup_copper_link_ich8lan()
5057 	ctrl |= E1000_CTRL_SLU;  in e1000_setup_copper_link_ich8lan()
5058 	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);  in e1000_setup_copper_link_ich8lan()
5059 	ew32(CTRL, ctrl);  in e1000_setup_copper_link_ich8lan()
5065 	ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);  in e1000_setup_copper_link_ich8lan()
5068 	ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,  in e1000_setup_copper_link_ich8lan()
5073 	ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,  in e1000_setup_copper_link_ich8lan()
5078 	switch (hw->phy.type) {  in e1000_setup_copper_link_ich8lan()
5080 		ret_val = e1000e_copper_link_setup_igp(hw);  in e1000_setup_copper_link_ich8lan()
5086 		ret_val = e1000e_copper_link_setup_m88(hw);  in e1000_setup_copper_link_ich8lan()
5092 		ret_val = e1000_copper_link_setup_82577(hw);  in e1000_setup_copper_link_ich8lan()
5097 		ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);  in e1000_setup_copper_link_ich8lan()
5103 		switch (hw->phy.mdix) {  in e1000_setup_copper_link_ich8lan()
5115 		ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);  in e1000_setup_copper_link_ich8lan()
5123 	return e1000e_setup_copper_link(hw);  in e1000_setup_copper_link_ich8lan()
5127  *  e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5128  *  @hw: pointer to the HW structure
5134 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)  in e1000_setup_copper_link_pch_lpt()  argument
5136 	u32 ctrl;  in e1000_setup_copper_link_pch_lpt()  local
5139 	ctrl = er32(CTRL);  in e1000_setup_copper_link_pch_lpt()
5140 	ctrl |= E1000_CTRL_SLU;  in e1000_setup_copper_link_pch_lpt()
5141 	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);  in e1000_setup_copper_link_pch_lpt()
5142 	ew32(CTRL, ctrl);  in e1000_setup_copper_link_pch_lpt()
5144 	ret_val = e1000_copper_link_setup_82577(hw);  in e1000_setup_copper_link_pch_lpt()
5148 	return e1000e_setup_copper_link(hw);  in e1000_setup_copper_link_pch_lpt()
5152  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5153  *  @hw: pointer to the HW structure
5161 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,  in e1000_get_link_up_info_ich8lan()  argument
5166 	ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);  in e1000_get_link_up_info_ich8lan()
5170 	if ((hw->mac.type == e1000_ich8lan) &&  in e1000_get_link_up_info_ich8lan()
5171 	    (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {  in e1000_get_link_up_info_ich8lan()
5172 		ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);  in e1000_get_link_up_info_ich8lan()
5179  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5180  *  @hw: pointer to the HW structure
5182  *  Work-around for 82566 Kumeran PCS lock loss:
5184  *  speed is gigabit-
5193 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)  in e1000_kmrn_lock_loss_workaround_ich8lan()  argument
5195 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;  in e1000_kmrn_lock_loss_workaround_ich8lan()
5201 	if (!dev_spec->kmrn_lock_loss_workaround_enabled)  in e1000_kmrn_lock_loss_workaround_ich8lan()
5208 	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);  in e1000_kmrn_lock_loss_workaround_ich8lan()
5214 		ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);  in e1000_kmrn_lock_loss_workaround_ich8lan()
5218 		ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);  in e1000_kmrn_lock_loss_workaround_ich8lan()
5227 		e1000_phy_hw_reset(hw);  in e1000_kmrn_lock_loss_workaround_ich8lan()
5239 	e1000e_gig_downshift_workaround_ich8lan(hw);  in e1000_kmrn_lock_loss_workaround_ich8lan()
5242 	return -E1000_ERR_PHY;  in e1000_kmrn_lock_loss_workaround_ich8lan()
5246  *  e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5247  *  @hw: pointer to the HW structure
5250  *  If ICH8, set the current Kumeran workaround state (enabled - true
5251  *  /disabled - false).
5253 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,  in e1000e_set_kmrn_lock_loss_workaround_ich8lan()  argument
5256 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;  in e1000e_set_kmrn_lock_loss_workaround_ich8lan()
5258 	if (hw->mac.type != e1000_ich8lan) {  in e1000e_set_kmrn_lock_loss_workaround_ich8lan()
5263 	dev_spec->kmrn_lock_loss_workaround_enabled = state;  in e1000e_set_kmrn_lock_loss_workaround_ich8lan()
5267  *  e1000e_igp3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5268  *  @hw: pointer to the HW structure
5270  *  Workaround for 82566 power-down on D3 entry:
5272  *    2) write VR power-down enable
5276 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)  in e1000e_igp3_phy_powerdown_workaround_ich8lan()  argument
5282 	if (hw->phy.type != e1000_phy_igp_3)  in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5296 		if (hw->mac.type == e1000_ich8lan)  in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5297 			e1000e_gig_downshift_workaround_ich8lan(hw);  in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5299 		/* Write VR power-down enable */  in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5300 		e1e_rphy(hw, IGP3_VR_CTRL, &data);  in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5302 		e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);  in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5305 		e1e_rphy(hw, IGP3_VR_CTRL, &data);  in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5311 		reg = er32(CTRL);  in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5312 		ew32(CTRL, reg | E1000_CTRL_PHY_RST);  in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5318  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5319  *  @hw: pointer to the HW structure
5323  *    1) Set Kumeran Near-end loopback
5324  *    2) Clear Kumeran Near-end loopback
5327 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)  in e1000e_gig_downshift_workaround_ich8lan()  argument
5332 	if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))  in e1000e_gig_downshift_workaround_ich8lan()
5335 	ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,  in e1000e_gig_downshift_workaround_ich8lan()
5340 	ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,  in e1000e_gig_downshift_workaround_ich8lan()
5345 	e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);  in e1000e_gig_downshift_workaround_ich8lan()
5349  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5350  *  @hw: pointer to the HW structure
5362 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)  in e1000_suspend_workarounds_ich8lan()  argument
5364 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;  in e1000_suspend_workarounds_ich8lan()
5371 	if (hw->phy.type == e1000_phy_i217) {  in e1000_suspend_workarounds_ich8lan()
5372 		u16 phy_reg, device_id = hw->adapter->pdev->device;  in e1000_suspend_workarounds_ich8lan()
5378 		    (hw->mac.type >= e1000_pch_spt)) {  in e1000_suspend_workarounds_ich8lan()
5384 		ret_val = hw->phy.ops.acquire(hw);  in e1000_suspend_workarounds_ich8lan()
5388 		if (!dev_spec->eee_disable) {  in e1000_suspend_workarounds_ich8lan()
5392 			    e1000_read_emi_reg_locked(hw,  in e1000_suspend_workarounds_ich8lan()
5404 			    (dev_spec->eee_lp_ability &  in e1000_suspend_workarounds_ich8lan()
5406 			    (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {  in e1000_suspend_workarounds_ich8lan()
5411 				e1e_rphy_locked(hw,  in e1000_suspend_workarounds_ich8lan()
5414 				e1e_wphy_locked(hw,  in e1000_suspend_workarounds_ich8lan()
5428 			e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);  in e1000_suspend_workarounds_ich8lan()
5430 			e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);  in e1000_suspend_workarounds_ich8lan()
5435 			e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);  in e1000_suspend_workarounds_ich8lan()
5437 			e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);  in e1000_suspend_workarounds_ich8lan()
5440 			e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);  in e1000_suspend_workarounds_ich8lan()
5442 			e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);  in e1000_suspend_workarounds_ich8lan()
5448 		e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);  in e1000_suspend_workarounds_ich8lan()
5450 		e1e_wphy_locked(hw, I217_CGFREG, phy_reg);  in e1000_suspend_workarounds_ich8lan()
5453 		hw->phy.ops.release(hw);  in e1000_suspend_workarounds_ich8lan()
5458 	if (hw->mac.type == e1000_ich8lan)  in e1000_suspend_workarounds_ich8lan()
5459 		e1000e_gig_downshift_workaround_ich8lan(hw);  in e1000_suspend_workarounds_ich8lan()
5461 	if (hw->mac.type >= e1000_pchlan) {  in e1000_suspend_workarounds_ich8lan()
5462 		e1000_oem_bits_config_ich8lan(hw, false);  in e1000_suspend_workarounds_ich8lan()
5465 		if (hw->mac.type == e1000_pchlan)  in e1000_suspend_workarounds_ich8lan()
5466 			e1000e_phy_hw_reset_generic(hw);  in e1000_suspend_workarounds_ich8lan()
5468 		ret_val = hw->phy.ops.acquire(hw);  in e1000_suspend_workarounds_ich8lan()
5471 		e1000_write_smbus_addr(hw);  in e1000_suspend_workarounds_ich8lan()
5472 		hw->phy.ops.release(hw);  in e1000_suspend_workarounds_ich8lan()
5477  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5478  *  @hw: pointer to the HW structure
5480  *  During Sx to S0 transitions on non-managed devices or managed devices
5486 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)  in e1000_resume_workarounds_pchlan()  argument
5490 	if (hw->mac.type < e1000_pch2lan)  in e1000_resume_workarounds_pchlan()
5493 	ret_val = e1000_init_phy_workarounds_pchlan(hw);  in e1000_resume_workarounds_pchlan()
5495 		e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);  in e1000_resume_workarounds_pchlan()
5504 	if (hw->phy.type == e1000_phy_i217) {  in e1000_resume_workarounds_pchlan()
5507 		ret_val = hw->phy.ops.acquire(hw);  in e1000_resume_workarounds_pchlan()
5514 		e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);  in e1000_resume_workarounds_pchlan()
5516 		e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);  in e1000_resume_workarounds_pchlan()
5522 			ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);  in e1000_resume_workarounds_pchlan()
5526 			e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);  in e1000_resume_workarounds_pchlan()
5529 			e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);  in e1000_resume_workarounds_pchlan()
5532 		ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);  in e1000_resume_workarounds_pchlan()
5536 		e1e_wphy_locked(hw, I217_CGFREG, phy_reg);  in e1000_resume_workarounds_pchlan()
5540 		hw->phy.ops.release(hw);  in e1000_resume_workarounds_pchlan()
5545  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
5546  *  @hw: pointer to the HW structure
5550 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)  in e1000_cleanup_led_ich8lan()  argument
5552 	if (hw->phy.type == e1000_phy_ife)  in e1000_cleanup_led_ich8lan()
5553 		return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);  in e1000_cleanup_led_ich8lan()
5555 	ew32(LEDCTL, hw->mac.ledctl_default);  in e1000_cleanup_led_ich8lan()
5560  *  e1000_led_on_ich8lan - Turn LEDs on
5561  *  @hw: pointer to the HW structure
5565 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)  in e1000_led_on_ich8lan()  argument
5567 	if (hw->phy.type == e1000_phy_ife)  in e1000_led_on_ich8lan()
5568 		return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,  in e1000_led_on_ich8lan()
5571 	ew32(LEDCTL, hw->mac.ledctl_mode2);  in e1000_led_on_ich8lan()
5576  *  e1000_led_off_ich8lan - Turn LEDs off
5577  *  @hw: pointer to the HW structure
5581 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)  in e1000_led_off_ich8lan()  argument
5583 	if (hw->phy.type == e1000_phy_ife)  in e1000_led_off_ich8lan()
5584 		return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,  in e1000_led_off_ich8lan()
5588 	ew32(LEDCTL, hw->mac.ledctl_mode1);  in e1000_led_off_ich8lan()
5593  *  e1000_setup_led_pchlan - Configures SW controllable LED
5594  *  @hw: pointer to the HW structure
5598 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)  in e1000_setup_led_pchlan()  argument
5600 	return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);  in e1000_setup_led_pchlan()
5604  *  e1000_cleanup_led_pchlan - Restore the default LED operation
5605  *  @hw: pointer to the HW structure
5609 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)  in e1000_cleanup_led_pchlan()  argument
5611 	return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);  in e1000_cleanup_led_pchlan()
5615  *  e1000_led_on_pchlan - Turn LEDs on
5616  *  @hw: pointer to the HW structure
5620 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)  in e1000_led_on_pchlan()  argument
5622 	u16 data = (u16)hw->mac.ledctl_mode2;  in e1000_led_on_pchlan()
5641 	return e1e_wphy(hw, HV_LED_CONFIG, data);  in e1000_led_on_pchlan()
5645  *  e1000_led_off_pchlan - Turn LEDs off
5646  *  @hw: pointer to the HW structure
5650 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)  in e1000_led_off_pchlan()  argument
5652 	u16 data = (u16)hw->mac.ledctl_mode1;  in e1000_led_off_pchlan()
5671 	return e1e_wphy(hw, HV_LED_CONFIG, data);  in e1000_led_off_pchlan()
5675  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5676  *  @hw: pointer to the HW structure
5679  *  and configure the PHY through s/w for EEPROM-less parts.
5681  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
5683  *  to return with error, EEPROM-less silicon would not be able to be reset
5686 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)  in e1000_get_cfg_done_ich8lan()  argument
5692 	e1000e_get_cfg_done_generic(hw);  in e1000_get_cfg_done_ich8lan()
5695 	if (hw->mac.type >= e1000_ich10lan) {  in e1000_get_cfg_done_ich8lan()
5696 		e1000_lan_init_done_ich8lan(hw);  in e1000_get_cfg_done_ich8lan()
5698 		ret_val = e1000e_get_auto_rd_done(hw);  in e1000_get_cfg_done_ich8lan()
5714 		e_dbg("PHY Reset Asserted not set - needs delay\n");  in e1000_get_cfg_done_ich8lan()
5717 	if (hw->mac.type <= e1000_ich9lan) {  in e1000_get_cfg_done_ich8lan()
5719 		    (hw->phy.type == e1000_phy_igp_3)) {  in e1000_get_cfg_done_ich8lan()
5720 			e1000e_phy_init_script_igp3(hw);  in e1000_get_cfg_done_ich8lan()
5723 		if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {  in e1000_get_cfg_done_ich8lan()
5726 			ret_val = -E1000_ERR_CONFIG;  in e1000_get_cfg_done_ich8lan()
5734  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5735  * @hw: pointer to the HW structure
5740 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)  in e1000_power_down_phy_copper_ich8lan()  argument
5743 	if (!(hw->mac.ops.check_mng_mode(hw) ||  in e1000_power_down_phy_copper_ich8lan()
5744 	      hw->phy.ops.check_reset_block(hw)))  in e1000_power_down_phy_copper_ich8lan()
5745 		e1000_power_down_phy_copper(hw);  in e1000_power_down_phy_copper_ich8lan()
5749  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5750  *  @hw: pointer to the HW structure
5755 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)  in e1000_clear_hw_cntrs_ich8lan()  argument
5760 	e1000e_clear_hw_cntrs_base(hw);  in e1000_clear_hw_cntrs_ich8lan()
5777 	if ((hw->phy.type == e1000_phy_82578) ||  in e1000_clear_hw_cntrs_ich8lan()
5778 	    (hw->phy.type == e1000_phy_82579) ||  in e1000_clear_hw_cntrs_ich8lan()
5779 	    (hw->phy.type == e1000_phy_i217) ||  in e1000_clear_hw_cntrs_ich8lan()
5780 	    (hw->phy.type == e1000_phy_82577)) {  in e1000_clear_hw_cntrs_ich8lan()
5781 		ret_val = hw->phy.ops.acquire(hw);  in e1000_clear_hw_cntrs_ich8lan()
5784 		ret_val = hw->phy.ops.set_page(hw,  in e1000_clear_hw_cntrs_ich8lan()
5788 		hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);  in e1000_clear_hw_cntrs_ich8lan()
5789 		hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);  in e1000_clear_hw_cntrs_ich8lan()
5790 		hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);  in e1000_clear_hw_cntrs_ich8lan()
5791 		hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);  in e1000_clear_hw_cntrs_ich8lan()
5792 		hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);  in e1000_clear_hw_cntrs_ich8lan()
5793 		hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);  in e1000_clear_hw_cntrs_ich8lan()
5794 		hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);  in e1000_clear_hw_cntrs_ich8lan()
5795 		hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);  in e1000_clear_hw_cntrs_ich8lan()
5796 		hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);  in e1000_clear_hw_cntrs_ich8lan()
5797 		hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);  in e1000_clear_hw_cntrs_ich8lan()
5798 		hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);  in e1000_clear_hw_cntrs_ich8lan()
5799 		hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);  in e1000_clear_hw_cntrs_ich8lan()
5800 		hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);  in e1000_clear_hw_cntrs_ich8lan()
5801 		hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);  in e1000_clear_hw_cntrs_ich8lan()
5803 		hw->phy.ops.release(hw);  in e1000_clear_hw_cntrs_ich8lan()