Lines Matching +full:0 +full:x1032
86 * hardware will not write to a size 0 descriptor and mark the previous
171 static int eeprom_bad_csum_allow = 0;
172 static int use_io = 0;
173 module_param(debug, int, 0);
174 module_param(eeprom_bad_csum_allow, int, 0);
175 module_param(use_io, int, 0);
176 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
182 PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }
184 INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),
185 INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),
186 INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),
187 INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),
188 INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),
189 INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),
190 INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),
191 INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),
192 INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),
193 INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),
194 INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),
195 INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),
196 INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),
197 INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),
198 INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),
199 INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),
200 INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),
201 INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),
202 INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),
203 INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),
204 INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),
205 INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),
206 INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),
207 INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),
208 INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),
209 INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),
210 INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),
211 INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),
212 INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),
213 INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),
214 INTEL_8255X_ETHERNET_DEVICE(0x1091, 7),
215 INTEL_8255X_ETHERNET_DEVICE(0x1092, 7),
216 INTEL_8255X_ETHERNET_DEVICE(0x1093, 7),
217 INTEL_8255X_ETHERNET_DEVICE(0x1094, 7),
218 INTEL_8255X_ETHERNET_DEVICE(0x1095, 7),
219 INTEL_8255X_ETHERNET_DEVICE(0x10fe, 7),
220 INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),
221 INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),
222 INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),
223 INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),
224 INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),
225 INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7),
226 { 0, }
231 mac_82557_D100_A = 0,
243 mac_unknown = 0xFF,
247 phy_100a = 0x000003E0,
248 phy_100c = 0x035002A8,
249 phy_82555_tx = 0x015002A8,
250 phy_nsc_tx = 0x5C002000,
251 phy_82562_et = 0x033002A8,
252 phy_82562_em = 0x032002A8,
253 phy_82562_ek = 0x031002A8,
254 phy_82562_eh = 0x017002A8,
255 phy_82552_v = 0xd061004d,
256 phy_unknown = 0xFFFFFFFF,
277 rus_no_res = 0x08,
278 rus_ready = 0x10,
279 rus_mask = 0x3C,
283 RU_SUSPENDED = 0,
289 stat_ack_not_ours = 0x00,
290 stat_ack_sw_gen = 0x04,
291 stat_ack_rnr = 0x10,
292 stat_ack_cu_idle = 0x20,
293 stat_ack_frame_rx = 0x40,
294 stat_ack_cu_cmd_done = 0x80,
295 stat_ack_not_present = 0xFF,
301 irq_mask_none = 0x00,
302 irq_mask_all = 0x01,
303 irq_sw_gen = 0x02,
307 cuc_nop = 0x00,
308 ruc_start = 0x01,
309 ruc_load_base = 0x06,
310 cuc_start = 0x10,
311 cuc_resume = 0x20,
312 cuc_dump_addr = 0x40,
313 cuc_dump_stats = 0x50,
314 cuc_load_base = 0x60,
315 cuc_dump_reset = 0x70,
319 cuc_dump_complete = 0x0000A005,
320 cuc_dump_reset_complete = 0x0000A007,
324 software_reset = 0x0000,
325 selftest = 0x0001,
326 selective_reset = 0x0002,
330 eesk = 0x01,
331 eecs = 0x02,
332 eedi = 0x04,
333 eedo = 0x08,
337 mdi_write = 0x04000000,
338 mdi_read = 0x08000000,
339 mdi_ready = 0x10000000,
343 op_write = 0x05,
344 op_read = 0x06,
345 op_ewds = 0x10,
346 op_ewen = 0x13,
350 eeprom_cnfg_mdix = 0x03,
351 eeprom_phy_iface = 0x06,
352 eeprom_id = 0x0A,
353 eeprom_config_asf = 0x0D,
354 eeprom_smbus_addr = 0x90,
358 eeprom_mdix_enabled = 0x0080,
362 NoSuchPhy = 0,
374 eeprom_id_wol = 0x0020,
378 eeprom_asf = 0x8000,
379 eeprom_gcl = 0x4000,
383 cb_complete = 0x8000,
384 cb_ok = 0x2000,
389 * @cb_tx_nc: 0: controller does CRC (normal), 1: CRC from skb memory
392 cb_nop = 0x0000,
393 cb_iaaddr = 0x0001,
394 cb_config = 0x0002,
395 cb_multi = 0x0003,
396 cb_tx = 0x0004,
397 cb_ucode = 0x0005,
398 cb_dump = 0x0006,
399 cb_tx_sf = 0x0008,
400 cb_tx_nc = 0x0010,
401 cb_cid = 0x1f00,
402 cb_i = 0x2000,
403 cb_s = 0x4000,
404 cb_el = 0x8000,
428 /*0*/ u8 X(byte_count:6, pad0:2);
502 lb_none = 0, lb_mac = 1, lb_phy = 3,
564 ich = (1 << 0),
655 nic->mem->selftest.signature = 0; in e100_self_test()
656 nic->mem->selftest.result = 0xFFFFFFFF; in e100_self_test()
667 if (nic->mem->selftest.result != 0) { in e100_self_test()
669 "Self-test failed: result=0x%08X\n", in e100_self_test()
673 if (nic->mem->selftest.signature == 0) { in e100_self_test()
678 return 0; in e100_self_test()
688 cmd_addr_data[0] = op_ewen << (addr_len - 2); in e100_eeprom_write()
694 for (j = 0; j < 3; j++) { in e100_eeprom_write()
700 for (i = 31; i >= 0; i--) { in e100_eeprom_write()
713 iowrite8(0, &nic->csr->eeprom_ctrl_lo); in e100_eeprom_write()
722 u16 data = 0; in e100_eeprom_read()
733 for (i = 31; i >= 0; i--) { in e100_eeprom_read()
749 data = (data << 1) | (ctrl & eedo ? 1 : 0); in e100_eeprom_read()
753 iowrite8(0, &nic->csr->eeprom_ctrl_lo); in e100_eeprom_read()
762 u16 addr, addr_len = 8, checksum = 0; in e100_eeprom_load()
765 e100_eeprom_read(nic, &addr_len, 0); in e100_eeprom_load()
768 for (addr = 0; addr < nic->eeprom_wc; addr++) { in e100_eeprom_load()
775 * the sum of words should be 0xBABA */ in e100_eeprom_load()
776 if (cpu_to_le16(0xBABA - checksum) != nic->eeprom[nic->eeprom_wc - 1]) { in e100_eeprom_load()
782 return 0; in e100_eeprom_load()
788 u16 addr, addr_len = 8, checksum = 0; in e100_eeprom_save()
791 e100_eeprom_read(nic, &addr_len, 0); in e100_eeprom_save()
801 * the sum of words should be 0xBABA */ in e100_eeprom_save()
802 for (addr = 0; addr < nic->eeprom_wc - 1; addr++) in e100_eeprom_save()
804 nic->eeprom[nic->eeprom_wc - 1] = cpu_to_le16(0xBABA - checksum); in e100_eeprom_save()
808 return 0; in e100_eeprom_save()
817 int err = 0; in e100_exec_cmd()
822 for (i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) { in e100_exec_cmd()
905 return nic->mdio_ctrl(nic, addr, mdi_read, reg, 0); in mdio_read()
918 u32 data_out = 0; in mdio_ctrl_hw()
938 return 0; /* No way to indicate timeout error */ in mdio_ctrl_hw()
942 for (i = 0; i < 100; i++) { in mdio_ctrl_hw()
949 "%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n", in mdio_ctrl_hw()
1012 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n", in mdio_ctrl_phy_mii_emulated()
1015 return 0xFFFF; in mdio_ctrl_phy_mii_emulated()
1021 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n", in mdio_ctrl_phy_mii_emulated()
1024 return 0xFFFF; in mdio_ctrl_phy_mii_emulated()
1050 nic->tx_threshold = 0xE0; in e100_get_defaults()
1057 nic->blank_rfd.command = 0; in e100_get_defaults()
1058 nic->blank_rfd.rbd = cpu_to_le32(0xFFFFFFFF); in e100_get_defaults()
1062 nic->mii.phy_id_mask = 0x1F; in e100_get_defaults()
1063 nic->mii.reg_num_mask = 0x1F; in e100_get_defaults()
1077 memset(config, 0, sizeof(struct config)); in e100_configure()
1079 config->byte_count = 0x16; /* bytes in this struct */ in e100_configure()
1080 config->rx_fifo_limit = 0x8; /* bytes in FIFO before DMA */ in e100_configure()
1081 config->direct_rx_dma = 0x1; /* reserved */ in e100_configure()
1082 config->standard_tcb = 0x1; /* 1=standard, 0=extended */ in e100_configure()
1083 config->standard_stat_counter = 0x1; /* 1=standard, 0=extended */ in e100_configure()
1084 config->rx_discard_short_frames = 0x1; /* 1=discard, 0=pass */ in e100_configure()
1085 config->tx_underrun_retry = 0x3; /* # of underrun retries */ in e100_configure()
1087 config->mii_mode = 1; /* 1=MII mode, 0=i82503 mode */ in e100_configure()
1088 config->pad10 = 0x6; in e100_configure()
1089 config->no_source_addr_insertion = 0x1; /* 1=no, 0=yes */ in e100_configure()
1090 config->preamble_length = 0x2; /* 0=1, 1=3, 2=7, 3=15 bytes */ in e100_configure()
1091 config->ifs = 0x6; /* x16 = inter frame spacing */ in e100_configure()
1092 config->ip_addr_hi = 0xF2; /* ARP IP filter - not used */ in e100_configure()
1093 config->pad15_1 = 0x1; in e100_configure()
1094 config->pad15_2 = 0x1; in e100_configure()
1095 config->crs_or_cdt = 0x0; /* 0=CRS only, 1=CRS or CDT */ in e100_configure()
1096 config->fc_delay_hi = 0x40; /* time delay for fc frame */ in e100_configure()
1097 config->tx_padding = 0x1; /* 1=pad short frames */ in e100_configure()
1098 config->fc_priority_threshold = 0x7; /* 7=priority fc disabled */ in e100_configure()
1099 config->pad18 = 0x1; in e100_configure()
1100 config->full_duplex_pin = 0x1; /* 1=examine FDX# pin */ in e100_configure()
1101 config->pad20_1 = 0x1F; in e100_configure()
1102 config->fc_priority_location = 0x1; /* 1=byte#31, 0=byte#19 */ in e100_configure()
1103 config->pad21_1 = 0x5; in e100_configure()
1109 config->full_duplex_force = 0x1; /* 1=force, 0=auto */ in e100_configure()
1112 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */ in e100_configure()
1113 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */ in e100_configure()
1114 config->promiscuous_mode = 0x1; /* 1=on, 0=off */ in e100_configure()
1118 config->rx_crc_transfer = 0x1; /* 1=save, 0=discard */ in e100_configure()
1121 config->multicast_all = 0x1; /* 1=accept, 0=no */ in e100_configure()
1125 config->magic_packet_disable = 0x1; /* 1=off, 0=on */ in e100_configure()
1128 config->fc_disable = 0x1; /* 1=Tx fc off, 0=Tx fc on */ in e100_configure()
1129 config->mwi_enable = 0x1; /* 1=enable, 0=disable */ in e100_configure()
1130 config->standard_tcb = 0x0; /* 1=standard, 0=extended */ in e100_configure()
1131 config->rx_long_ok = 0x1; /* 1=VLANs ok, 0=standard */ in e100_configure()
1133 config->tno_intr = 0x1; /* TCO stats enable */ in e100_configure()
1136 config->byte_count = 0x20; /* extended bytes */ in e100_configure()
1137 config->rx_d102_mode = 0x1; /* GMRC for TCO */ in e100_configure()
1140 config->standard_stat_counter = 0x0; in e100_configure()
1145 config->rx_save_overruns = 0x1; /* 1=save, 0=discard */ in e100_configure()
1146 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */ in e100_configure()
1147 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */ in e100_configure()
1151 c + 0); in e100_configure()
1156 return 0; in e100_configure()
1171 * The current default is 0x600 or 1536. Experiments show that
1172 * the value should probably stay within the 0x200 - 0x1000.
1197 * The current default is 0xFF80, which masks out the lower 7 bits.
1203 * parameters are used). Likewise, a value of 0xF800 (2047) would
1210 * BUNDLESMALL 0
1216 #define INTDELAY (u16)1536 /* 0x600 */
1224 int err = 0; in e100_request_firmware()
1295 "\"%s\" has bogus offset values (0x%x,0x%x,0x%x)\n", in e100_request_firmware()
1326 cb->u.ucode[timer] &= cpu_to_le32(0xFFFF0000); in e100_setup_ucode()
1328 cb->u.ucode[bundle] &= cpu_to_le32(0xFFFF0000); in e100_setup_ucode()
1330 cb->u.ucode[min_size] &= cpu_to_le32(0xFFFF0000); in e100_setup_ucode()
1331 cb->u.ucode[min_size] |= cpu_to_le32((BUNDLESMALL) ? 0xFFFF : 0xFF80); in e100_setup_ucode()
1334 return 0; in e100_setup_ucode()
1340 int err = 0, counter = 50; in e100_load_ucode_wait()
1366 iowrite8(~0, &nic->csr->scb.stat_ack); in e100_load_ucode_wait()
1382 return 0; in e100_setup_iaaddr()
1390 return 0; in e100_dump()
1398 phy_type = (le16_to_cpu(nic->eeprom[eeprom_phy_iface]) >> 8) & 0x0f; in e100_phy_check_without_mii()
1414 nic->mii.phy_id = 0; /* is this ok for an MII-less PHY? */ in e100_phy_check_without_mii()
1423 without_mii = 0; in e100_phy_check_without_mii()
1429 #define NCONFIG_AUTO_SWITCH 0x0080
1431 #define NSC_CONG_ENABLE 0x0100
1432 #define NSC_CONG_TXREADY 0x0400
1439 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */ in e100_phy_init()
1440 for (addr = 0; addr < 32; addr++) { in e100_phy_init()
1441 nic->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr; in e100_phy_init()
1445 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0)))) in e100_phy_init()
1454 return 0; /* simply return and hope for the best */ in e100_phy_init()
1470 "phy ID = 0x%08X\n", nic->phy); in e100_phy_init()
1473 for (addr = 0; addr < 32; addr++) { in e100_phy_init()
1492 #define NCS_PHY_MODEL_MASK 0xFFF0FFFF in e100_phy_init()
1516 (mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000) && in e100_phy_init()
1520 nic->mii.force_media ? 0 : NCONFIG_AUTO_SWITCH); in e100_phy_init()
1523 return 0; in e100_phy_init()
1528 int err = 0; in e100_hw_init()
1538 if ((err = e100_exec_cmd(nic, cuc_load_base, 0))) in e100_hw_init()
1540 if ((err = e100_exec_cmd(nic, ruc_load_base, 0))) in e100_hw_init()
1551 if ((err = e100_exec_cmd(nic, cuc_dump_reset, 0))) in e100_hw_init()
1556 return 0; in e100_hw_init()
1567 i = 0; in e100_multi()
1574 return 0; in e100_multi()
1582 "mc_count=%d, flags=0x%04X\n", in e100_set_multicast_list()
1614 *complete = 0; in e100_update_stats()
1657 if (e100_exec_cmd(nic, cuc_dump_reset, 0)) in e100_update_stats()
1760 cb->u.tcb.tcb_byte_count = 0; in e100_xmit_prepare()
1766 return 0; in e100_xmit_prepare()
1779 if (e100_exec_cmd(nic, cuc_nop, 0)) in e100_xmit_frame()
1809 int tx_cleaned = 0; in e100_tx_clean()
1819 "cb[%d]->status = 0x%04X\n", in e100_tx_clean()
1835 cb->status = 0; in e100_tx_clean()
1865 nic->cbs_avail = 0; in e100_clean_cbs()
1879 nic->cbs_avail = 0; in e100_alloc_cbs()
1886 for (cb = nic->cbs, i = 0; i < count; cb++, i++) { in e100_alloc_cbs()
1888 cb->prev = (i == 0) ? nic->cbs + count - 1 : cb - 1; in e100_alloc_cbs()
1898 return 0; in e100_alloc_cbs()
1930 rx->dma_addr = 0; in e100_rx_alloc_skb()
1946 return 0; in e100_rx_alloc_skb()
1956 u16 fcs_pad = 0; in e100_rx_indicate()
1967 "status=0x%04X\n", rfd_status); in e100_rx_indicate()
1991 actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF; in e100_rx_indicate()
2045 return 0; in e100_rx_indicate()
2052 int restart_required = 0, err = 0; in e100_rx_clean()
2088 * We set the size to 0 to prevent hardware from touching this in e100_rx_clean()
2091 * and size of 0, it will RNR interrupt, the RUS will go into in e100_rx_clean()
2096 new_before_last_rfd->size = 0; in e100_rx_clean()
2136 for (rx = nic->rxs, i = 0; i < count; rx++, i++) { in e100_rx_clean_list()
2163 for (rx = nic->rxs, i = 0; i < count; rx++, i++) { in e100_rx_alloc_list()
2165 rx->prev = (i == 0) ? nic->rxs + count - 1 : rx - 1; in e100_rx_alloc_list()
2174 * We set the size to 0 to prevent hardware from touching this buffer. in e100_rx_alloc_list()
2176 * of 0, it will RNR interrupt, the RU will go into the No Resources in e100_rx_alloc_list()
2181 before_last->size = 0; in e100_rx_alloc_list()
2188 return 0; in e100_rx_alloc_list()
2198 "stat_ack = 0x%02X\n", stat_ack); in e100_intr()
2222 unsigned int work_done = 0; in e100_poll()
2261 return 0; in e100_set_mac_address()
2267 return (nic->pdev->device >= 0x1050) && (nic->pdev->device <= 0x1057) && in e100_asf()
2270 ((le16_to_cpu(nic->eeprom[eeprom_smbus_addr]) & 0xFF) != 0xFE); in e100_asf()
2294 return 0; in e100_up()
2333 "scb.status=0x%02X\n", ioread8(&nic->csr->scb.status)); in e100_tx_timeout_task()
2377 memset(skb->data, 0xFF, ETH_DATA_LEN); in e100_loopback_test()
2390 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 0); in e100_loopback_test()
2399 #define MII_LED_CONTROL 0x1B
2400 #define E100_82552_LED_OVERRIDE 0x19
2401 #define E100_82552_LED_ON 0x000F /* LEDTX and LED_RX both on */
2402 #define E100_82552_LED_OFF 0x000A /* LEDTX and LED_RX both off */
2411 return 0; in e100_get_link_ksettings()
2436 #define E100_PHY_REGS 0x1D
2455 buff[0] = ioread8(&nic->csr->scb.cmd_hi) << 24 | in e100_get_regs()
2458 for (i = 0; i < E100_PHY_REGS; i++) in e100_get_regs()
2465 memset(nic->mem->dump_buf, 0, sizeof(nic->mem->dump_buf)); in e100_get_regs()
2475 wol->supported = (nic->mac >= mac_82558_D101_A4) ? WAKE_MAGIC : 0; in e100_get_wol()
2476 wol->wolopts = (nic->flags & wol_magic) ? WAKE_MAGIC : 0; in e100_get_wol()
2496 return 0; in e100_set_wol()
2529 #define E100_EEPROM_MAGIC 0x1234
2538 return 0; in e100_get_eeprom()
2593 return 0; in e100_set_ringparam()
2612 memset(data, 0, E100_TEST_LEN * sizeof(u64)); in e100_diag_test()
2613 data[0] = !mii_link_ok(&nic->mii); in e100_diag_test()
2632 for (i = 0; i < E100_TEST_LEN; i++) in e100_diag_test()
2633 test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0; in e100_diag_test()
2643 led_on = 0x01, in e100_set_phys_id()
2644 led_off = 0x04, in e100_set_phys_id()
2645 led_on_559 = 0x05, in e100_set_phys_id()
2646 led_on_557 = 0x07, in e100_set_phys_id()
2650 u16 leds = 0; in e100_set_phys_id()
2670 return 0; in e100_set_phys_id()
2707 for (i = 0; i < E100_NET_STATS_LEN; i++) in e100_get_ethtool_stats()
2770 return nic->mem ? 0 : -ENOMEM; in e100_alloc()
2785 int err = 0; in e100_open()
2796 return 0; in e100_close()
2806 return 0; in e100_set_features()
2859 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { in e100_probe()
2880 nic->csr = pci_iomap(pdev, (use_io ? 1 : 0), sizeof(struct csr)); in e100_probe()
2910 timer_setup(&nic->watchdog, e100_watchdog, 0); in e100_probe()
2954 0); in e100_probe()
2961 "addr 0x%llx, irq %d, MAC addr %pM\n", in e100_probe()
2962 (unsigned long long)pci_resource_start(pdev, use_io ? 1 : 0), in e100_probe()
2965 return 0; in e100_probe()
2998 #define E100_82552_SMARTSPEED 0x14 /* SmartSpeed Ctrl register */
2999 #define E100_82552_REV_ANEG 0x0200 /* Reverse auto-negotiation */
3000 #define E100_82552_ANEG_NOW 0x0400 /* Auto-negotiate now */
3037 return 0; in __e100_power_off()
3046 return 0; in e100_suspend()
3077 return 0; in e100_resume()
3130 if (0 != PCI_FUNC(pdev->devfn)) in e100_io_slot_reset()
3151 pci_enable_wake(pdev, PCI_D0, 0); in e100_io_resume()