Lines Matching +full:1 +full:gbps
24 #define HCLGE_VF_VPORT_START_NUM 1
86 #define HCLGE_RSS_TC_SIZE_0 1
149 #define HCLGE_CORE_RESET_BIT 1
164 #define HCLGE_VECTOR0_RX_CMDQ_INT_B 1
166 #define HCLGE_VECTOR0_IMP_RESET_INT_B 1
176 (pci_resource_len((hdev)->pdev, HCLGE_MEM_BAR) >> 1)
186 #define HCLGE_SUPPORT_10G_BIT BIT(1)
242 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */
243 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */
244 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */
245 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */
246 HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */
247 HCLGE_MAC_SPEED_100G = 100000, /* 100000 Mbps = 100 Gbps */
248 HCLGE_MAC_SPEED_200G = 200000 /* 200000 Mbps = 200 Gbps */
257 #define QUERY_ACTIVE_SPEED 1
275 u8 speed_type; /* 0: sfp speed, 1: active speed */
309 #define HCLGE_FILTER_TYPE_PORT 1
312 #define HCLGE_FILTER_FE_NIC_EGRESS_B BIT(1)
332 #define HCLGE_LINK_STATUS_UP 1
336 #define HCLGE_SCH_MODE_DWRR 1
339 u8 pg_sch_mode; /* 0: sp; 1: dwrr */
347 u8 tc_sch_mode; /* 0: sp; 1: dwrr */
371 u8 num_pg; /* It must be 1 if vNET-Base schd */
813 #pragma pack(1)
836 * | 1 | 0 | match '0' |
838 * | 0 | 1 | match '1' |
840 * | 1 | 1 | invalid |
893 #define HCLGE_FLAG_TC_BASE_SCH_MODE 1
928 #define HCLGE_FLAG_DCB_CAPABLE BIT(1)