Lines Matching +full:inter +full:- +full:data
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) Freescale Semicondutor, Inc. 2006-2009. All rights reserved.
12 * - Rearrange code and style fixes
40 u8 res0[0x100 - sizeof(struct ucc_fast)];
45 u32 hafdup; /* half-duplex reg. */
56 u8 res3[0x180 - 0x15A];
104 u8 res5[0x200 - 0x1c4];
118 #define TEMODER_NUM_OF_QUEUES_SHIFT (15-15) /* Number of queues <<
127 #define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31-9 ) /* vlan operation
129 #define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10) /* vlan operation non
131 #define REMODER_RX_QOS_MODE_SHIFT (31-15) /* rx QoS mode << shift
138 mpc82xx-like
140 #define REMODER_NUM_OF_QUEUES_SHIFT (31-23) /* Number of queues <<
154 4-byte
234 #define MACCFG2_PREL_SHIFT (31 - 19) /* Preamble
244 #define MACCFG2_RESERVED_1 0x00000020 /* Reserved -
274 /* UCC GETH IPGIFG (Inter-frame Gap / Inter-Frame Gap Register) */
275 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT (31 - 7) /* Non
276 back-to-back
277 inter frame
280 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT (31 - 15) /* Non
281 back-to-back
282 inter frame
285 #define IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT (31 - 23) /* Mimimum IFG
288 #define IPGIFG_BACK_TO_BACK_IFG_SHIFT (31 - 31) /* back-to-back
289 inter frame
292 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX 127 /* Non back-to-back
293 inter frame gap part
295 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX 127 /* Non back-to-back
296 inter frame gap part
300 #define IPGIFG_BACK_TO_BACK_IFG_MAX 127 /* back-to-back inter
308 #define HALFDUP_ALT_BEB_TRUNCATION_SHIFT (31 - 11) /* Alternate
327 #define HALFDUP_MAX_RETRANSMISSION_SHIFT (31 - 19) /* Maximum
333 #define HALFDUP_COLLISION_WINDOW_SHIFT (31 - 31) /* Collision
356 #define MACSTNADDR1_OCTET_6_SHIFT (31 - 7) /* Station
360 #define MACSTNADDR1_OCTET_5_SHIFT (31 - 15) /* Station
364 #define MACSTNADDR1_OCTET_4_SHIFT (31 - 23) /* Station
368 #define MACSTNADDR1_OCTET_3_SHIFT (31 - 31) /* Station
374 #define MACSTNADDR2_OCTET_2_SHIFT (31 - 7) /* Station
378 #define MACSTNADDR2_OCTET_1_SHIFT (31 - 15) /* Station
384 #define UEMPR_PAUSE_TIME_VALUE_SHIFT (31 - 15) /* Pause time
387 #define UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT (31 - 31) /* Extended
393 #define UTBIPAR_PHY_ADDRESS_SHIFT (31 - 31) /* Phy address
405 #define UESCR_MAXCOV_SHIFT (15 - 7) /* Max
409 #define UESCR_SCOV_SHIFT (15 - 15) /* Status
414 /* UCC GETH UDSR (Data Synchronization Register) */
425 /* Send Queue Queue-Descriptor */
482 u8 res1[0x70 - 0x64];
567 u8 res0[0x38 - 0x02];
575 u32 vtagtable[0x8]; /* 8 4-byte VLAN tags */
578 u8 res2[0x78 - 0x74];
583 u8 res3[0xa8 - 0x94];
585 u8 res4[0xc0 - 0xac];
591 u8 res0[0x10 - 0x04];
598 u8 res1[0x20 - 0xC];
604 u8 res3[0x30 - 0x28];
606 u8 res4[0x36 - 0x34];
609 u8 res5[0x46 - 0x37];
622 u8 addressfiltering[64]; /* address filtering data structure */
625 u8 res6[0x100 - 0xC4]; /* Initialize to zero */
641 u8 res2[0x38 - 0x30];
647 #define ENET_INIT_PARAM_RGF_SHIFT (32 - 4)
648 #define ENET_INIT_PARAM_TGF_SHIFT (32 - 8)
677 u8 res0[0x40 - 0x38];
819 #define R_NO 0x00100000 /* Non-octet aligned frame. */
884 #define TX_RING_MOD_MASK(size) (size-1)
885 #define RX_RING_MOD_MASK(size) (size-1)
960 UCC_GETH_VLAN_OPERATION_TAGGED_NOP = 0x0, /* Tagged - nop */
962 = 0x1, /* Tagged - replace vid portion of q tag */
964 = 0x2, /* Tagged - if vid0 replace vid with default value */
966 = 0x3 /* Tagged - extract q tag from frame */
969 /* UCC GETH vlan operation non-tagged */
971 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP = 0x0, /* Non tagged - nop */
972 UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT = 0x1 /* Non tagged -
990 /* UCC GETH Statistics Gathering Mode - These are bit flags, 'or' them together
1015 /* UCC GETH Pad and CRC Mode - Note, Padding without CRC is not possible */