chelsio/cxgb3/adapter.h

2  * Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved.
14  *      - Redistributions of source code must retain the above
18  *      - Redistributions in binary form must reproduce the above
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
33 /* This file should not be included directly.  Include common.h instead. */
63 	int (*recv)(struct port_info *pi, struct sk_buff *skb);  member
102 struct sge_fl {                     /* SGE per free-buffer list state */
118 	unsigned long empty;        /* # of times queue ran out of buffers */  member
139 					within current sop-eop */
150 	unsigned long pure_rsps;	/* # of pure (non-data) responses */
154 	unsigned long empty;	/* # of times queue ran out of credits */  member
166 	unsigned int in_use;	/* # of in-use Tx descriptors */
217 	spinlock_t reg_lock;	/* guards non-atomic SGE registers (eg context) */
240 		char desc[IFNAMSIZ + 1 + 12];	/* Needs space for "%s-%d" */
272 	u32 val = readl(adapter->regs + reg_addr);  in t3_read_reg()
281 	writel(val, adapter->regs + reg_addr);  in t3_write_reg()
286 	return netdev_priv(adap->port[idx]);  in adap2pinfo()
291 	struct adapter *adap = phy->adapter;  in phy2portid()
294 	return &port0->phy == phy ? 0 : 1;  in phy2portid()
303 	return test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map);  in offload_running()