Lines Matching +full:revision +full:- +full:id2
7 * Copyright (C) 2005-2016 Broadcom Corporation.
8 * Copyright (C) 2016-2017 Broadcom Limited.
14 * Copyright (C) 2000-2016 Broadcom Corporation.
15 * Copyright (C) 2016-2017 Broadcom Ltd.
52 #include <linux/dma-mapping.h>
56 #include <linux/hwmon-sysfs.h>
93 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
95 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
97 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
123 * and dev->tx_timeout() should be called to fix the problem
146 /* Do not place this n-ring entries value into the tp struct itself,
150 * replace things like '% foo' with '& (foo - 1)'.
154 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
161 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
164 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
197 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
201 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
207 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
232 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
354 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
472 writel(val, tp->regs + off); in tg3_write32()
477 return readl(tp->regs + off); in tg3_read32()
482 writel(val, tp->aperegs + off); in tg3_ape_write32()
487 return readl(tp->aperegs + off); in tg3_ape_read32()
494 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_indirect_reg32()
495 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); in tg3_write_indirect_reg32()
496 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); in tg3_write_indirect_reg32()
497 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_indirect_reg32()
502 writel(val, tp->regs + off); in tg3_write_flush_reg32()
503 readl(tp->regs + off); in tg3_write_flush_reg32()
511 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_indirect_reg32()
512 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); in tg3_read_indirect_reg32()
513 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); in tg3_read_indirect_reg32()
514 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_indirect_reg32()
523 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX + in tg3_write_indirect_mbox()
528 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX + in tg3_write_indirect_mbox()
533 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_indirect_mbox()
534 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); in tg3_write_indirect_mbox()
535 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); in tg3_write_indirect_mbox()
536 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_indirect_mbox()
543 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL, in tg3_write_indirect_mbox()
544 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT); in tg3_write_indirect_mbox()
553 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_indirect_mbox()
554 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); in tg3_read_indirect_mbox()
555 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); in tg3_read_indirect_mbox()
556 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_indirect_mbox()
568 /* Non-posted methods */ in _tw32_flush()
569 tp->write32(tp, off, val); in _tw32_flush()
575 tp->read32(tp, off); in _tw32_flush()
586 tp->write32_mbox(tp, off, val); in tw32_mailbox_flush()
590 tp->read32_mbox(tp, off); in tw32_mailbox_flush()
595 void __iomem *mbox = tp->regs + off; in tg3_write32_tx_mbox()
606 return readl(tp->regs + off + GRCMBOX_BASE); in tg3_read32_mbox_5906()
611 writel(val, tp->regs + off + GRCMBOX_BASE); in tg3_write32_mbox_5906()
614 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
616 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
617 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
618 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
620 #define tw32(reg, val) tp->write32(tp, reg, val)
623 #define tr32(reg) tp->read32(tp, reg)
633 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_mem()
635 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); in tg3_write_mem()
636 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_write_mem()
639 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_write_mem()
647 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_mem()
660 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_mem()
662 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); in tg3_read_mem()
663 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_read_mem()
666 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_read_mem()
674 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_mem()
697 if (!tp->pci_fn) in tg3_ape_lock_init()
700 bit = 1 << tp->pci_fn; in tg3_ape_lock_init()
723 if (!tp->pci_fn) in tg3_ape_lock()
726 bit = 1 << tp->pci_fn; in tg3_ape_lock()
735 return -EINVAL; in tg3_ape_lock()
755 if (pci_channel_offline(tp->pdev)) in tg3_ape_lock()
764 ret = -EBUSY; in tg3_ape_lock()
784 if (!tp->pci_fn) in tg3_ape_unlock()
787 bit = 1 << tp->pci_fn; in tg3_ape_unlock()
813 return -EBUSY; in tg3_ape_event_lock()
822 timeout_us -= (timeout_us > 10) ? 10 : timeout_us; in tg3_ape_event_lock()
825 return timeout_us ? 0 : -EBUSY; in tg3_ape_event_lock()
856 return -ENODEV; in tg3_ape_scratchpad_read()
860 return -EAGAIN; in tg3_ape_scratchpad_read()
872 len -= length; in tg3_ape_scratchpad_read()
876 return -EAGAIN; in tg3_ape_scratchpad_read()
897 return -EAGAIN; in tg3_ape_scratchpad_read()
899 for (i = 0; length; i += 4, length -= 4) { in tg3_ape_scratchpad_read()
917 return -EAGAIN; in tg3_ape_send_event()
921 return -EAGAIN; in tg3_ape_send_event()
947 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++); in tg3_ape_driver_state_change()
964 if (device_may_wakeup(&tp->pdev->dev) && in tg3_ape_driver_state_change()
990 time_before(jiffies, tp->ape_hb_jiffies + interval)) in tg3_send_ape_heartbeat()
993 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++); in tg3_send_ape_heartbeat()
994 tp->ape_hb_jiffies = jiffies; in tg3_send_ape_heartbeat()
1002 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); in tg3_disable_ints()
1003 for (i = 0; i < tp->irq_max; i++) in tg3_disable_ints()
1004 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001); in tg3_disable_ints()
1011 tp->irq_sync = 0; in tg3_enable_ints()
1015 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); in tg3_enable_ints()
1017 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE; in tg3_enable_ints()
1018 for (i = 0; i < tp->irq_cnt; i++) { in tg3_enable_ints()
1019 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_enable_ints()
1021 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_enable_ints()
1023 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_enable_ints()
1025 tp->coal_now |= tnapi->coal_now; in tg3_enable_ints()
1030 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED)) in tg3_enable_ints()
1031 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); in tg3_enable_ints()
1033 tw32(HOSTCC_MODE, tp->coal_now); in tg3_enable_ints()
1035 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now); in tg3_enable_ints()
1040 struct tg3 *tp = tnapi->tp; in tg3_has_work()
1041 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_has_work()
1046 if (sblk->status & SD_STATUS_LINK_CHG) in tg3_has_work()
1051 if (sblk->idx[0].tx_consumer != tnapi->tx_cons) in tg3_has_work()
1055 if (tnapi->rx_rcb_prod_idx && in tg3_has_work()
1056 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) in tg3_has_work()
1069 struct tg3 *tp = tnapi->tp; in tg3_int_reenable()
1071 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_int_reenable()
1078 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_int_reenable()
1079 HOSTCC_MODE_ENABLE | tnapi->coal_now); in tg3_int_reenable()
1096 tp->pci_clock_ctrl = clock_ctrl; in tg3_switch_clocks()
1124 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_readphy()
1126 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in __tg3_readphy()
1130 tg3_ape_lock(tp, tp->phy_ape_lock); in __tg3_readphy()
1152 loops -= 1; in __tg3_readphy()
1155 ret = -EBUSY; in __tg3_readphy()
1161 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_readphy()
1162 tw32_f(MAC_MI_MODE, tp->mi_mode); in __tg3_readphy()
1166 tg3_ape_unlock(tp, tp->phy_ape_lock); in __tg3_readphy()
1173 return __tg3_readphy(tp, tp->phy_addr, reg, val); in tg3_readphy()
1183 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && in __tg3_writephy()
1187 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_writephy()
1189 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in __tg3_writephy()
1193 tg3_ape_lock(tp, tp->phy_ape_lock); in __tg3_writephy()
1213 loops -= 1; in __tg3_writephy()
1216 ret = -EBUSY; in __tg3_writephy()
1220 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_writephy()
1221 tw32_f(MAC_MI_MODE, tp->mi_mode); in __tg3_writephy()
1225 tg3_ape_unlock(tp, tp->phy_ape_lock); in __tg3_writephy()
1232 return __tg3_writephy(tp, tp->phy_addr, reg, val); in tg3_writephy()
1362 return -EBUSY; in tg3_bmcr_reset()
1365 while (limit--) { in tg3_bmcr_reset()
1368 return -EBUSY; in tg3_bmcr_reset()
1377 return -EBUSY; in tg3_bmcr_reset()
1384 struct tg3 *tp = bp->priv; in tg3_mdio_read()
1387 spin_lock_bh(&tp->lock); in tg3_mdio_read()
1390 val = -EIO; in tg3_mdio_read()
1392 spin_unlock_bh(&tp->lock); in tg3_mdio_read()
1399 struct tg3 *tp = bp->priv; in tg3_mdio_write()
1402 spin_lock_bh(&tp->lock); in tg3_mdio_write()
1405 ret = -EIO; in tg3_mdio_write()
1407 spin_unlock_bh(&tp->lock); in tg3_mdio_write()
1417 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_mdio_config_5785()
1418 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { in tg3_mdio_config_5785()
1436 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) { in tg3_mdio_config_5785()
1495 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; in tg3_mdio_start()
1496 tw32_f(MAC_MI_MODE, tp->mi_mode); in tg3_mdio_start()
1513 tp->phy_addr = tp->pci_fn + 1; in tg3_mdio_init()
1521 tp->phy_addr += 7; in tg3_mdio_init()
1525 addr = ssb_gige_get_phyaddr(tp->pdev); in tg3_mdio_init()
1528 tp->phy_addr = addr; in tg3_mdio_init()
1530 tp->phy_addr = TG3_PHY_MII_ADDR; in tg3_mdio_init()
1537 tp->mdio_bus = mdiobus_alloc(); in tg3_mdio_init()
1538 if (tp->mdio_bus == NULL) in tg3_mdio_init()
1539 return -ENOMEM; in tg3_mdio_init()
1541 tp->mdio_bus->name = "tg3 mdio bus"; in tg3_mdio_init()
1542 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x", pci_dev_id(tp->pdev)); in tg3_mdio_init()
1543 tp->mdio_bus->priv = tp; in tg3_mdio_init()
1544 tp->mdio_bus->parent = &tp->pdev->dev; in tg3_mdio_init()
1545 tp->mdio_bus->read = &tg3_mdio_read; in tg3_mdio_init()
1546 tp->mdio_bus->write = &tg3_mdio_write; in tg3_mdio_init()
1547 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr); in tg3_mdio_init()
1557 i = mdiobus_register(tp->mdio_bus); in tg3_mdio_init()
1559 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i); in tg3_mdio_init()
1560 mdiobus_free(tp->mdio_bus); in tg3_mdio_init()
1564 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_mdio_init()
1566 if (!phydev || !phydev->drv) { in tg3_mdio_init()
1567 dev_warn(&tp->pdev->dev, "No PHY devices\n"); in tg3_mdio_init()
1568 mdiobus_unregister(tp->mdio_bus); in tg3_mdio_init()
1569 mdiobus_free(tp->mdio_bus); in tg3_mdio_init()
1570 return -ENODEV; in tg3_mdio_init()
1573 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { in tg3_mdio_init()
1575 phydev->interface = PHY_INTERFACE_MODE_GMII; in tg3_mdio_init()
1576 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; in tg3_mdio_init()
1580 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE | in tg3_mdio_init()
1586 phydev->interface = PHY_INTERFACE_MODE_RGMII; in tg3_mdio_init()
1590 phydev->interface = PHY_INTERFACE_MODE_MII; in tg3_mdio_init()
1591 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; in tg3_mdio_init()
1592 tp->phy_flags |= TG3_PHYFLG_IS_FET; in tg3_mdio_init()
1608 mdiobus_unregister(tp->mdio_bus); in tg3_mdio_fini()
1609 mdiobus_free(tp->mdio_bus); in tg3_mdio_fini()
1613 /* tp->lock is held. */
1622 tp->last_event_jiffies = jiffies; in tg3_generate_fw_event()
1627 /* tp->lock is held. */
1635 time_remain = (long)(tp->last_event_jiffies + 1 + in tg3_wait_for_event_ack()
1636 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) - in tg3_wait_for_event_ack()
1650 if (pci_channel_offline(tp->pdev)) in tg3_wait_for_event_ack()
1657 /* tp->lock is held. */
1677 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) { in tg3_phy_gather_ump_data()
1692 /* tp->lock is held. */
1714 /* tp->lock is held. */
1730 /* tp->lock is held. */
1759 /* tp->lock is held. */
1780 /* tp->lock is held. */
1824 if (pci_channel_offline(tp->pdev)) in tg3_poll_fw()
1825 return -ENODEV; in tg3_poll_fw()
1829 return -ENODEV; in tg3_poll_fw()
1837 if (pci_channel_offline(tp->pdev)) { in tg3_poll_fw()
1840 netdev_info(tp->dev, "No firmware running\n"); in tg3_poll_fw()
1857 netdev_info(tp->dev, "No firmware running\n"); in tg3_poll_fw()
1872 if (!netif_carrier_ok(tp->dev)) { in tg3_link_report()
1873 netif_info(tp, link, tp->dev, "Link is down\n"); in tg3_link_report()
1876 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n", in tg3_link_report()
1877 (tp->link_config.active_speed == SPEED_1000 ? in tg3_link_report()
1879 (tp->link_config.active_speed == SPEED_100 ? in tg3_link_report()
1881 (tp->link_config.active_duplex == DUPLEX_FULL ? in tg3_link_report()
1884 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n", in tg3_link_report()
1885 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ? in tg3_link_report()
1887 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ? in tg3_link_report()
1890 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) in tg3_link_report()
1891 netdev_info(tp->dev, "EEE is %s\n", in tg3_link_report()
1892 tp->setlpicnt ? "enabled" : "disabled"); in tg3_link_report()
1897 tp->link_up = netif_carrier_ok(tp->dev); in tg3_link_report()
1964 u32 old_rx_mode = tp->rx_mode; in tg3_setup_flow_control()
1965 u32 old_tx_mode = tp->tx_mode; in tg3_setup_flow_control()
1968 autoneg = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)->autoneg; in tg3_setup_flow_control()
1970 autoneg = tp->link_config.autoneg; in tg3_setup_flow_control()
1973 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_setup_flow_control()
1978 flowctrl = tp->link_config.flowctrl; in tg3_setup_flow_control()
1980 tp->link_config.active_flowctrl = flowctrl; in tg3_setup_flow_control()
1983 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1985 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1987 if (old_rx_mode != tp->rx_mode) in tg3_setup_flow_control()
1988 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_setup_flow_control()
1991 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1993 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1995 if (old_tx_mode != tp->tx_mode) in tg3_setup_flow_control()
1996 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_setup_flow_control()
2004 struct phy_device *phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_adjust_link()
2006 spin_lock_bh(&tp->lock); in tg3_adjust_link()
2008 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK | in tg3_adjust_link()
2011 oldflowctrl = tp->link_config.active_flowctrl; in tg3_adjust_link()
2013 if (phydev->link) { in tg3_adjust_link()
2017 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10) in tg3_adjust_link()
2019 else if (phydev->speed == SPEED_1000 || in tg3_adjust_link()
2025 if (phydev->duplex == DUPLEX_HALF) in tg3_adjust_link()
2029 tp->link_config.flowctrl); in tg3_adjust_link()
2031 if (phydev->pause) in tg3_adjust_link()
2033 if (phydev->asym_pause) in tg3_adjust_link()
2041 if (mac_mode != tp->mac_mode) { in tg3_adjust_link()
2042 tp->mac_mode = mac_mode; in tg3_adjust_link()
2043 tw32_f(MAC_MODE, tp->mac_mode); in tg3_adjust_link()
2048 if (phydev->speed == SPEED_10) in tg3_adjust_link()
2056 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF) in tg3_adjust_link()
2067 if (phydev->link != tp->old_link || in tg3_adjust_link()
2068 phydev->speed != tp->link_config.active_speed || in tg3_adjust_link()
2069 phydev->duplex != tp->link_config.active_duplex || in tg3_adjust_link()
2070 oldflowctrl != tp->link_config.active_flowctrl) in tg3_adjust_link()
2073 tp->old_link = phydev->link; in tg3_adjust_link()
2074 tp->link_config.active_speed = phydev->speed; in tg3_adjust_link()
2075 tp->link_config.active_duplex = phydev->duplex; in tg3_adjust_link()
2077 spin_unlock_bh(&tp->lock); in tg3_adjust_link()
2087 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) in tg3_phy_init()
2093 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_phy_init()
2096 phydev = phy_connect(tp->dev, phydev_name(phydev), in tg3_phy_init()
2097 tg3_adjust_link, phydev->interface); in tg3_phy_init()
2099 dev_err(&tp->pdev->dev, "Could not attach to PHY\n"); in tg3_phy_init()
2104 switch (phydev->interface) { in tg3_phy_init()
2107 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_init()
2118 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_init()
2119 return -EINVAL; in tg3_phy_init()
2122 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED; in tg3_phy_init()
2133 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_phy_start()
2136 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_phy_start()
2138 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { in tg3_phy_start()
2139 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; in tg3_phy_start()
2140 phydev->speed = tp->link_config.speed; in tg3_phy_start()
2141 phydev->duplex = tp->link_config.duplex; in tg3_phy_start()
2142 phydev->autoneg = tp->link_config.autoneg; in tg3_phy_start()
2144 phydev->advertising, tp->link_config.advertising); in tg3_phy_start()
2154 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_phy_stop()
2157 phy_stop(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_stop()
2162 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { in tg3_phy_fini()
2163 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_fini()
2164 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED; in tg3_phy_fini()
2173 if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_phy_set_extloopbk()
2176 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_set_extloopbk()
2177 /* Cannot do read-modify-write on 5401 */ in tg3_phy_set_extloopbk()
2224 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) in tg3_phy_toggle_apd()
2227 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_toggle_apd()
2254 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_phy_toggle_automdix()
2257 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_toggle_automdix()
2295 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) in tg3_phy_set_wirespeed()
2308 if (!tp->phy_otp) in tg3_phy_apply_otp()
2311 otp = tp->phy_otp; in tg3_phy_apply_otp()
2344 struct ethtool_eee *dest = &tp->eee; in tg3_eee_pull_config()
2346 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_eee_pull_config()
2358 dest->eee_active = 1; in tg3_eee_pull_config()
2360 dest->eee_active = 0; in tg3_eee_pull_config()
2365 dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val); in tg3_eee_pull_config()
2370 dest->eee_enabled = !!val; in tg3_eee_pull_config()
2371 dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val); in tg3_eee_pull_config()
2375 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX); in tg3_eee_pull_config()
2378 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff; in tg3_eee_pull_config()
2385 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_eee_adjust()
2388 tp->setlpicnt = 0; in tg3_phy_eee_adjust()
2390 if (tp->link_config.autoneg == AUTONEG_ENABLE && in tg3_phy_eee_adjust()
2392 tp->link_config.active_duplex == DUPLEX_FULL && in tg3_phy_eee_adjust()
2393 (tp->link_config.active_speed == SPEED_100 || in tg3_phy_eee_adjust()
2394 tp->link_config.active_speed == SPEED_1000)) { in tg3_phy_eee_adjust()
2397 if (tp->link_config.active_speed == SPEED_1000) in tg3_phy_eee_adjust()
2405 if (tp->eee.eee_active) in tg3_phy_eee_adjust()
2406 tp->setlpicnt = 2; in tg3_phy_eee_adjust()
2409 if (!tp->setlpicnt) { in tg3_phy_eee_adjust()
2425 if (tp->link_config.active_speed == SPEED_1000 && in tg3_phy_eee_enable()
2444 while (limit--) { in tg3_wait_macro_done()
2453 return -EBUSY; in tg3_wait_macro_done()
2482 return -EBUSY; in tg3_phy_write_and_check_testpat()
2490 return -EBUSY; in tg3_phy_write_and_check_testpat()
2496 return -EBUSY; in tg3_phy_write_and_check_testpat()
2506 return -EBUSY; in tg3_phy_write_and_check_testpat()
2516 return -EBUSY; in tg3_phy_write_and_check_testpat()
2538 return -EBUSY; in tg3_phy_reset_chanpat()
2566 /* Set full-duplex, 1000 mbps. */ in tg3_phy_reset_5703_4_5()
2587 } while (--retries); in tg3_phy_reset_5703_4_5()
2614 netif_carrier_off(tp->dev); in tg3_carrier_off()
2615 tp->link_up = false; in tg3_carrier_off()
2621 netdev_warn(tp->dev, in tg3_warn_mgmt_link_flap()
2622 "Management side-band traffic will be interrupted during phy settings change\n"); in tg3_warn_mgmt_link_flap()
2626 * link unless the FORCE argument is non-zero.
2641 return -EBUSY; in tg3_phy_reset()
2643 if (netif_running(tp->dev) && tp->link_up) { in tg3_phy_reset()
2644 netif_carrier_off(tp->dev); in tg3_phy_reset()
2689 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) in tg3_phy_reset()
2694 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) in tg3_phy_reset()
2700 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) && in tg3_phy_reset()
2707 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) { in tg3_phy_reset()
2712 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) { in tg3_phy_reset()
2719 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) { in tg3_phy_reset()
2722 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) { in tg3_phy_reset()
2735 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_reset()
2736 /* Cannot do read-modify-write on 5401 */ in tg3_phy_reset()
2739 /* Set bit 14 with read-modify-write to preserve other bits */ in tg3_phy_reset()
2795 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn; in tg3_set_function_status()
2817 return -EIO; in tg3_pwrsrc_switch_to_vmain()
2821 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, in tg3_pwrsrc_switch_to_vmain()
2826 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, in tg3_pwrsrc_switch_to_vmain()
2842 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1; in tg3_pwrsrc_die_with_vmain()
2864 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | in tg3_pwrsrc_switch_to_vaux()
2871 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_pwrsrc_switch_to_vaux()
2872 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { in tg3_pwrsrc_switch_to_vaux()
2873 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */ in tg3_pwrsrc_switch_to_vaux()
2879 tp->grc_local_ctrl; in tg3_pwrsrc_switch_to_vaux()
2897 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | in tg3_pwrsrc_switch_to_vaux()
2903 no_gpio2 = tp->nic_sram_data_cfg & in tg3_pwrsrc_switch_to_vaux()
2916 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2922 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2928 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2975 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) { in tg3_frob_aux_power()
2978 dev_peer = pci_get_drvdata(tp->pdev_peer); in tg3_frob_aux_power()
3005 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2) in tg3_5700_link_polarity()
3007 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) { in tg3_5700_link_polarity()
3023 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_phy_power_bug()
3027 if (!tp->pci_fn) in tg3_phy_power_bug()
3032 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_phy_power_bug()
3033 !tp->pci_fn) in tg3_phy_power_bug()
3046 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_phy_led_bug()
3047 !tp->pci_fn) in tg3_phy_led_bug()
3059 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) in tg3_power_down_phy()
3062 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_power_down_phy()
3081 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_power_down_phy()
3129 /* tp->lock is held. */
3135 if (tp->nvram_lock_cnt == 0) { in tg3_nvram_lock()
3144 return -ENODEV; in tg3_nvram_lock()
3147 tp->nvram_lock_cnt++; in tg3_nvram_lock()
3152 /* tp->lock is held. */
3156 if (tp->nvram_lock_cnt > 0) in tg3_nvram_unlock()
3157 tp->nvram_lock_cnt--; in tg3_nvram_unlock()
3158 if (tp->nvram_lock_cnt == 0) in tg3_nvram_unlock()
3163 /* tp->lock is held. */
3173 /* tp->lock is held. */
3190 return -EINVAL; in tg3_nvram_read_using_eeprom()
3210 return -EBUSY; in tg3_nvram_read_using_eeprom()
3239 return -EBUSY; in tg3_nvram_exec_cmd()
3250 (tp->nvram_jedecnum == JEDEC_ATMEL)) in tg3_nvram_phys_addr()
3252 addr = ((addr / tp->nvram_pagesize) << in tg3_nvram_phys_addr()
3254 (addr % tp->nvram_pagesize); in tg3_nvram_phys_addr()
3265 (tp->nvram_jedecnum == JEDEC_ATMEL)) in tg3_nvram_logical_addr()
3268 tp->nvram_pagesize) + in tg3_nvram_logical_addr()
3269 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1)); in tg3_nvram_logical_addr()
3278 * machine, the 32-bit value will be byteswapped.
3290 return -EINVAL; in tg3_nvram_read()
3363 rc = -EBUSY; in tg3_nvram_write_block_using_eeprom()
3376 u32 pagesize = tp->nvram_pagesize; in tg3_nvram_write_block_unbuffered()
3377 u32 pagemask = pagesize - 1; in tg3_nvram_write_block_unbuffered()
3383 return -ENOMEM; in tg3_nvram_write_block_unbuffered()
3405 len -= size; in tg3_nvram_write_block_unbuffered()
3409 offset = offset + (pagesize - page_off); in tg3_nvram_write_block_unbuffered()
3451 else if (j == (pagesize - 4)) in tg3_nvram_write_block_unbuffered()
3483 page_off = offset % tp->nvram_pagesize; in tg3_nvram_write_block_buffered()
3491 if (page_off == (tp->nvram_pagesize - 4)) in tg3_nvram_write_block_buffered()
3494 if (i == (len - 4)) in tg3_nvram_write_block_buffered()
3504 (tp->nvram_jedecnum == JEDEC_ST) && in tg3_nvram_write_block_buffered()
3531 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & in tg3_nvram_write_block()
3568 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_nvram_write_block()
3580 /* tp->lock is held. */
3591 if (pci_channel_offline(tp->pdev)) in tg3_pause_cpu()
3592 return -EBUSY; in tg3_pause_cpu()
3595 return (i == iters) ? -EBUSY : 0; in tg3_pause_cpu()
3598 /* tp->lock is held. */
3610 /* tp->lock is held. */
3616 /* tp->lock is held. */
3623 /* tp->lock is held. */
3629 /* tp->lock is held. */
3656 netdev_err(tp->dev, "%s timed out, %s CPU\n", in tg3_halt_cpu()
3658 return -ENODEV; in tg3_halt_cpu()
3676 * tp->fw->size minus headers. in tg3_fw_data_len()
3686 if (tp->fw_len == 0xffffffff) in tg3_fw_data_len()
3687 fw_len = be32_to_cpu(fw_hdr->len); in tg3_fw_data_len()
3689 fw_len = tp->fw->size; in tg3_fw_data_len()
3691 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32); in tg3_fw_data_len()
3694 /* tp->lock is held. */
3701 int total_len = tp->fw->size; in tg3_load_firmware_cpu()
3704 netdev_err(tp->dev, in tg3_load_firmware_cpu()
3707 return -EINVAL; in tg3_load_firmware_cpu()
3735 total_len -= TG3_FW_HDR_LEN; in tg3_load_firmware_cpu()
3743 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) + in tg3_load_firmware_cpu()
3747 total_len -= be32_to_cpu(fw_hdr->len); in tg3_load_firmware_cpu()
3751 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len)); in tg3_load_firmware_cpu()
3760 /* tp->lock is held. */
3778 return (i == iters) ? -EBUSY : 0; in tg3_pause_cpu_and_set_pc()
3781 /* tp->lock is held. */
3787 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_5701_a0_firmware_fix()
3791 length = end_address_of_bss - start_address_of_text. in tg3_load_5701_a0_firmware_fix()
3809 be32_to_cpu(fw_hdr->base_addr)); in tg3_load_5701_a0_firmware_fix()
3811 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x " in tg3_load_5701_a0_firmware_fix()
3814 be32_to_cpu(fw_hdr->base_addr)); in tg3_load_5701_a0_firmware_fix()
3815 return -ENODEV; in tg3_load_5701_a0_firmware_fix()
3840 netdev_err(tp->dev, "Boot code not ready for service patches\n"); in tg3_validate_rxcpu_state()
3841 return -EBUSY; in tg3_validate_rxcpu_state()
3846 netdev_warn(tp->dev, in tg3_validate_rxcpu_state()
3848 return -EEXIST; in tg3_validate_rxcpu_state()
3854 /* tp->lock is held. */
3865 if (!tp->fw) in tg3_load_57766_firmware()
3870 * data to be written to non-contiguous locations. in tg3_load_57766_firmware()
3882 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_57766_firmware()
3883 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR) in tg3_load_57766_firmware()
3895 /* tp->lock is held. */
3905 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_tso_firmware()
3909 length = end_address_of_bss - start_address_of_text. in tg3_load_tso_firmware()
3913 cpu_scratch_size = tp->fw_len; in tg3_load_tso_firmware()
3932 be32_to_cpu(fw_hdr->base_addr)); in tg3_load_tso_firmware()
3934 netdev_err(tp->dev, in tg3_load_tso_firmware()
3937 be32_to_cpu(fw_hdr->base_addr)); in tg3_load_tso_firmware()
3938 return -ENODEV; in tg3_load_tso_firmware()
3945 /* tp->lock is held. */
3959 index -= 4; in __tg3_set_one_mac_addr()
3965 /* tp->lock is held. */
3974 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i); in __tg3_set_mac_addr()
3980 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i); in __tg3_set_mac_addr()
3983 addr_high = (tp->dev->dev_addr[0] + in __tg3_set_mac_addr()
3984 tp->dev->dev_addr[1] + in __tg3_set_mac_addr()
3985 tp->dev->dev_addr[2] + in __tg3_set_mac_addr()
3986 tp->dev->dev_addr[3] + in __tg3_set_mac_addr()
3987 tp->dev->dev_addr[4] + in __tg3_set_mac_addr()
3988 tp->dev->dev_addr[5]) & in __tg3_set_mac_addr()
3999 pci_write_config_dword(tp->pdev, in tg3_enable_register_access()
4000 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl); in tg3_enable_register_access()
4009 err = pci_set_power_state(tp->pdev, PCI_D0); in tg3_power_up()
4014 netdev_err(tp->dev, "Transition to D0 failed\n"); in tg3_power_up()
4031 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_power_down_prepare()
4038 device_should_wake = device_may_wakeup(&tp->pdev->dev) && in tg3_power_down_prepare()
4043 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) && in tg3_power_down_prepare()
4044 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_power_down_prepare()
4049 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_power_down_prepare()
4051 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; in tg3_power_down_prepare()
4053 tp->link_config.speed = phydev->speed; in tg3_power_down_prepare()
4054 tp->link_config.duplex = phydev->duplex; in tg3_power_down_prepare()
4055 tp->link_config.autoneg = phydev->autoneg; in tg3_power_down_prepare()
4057 &tp->link_config.advertising, in tg3_power_down_prepare()
4058 phydev->advertising); in tg3_power_down_prepare()
4082 linkmode_copy(phydev->advertising, advertising); in tg3_power_down_prepare()
4085 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask; in tg3_power_down_prepare()
4097 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) in tg3_power_down_prepare()
4098 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; in tg3_power_down_prepare()
4100 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_power_down_prepare()
4129 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_power_down_prepare()
4131 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_power_down_prepare()
4140 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_power_down_prepare()
4142 else if (tp->phy_flags & in tg3_power_down_prepare()
4144 if (tp->link_config.active_speed == SPEED_1000) in tg3_power_down_prepare()
4151 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; in tg3_power_down_prepare()
4165 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_power_down_prepare()
4189 base_val = tp->pci_clock_ctrl; in tg3_power_down_prepare()
4216 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1, in tg3_power_down_prepare()
4219 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2, in tg3_power_down_prepare()
4235 tp->pci_clock_ctrl | newbits3, 40); in tg3_power_down_prepare()
4271 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE)); in tg3_power_down()
4272 pci_set_power_state(tp->pdev, PCI_D3hot); in tg3_power_down()
4309 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_aux_stat_to_speed_duplex()
4335 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_autoneg_cfg()
4347 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_autoneg_cfg()
4358 /* Advertise 100-BaseTX EEE ability */ in tg3_phy_autoneg_cfg()
4361 /* Advertise 1000-BaseT EEE ability */ in tg3_phy_autoneg_cfg()
4365 if (!tp->eee.eee_enabled) { in tg3_phy_autoneg_cfg()
4367 tp->eee.advertised = 0; in tg3_phy_autoneg_cfg()
4369 tp->eee.advertised = advertise & in tg3_phy_autoneg_cfg()
4408 if (tp->link_config.autoneg == AUTONEG_ENABLE || in tg3_phy_copper_begin()
4409 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_phy_copper_begin()
4412 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && in tg3_phy_copper_begin()
4413 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) { in tg3_phy_copper_begin()
4419 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) { in tg3_phy_copper_begin()
4420 if (!(tp->phy_flags & in tg3_phy_copper_begin()
4428 adv = tp->link_config.advertising; in tg3_phy_copper_begin()
4429 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_phy_copper_begin()
4433 fc = tp->link_config.flowctrl; in tg3_phy_copper_begin()
4438 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && in tg3_phy_copper_begin()
4439 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) { in tg3_phy_copper_begin()
4453 tp->link_config.active_speed = tp->link_config.speed; in tg3_phy_copper_begin()
4454 tp->link_config.active_duplex = tp->link_config.duplex; in tg3_phy_copper_begin()
4465 switch (tp->link_config.speed) { in tg3_phy_copper_begin()
4479 if (tp->link_config.duplex == DUPLEX_FULL) in tg3_phy_copper_begin()
4513 tp->link_config.autoneg = AUTONEG_DISABLE; in tg3_phy_pull_config()
4514 tp->link_config.advertising = 0; in tg3_phy_pull_config()
4517 err = -EIO; in tg3_phy_pull_config()
4521 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_phy_pull_config()
4524 tp->link_config.speed = SPEED_10; in tg3_phy_pull_config()
4527 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_phy_pull_config()
4530 tp->link_config.speed = SPEED_100; in tg3_phy_pull_config()
4533 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_pull_config()
4534 tp->link_config.speed = SPEED_1000; in tg3_phy_pull_config()
4543 tp->link_config.duplex = DUPLEX_FULL; in tg3_phy_pull_config()
4545 tp->link_config.duplex = DUPLEX_HALF; in tg3_phy_pull_config()
4547 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX; in tg3_phy_pull_config()
4553 tp->link_config.autoneg = AUTONEG_ENABLE; in tg3_phy_pull_config()
4554 tp->link_config.advertising = ADVERTISED_Autoneg; in tg3_phy_pull_config()
4557 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_phy_pull_config()
4565 tp->link_config.advertising |= adv | ADVERTISED_TP; in tg3_phy_pull_config()
4567 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val); in tg3_phy_pull_config()
4569 tp->link_config.advertising |= ADVERTISED_FIBRE; in tg3_phy_pull_config()
4572 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_pull_config()
4575 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_phy_pull_config()
4587 tp->link_config.flowctrl = adv; in tg3_phy_pull_config()
4593 tp->link_config.advertising |= adv; in tg3_phy_pull_config()
4623 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_eee_config_ok()
4628 if (tp->eee.eee_enabled) { in tg3_phy_eee_config_ok()
4629 if (tp->eee.advertised != eee.advertised || in tg3_phy_eee_config_ok()
4630 tp->eee.tx_lpi_timer != eee.tx_lpi_timer || in tg3_phy_eee_config_ok()
4631 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled) in tg3_phy_eee_config_ok()
4646 advertising = tp->link_config.advertising; in tg3_phy_copper_an_config_ok()
4650 if (tp->link_config.active_duplex == DUPLEX_FULL) { in tg3_phy_copper_an_config_ok()
4651 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl); in tg3_phy_copper_an_config_ok()
4661 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_copper_an_config_ok()
4690 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_copper_fetch_rmtadv()
4703 tp->link_config.rmt_adv = lpeth; in tg3_phy_copper_fetch_rmtadv()
4710 if (curr_link_up != tp->link_up) { in tg3_test_and_report_link_chg()
4712 netif_carrier_on(tp->dev); in tg3_test_and_report_link_chg()
4714 netif_carrier_off(tp->dev); in tg3_test_and_report_link_chg()
4715 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_test_and_report_link_chg()
4716 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_test_and_report_link_chg()
4753 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) | in tg3_setup_eee()
4763 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0); in tg3_setup_eee()
4767 (tp->eee.tx_lpi_timer & 0xffff)); in tg3_setup_eee()
4785 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in tg3_setup_copper_phy()
4787 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in tg3_setup_copper_phy()
4793 /* Some third-party PHYs need to be reset on link going in tg3_setup_copper_phy()
4799 tp->link_up) { in tg3_setup_copper_phy()
4808 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_setup_copper_phy()
4829 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) == in tg3_setup_copper_phy()
4832 tp->link_config.active_speed == SPEED_1000) { in tg3_setup_copper_phy()
4853 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) in tg3_setup_copper_phy()
4855 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) in tg3_setup_copper_phy()
4860 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) in tg3_setup_copper_phy()
4870 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE; in tg3_setup_copper_phy()
4871 tp->link_config.rmt_adv = 0; in tg3_setup_copper_phy()
4873 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) { in tg3_setup_copper_phy()
4922 tp->link_config.active_speed = current_speed; in tg3_setup_copper_phy()
4923 tp->link_config.active_duplex = current_duplex; in tg3_setup_copper_phy()
4925 if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_copper_phy()
4939 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_setup_copper_phy()
4946 tp->link_config.speed == current_speed && in tg3_setup_copper_phy()
4947 tp->link_config.duplex == current_duplex) { in tg3_setup_copper_phy()
4953 tp->link_config.active_duplex == DUPLEX_FULL) { in tg3_setup_copper_phy()
4956 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_setup_copper_phy()
4965 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE; in tg3_setup_copper_phy()
4972 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_setup_copper_phy()
4980 tp->link_config.active_speed = current_speed; in tg3_setup_copper_phy()
4981 tp->link_config.active_duplex = current_duplex; in tg3_setup_copper_phy()
4986 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) in tg3_setup_copper_phy()
4990 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; in tg3_setup_copper_phy()
4992 if (tp->link_config.active_speed == SPEED_100 || in tg3_setup_copper_phy()
4993 tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
4994 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_copper_phy()
4996 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_copper_phy()
4997 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_setup_copper_phy()
4998 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_copper_phy()
5000 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_copper_phy()
5009 if (tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
5011 else if (tp->link_config.active_speed == SPEED_100) in tg3_setup_copper_phy()
5014 else if (tp->link_config.active_speed == SPEED_1000) in tg3_setup_copper_phy()
5022 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; in tg3_setup_copper_phy()
5023 if (tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_copper_phy()
5024 tp->mac_mode |= MAC_MODE_HALF_DUPLEX; in tg3_setup_copper_phy()
5028 tg3_5700_link_polarity(tp, tp->link_config.active_speed)) in tg3_setup_copper_phy()
5029 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_setup_copper_phy()
5031 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; in tg3_setup_copper_phy()
5037 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 && in tg3_setup_copper_phy()
5039 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; in tg3_setup_copper_phy()
5040 tw32_f(MAC_MI_MODE, tp->mi_mode); in tg3_setup_copper_phy()
5044 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_copper_phy()
5059 tp->link_config.active_speed == SPEED_1000 && in tg3_setup_copper_phy()
5073 if (tp->link_config.active_speed == SPEED_100 || in tg3_setup_copper_phy()
5074 tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
5075 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_setup_copper_phy()
5078 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_setup_copper_phy()
5147 #define ANEG_FAILED -1
5159 if (ap->state == ANEG_STATE_UNKNOWN) { in tg3_fiber_aneg_smachine()
5160 ap->rxconfig = 0; in tg3_fiber_aneg_smachine()
5161 ap->link_time = 0; in tg3_fiber_aneg_smachine()
5162 ap->cur_time = 0; in tg3_fiber_aneg_smachine()
5163 ap->ability_match_cfg = 0; in tg3_fiber_aneg_smachine()
5164 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5165 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5166 ap->idle_match = 0; in tg3_fiber_aneg_smachine()
5167 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5169 ap->cur_time++; in tg3_fiber_aneg_smachine()
5174 if (rx_cfg_reg != ap->ability_match_cfg) { in tg3_fiber_aneg_smachine()
5175 ap->ability_match_cfg = rx_cfg_reg; in tg3_fiber_aneg_smachine()
5176 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5177 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5179 if (++ap->ability_match_count > 1) { in tg3_fiber_aneg_smachine()
5180 ap->ability_match = 1; in tg3_fiber_aneg_smachine()
5181 ap->ability_match_cfg = rx_cfg_reg; in tg3_fiber_aneg_smachine()
5185 ap->ack_match = 1; in tg3_fiber_aneg_smachine()
5187 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5189 ap->idle_match = 0; in tg3_fiber_aneg_smachine()
5191 ap->idle_match = 1; in tg3_fiber_aneg_smachine()
5192 ap->ability_match_cfg = 0; in tg3_fiber_aneg_smachine()
5193 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5194 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5195 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5200 ap->rxconfig = rx_cfg_reg; in tg3_fiber_aneg_smachine()
5203 switch (ap->state) { in tg3_fiber_aneg_smachine()
5205 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN)) in tg3_fiber_aneg_smachine()
5206 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5210 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX); in tg3_fiber_aneg_smachine()
5211 if (ap->flags & MR_AN_ENABLE) { in tg3_fiber_aneg_smachine()
5212 ap->link_time = 0; in tg3_fiber_aneg_smachine()
5213 ap->cur_time = 0; in tg3_fiber_aneg_smachine()
5214 ap->ability_match_cfg = 0; in tg3_fiber_aneg_smachine()
5215 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5216 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5217 ap->idle_match = 0; in tg3_fiber_aneg_smachine()
5218 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5220 ap->state = ANEG_STATE_RESTART_INIT; in tg3_fiber_aneg_smachine()
5222 ap->state = ANEG_STATE_DISABLE_LINK_OK; in tg3_fiber_aneg_smachine()
5227 ap->link_time = ap->cur_time; in tg3_fiber_aneg_smachine()
5228 ap->flags &= ~(MR_NP_LOADED); in tg3_fiber_aneg_smachine()
5229 ap->txconfig = 0; in tg3_fiber_aneg_smachine()
5231 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5232 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5236 ap->state = ANEG_STATE_RESTART; in tg3_fiber_aneg_smachine()
5240 delta = ap->cur_time - ap->link_time; in tg3_fiber_aneg_smachine()
5242 ap->state = ANEG_STATE_ABILITY_DETECT_INIT; in tg3_fiber_aneg_smachine()
5252 ap->flags &= ~(MR_TOGGLE_TX); in tg3_fiber_aneg_smachine()
5253 ap->txconfig = ANEG_CFG_FD; in tg3_fiber_aneg_smachine()
5254 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_fiber_aneg_smachine()
5256 ap->txconfig |= ANEG_CFG_PS1; in tg3_fiber_aneg_smachine()
5258 ap->txconfig |= ANEG_CFG_PS2; in tg3_fiber_aneg_smachine()
5259 tw32(MAC_TX_AUTO_NEG, ap->txconfig); in tg3_fiber_aneg_smachine()
5260 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5261 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5264 ap->state = ANEG_STATE_ABILITY_DETECT; in tg3_fiber_aneg_smachine()
5268 if (ap->ability_match != 0 && ap->rxconfig != 0) in tg3_fiber_aneg_smachine()
5269 ap->state = ANEG_STATE_ACK_DETECT_INIT; in tg3_fiber_aneg_smachine()
5273 ap->txconfig |= ANEG_CFG_ACK; in tg3_fiber_aneg_smachine()
5274 tw32(MAC_TX_AUTO_NEG, ap->txconfig); in tg3_fiber_aneg_smachine()
5275 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5276 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5279 ap->state = ANEG_STATE_ACK_DETECT; in tg3_fiber_aneg_smachine()
5283 if (ap->ack_match != 0) { in tg3_fiber_aneg_smachine()
5284 if ((ap->rxconfig & ~ANEG_CFG_ACK) == in tg3_fiber_aneg_smachine()
5285 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) { in tg3_fiber_aneg_smachine()
5286 ap->state = ANEG_STATE_COMPLETE_ACK_INIT; in tg3_fiber_aneg_smachine()
5288 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5290 } else if (ap->ability_match != 0 && in tg3_fiber_aneg_smachine()
5291 ap->rxconfig == 0) { in tg3_fiber_aneg_smachine()
5292 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5297 if (ap->rxconfig & ANEG_CFG_INVAL) { in tg3_fiber_aneg_smachine()
5301 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX | in tg3_fiber_aneg_smachine()
5310 if (ap->rxconfig & ANEG_CFG_FD) in tg3_fiber_aneg_smachine()
5311 ap->flags |= MR_LP_ADV_FULL_DUPLEX; in tg3_fiber_aneg_smachine()
5312 if (ap->rxconfig & ANEG_CFG_HD) in tg3_fiber_aneg_smachine()
5313 ap->flags |= MR_LP_ADV_HALF_DUPLEX; in tg3_fiber_aneg_smachine()
5314 if (ap->rxconfig & ANEG_CFG_PS1) in tg3_fiber_aneg_smachine()
5315 ap->flags |= MR_LP_ADV_SYM_PAUSE; in tg3_fiber_aneg_smachine()
5316 if (ap->rxconfig & ANEG_CFG_PS2) in tg3_fiber_aneg_smachine()
5317 ap->flags |= MR_LP_ADV_ASYM_PAUSE; in tg3_fiber_aneg_smachine()
5318 if (ap->rxconfig & ANEG_CFG_RF1) in tg3_fiber_aneg_smachine()
5319 ap->flags |= MR_LP_ADV_REMOTE_FAULT1; in tg3_fiber_aneg_smachine()
5320 if (ap->rxconfig & ANEG_CFG_RF2) in tg3_fiber_aneg_smachine()
5321 ap->flags |= MR_LP_ADV_REMOTE_FAULT2; in tg3_fiber_aneg_smachine()
5322 if (ap->rxconfig & ANEG_CFG_NP) in tg3_fiber_aneg_smachine()
5323 ap->flags |= MR_LP_ADV_NEXT_PAGE; in tg3_fiber_aneg_smachine()
5325 ap->link_time = ap->cur_time; in tg3_fiber_aneg_smachine()
5327 ap->flags ^= (MR_TOGGLE_TX); in tg3_fiber_aneg_smachine()
5328 if (ap->rxconfig & 0x0008) in tg3_fiber_aneg_smachine()
5329 ap->flags |= MR_TOGGLE_RX; in tg3_fiber_aneg_smachine()
5330 if (ap->rxconfig & ANEG_CFG_NP) in tg3_fiber_aneg_smachine()
5331 ap->flags |= MR_NP_RX; in tg3_fiber_aneg_smachine()
5332 ap->flags |= MR_PAGE_RX; in tg3_fiber_aneg_smachine()
5334 ap->state = ANEG_STATE_COMPLETE_ACK; in tg3_fiber_aneg_smachine()
5339 if (ap->ability_match != 0 && in tg3_fiber_aneg_smachine()
5340 ap->rxconfig == 0) { in tg3_fiber_aneg_smachine()
5341 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5344 delta = ap->cur_time - ap->link_time; in tg3_fiber_aneg_smachine()
5346 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) { in tg3_fiber_aneg_smachine()
5347 ap->state = ANEG_STATE_IDLE_DETECT_INIT; in tg3_fiber_aneg_smachine()
5349 if ((ap->txconfig & ANEG_CFG_NP) == 0 && in tg3_fiber_aneg_smachine()
5350 !(ap->flags & MR_NP_RX)) { in tg3_fiber_aneg_smachine()
5351 ap->state = ANEG_STATE_IDLE_DETECT_INIT; in tg3_fiber_aneg_smachine()
5360 ap->link_time = ap->cur_time; in tg3_fiber_aneg_smachine()
5361 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5362 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5365 ap->state = ANEG_STATE_IDLE_DETECT; in tg3_fiber_aneg_smachine()
5370 if (ap->ability_match != 0 && in tg3_fiber_aneg_smachine()
5371 ap->rxconfig == 0) { in tg3_fiber_aneg_smachine()
5372 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5375 delta = ap->cur_time - ap->link_time; in tg3_fiber_aneg_smachine()
5378 ap->state = ANEG_STATE_LINK_OK; in tg3_fiber_aneg_smachine()
5383 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK); in tg3_fiber_aneg_smachine()
5413 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; in fiber_autoneg()
5417 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); in fiber_autoneg()
5433 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; in fiber_autoneg()
5434 tw32_f(MAC_MODE, tp->mac_mode); in fiber_autoneg()
5472 /* Enable auto-lock and comdet, select txclk for tx. */ in tg3_init_bcm8002()
5517 /* preserve bits 0-11,13,14 for signal pre-emphasis */ in tg3_setup_fiber_hw_autoneg()
5518 /* preserve bits 20-23 for voltage regulator */ in tg3_setup_fiber_hw_autoneg()
5524 if (tp->link_config.autoneg != AUTONEG_ENABLE) { in tg3_setup_fiber_hw_autoneg()
5545 /* Want auto-negotiation. */ in tg3_setup_fiber_hw_autoneg()
5548 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_setup_fiber_hw_autoneg()
5555 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) && in tg3_setup_fiber_hw_autoneg()
5556 tp->serdes_counter && in tg3_setup_fiber_hw_autoneg()
5560 tp->serdes_counter--; in tg3_setup_fiber_hw_autoneg()
5571 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; in tg3_setup_fiber_hw_autoneg()
5572 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5592 tp->link_config.rmt_adv = in tg3_setup_fiber_hw_autoneg()
5597 tp->serdes_counter = 0; in tg3_setup_fiber_hw_autoneg()
5598 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5600 if (tp->serdes_counter) in tg3_setup_fiber_hw_autoneg()
5601 tp->serdes_counter--; in tg3_setup_fiber_hw_autoneg()
5617 /* Link parallel detection - link is up */ in tg3_setup_fiber_hw_autoneg()
5625 tp->phy_flags |= in tg3_setup_fiber_hw_autoneg()
5627 tp->serdes_counter = in tg3_setup_fiber_hw_autoneg()
5634 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; in tg3_setup_fiber_hw_autoneg()
5635 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5649 if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_fiber_by_hand()
5666 tp->link_config.rmt_adv = in tg3_setup_fiber_by_hand()
5696 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); in tg3_setup_fiber_by_hand()
5699 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_by_hand()
5716 orig_pause_cfg = tp->link_config.active_flowctrl; in tg3_setup_fiber_phy()
5717 orig_active_speed = tp->link_config.active_speed; in tg3_setup_fiber_phy()
5718 orig_active_duplex = tp->link_config.active_duplex; in tg3_setup_fiber_phy()
5721 tp->link_up && in tg3_setup_fiber_phy()
5738 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); in tg3_setup_fiber_phy()
5739 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; in tg3_setup_fiber_phy()
5740 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_phy()
5743 if (tp->phy_id == TG3_PHY_ID_BCM8002) in tg3_setup_fiber_phy()
5750 tp->link_config.rmt_adv = 0; in tg3_setup_fiber_phy()
5758 tp->napi[0].hw_status->status = in tg3_setup_fiber_phy()
5760 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG)); in tg3_setup_fiber_phy()
5775 if (tp->link_config.autoneg == AUTONEG_ENABLE && in tg3_setup_fiber_phy()
5776 tp->serdes_counter == 0) { in tg3_setup_fiber_phy()
5777 tw32_f(MAC_MODE, (tp->mac_mode | in tg3_setup_fiber_phy()
5780 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_phy()
5785 tp->link_config.active_speed = SPEED_1000; in tg3_setup_fiber_phy()
5786 tp->link_config.active_duplex = DUPLEX_FULL; in tg3_setup_fiber_phy()
5787 tw32(MAC_LED_CTRL, (tp->led_ctrl | in tg3_setup_fiber_phy()
5791 tp->link_config.active_speed = SPEED_UNKNOWN; in tg3_setup_fiber_phy()
5792 tp->link_config.active_duplex = DUPLEX_UNKNOWN; in tg3_setup_fiber_phy()
5793 tw32(MAC_LED_CTRL, (tp->led_ctrl | in tg3_setup_fiber_phy()
5799 u32 now_pause_cfg = tp->link_config.active_flowctrl; in tg3_setup_fiber_phy()
5801 orig_active_speed != tp->link_config.active_speed || in tg3_setup_fiber_phy()
5802 orig_active_duplex != tp->link_config.active_duplex) in tg3_setup_fiber_phy()
5826 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; in tg3_setup_fiber_mii_phy()
5829 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5834 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5837 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_fiber_mii_phy()
5840 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_fiber_mii_phy()
5849 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5857 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5858 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5866 tp->link_config.rmt_adv = 0; in tg3_setup_fiber_mii_phy()
5879 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset && in tg3_setup_fiber_mii_phy()
5880 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { in tg3_setup_fiber_mii_phy()
5882 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_fiber_mii_phy()
5891 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_setup_fiber_mii_phy()
5892 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising); in tg3_setup_fiber_mii_phy()
5900 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S; in tg3_setup_fiber_mii_phy()
5901 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_mii_phy()
5911 if (tp->link_config.duplex == DUPLEX_FULL) in tg3_setup_fiber_mii_phy()
5921 if (tp->link_up) { in tg3_setup_fiber_mii_phy()
5945 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_mii_phy()
5973 tp->link_config.rmt_adv = in tg3_setup_fiber_mii_phy()
5987 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; in tg3_setup_fiber_mii_phy()
5988 if (tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_fiber_mii_phy()
5989 tp->mac_mode |= MAC_MODE_HALF_DUPLEX; in tg3_setup_fiber_mii_phy()
5991 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5996 tp->link_config.active_speed = current_speed; in tg3_setup_fiber_mii_phy()
5997 tp->link_config.active_duplex = current_duplex; in tg3_setup_fiber_mii_phy()
6005 if (tp->serdes_counter) { in tg3_serdes_parallel_detect()
6007 tp->serdes_counter--; in tg3_serdes_parallel_detect()
6011 if (!tp->link_up && in tg3_serdes_parallel_detect()
6012 (tp->link_config.autoneg == AUTONEG_ENABLE)) { in tg3_serdes_parallel_detect()
6038 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT; in tg3_serdes_parallel_detect()
6041 } else if (tp->link_up && in tg3_serdes_parallel_detect()
6042 (tp->link_config.autoneg == AUTONEG_ENABLE) && in tg3_serdes_parallel_detect()
6043 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { in tg3_serdes_parallel_detect()
6057 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_serdes_parallel_detect()
6068 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_setup_phy()
6070 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_setup_phy()
6099 if (tp->link_config.active_speed == SPEED_1000 && in tg3_setup_phy()
6100 tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_phy()
6108 if (tp->link_up) { in tg3_setup_phy()
6110 tp->coal.stats_block_coalesce_usecs); in tg3_setup_phy()
6118 if (!tp->link_up) in tg3_setup_phy()
6120 tp->pwrmgmt_thresh; in tg3_setup_phy()
6129 /* tp->lock must be held */
6142 /* tp->lock must be held */
6159 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | in tg3_get_ts_info()
6164 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE | in tg3_get_ts_info()
6169 if (tp->ptp_clock) in tg3_get_ts_info()
6170 info->phc_index = ptp_clock_index(tp->ptp_clock); in tg3_get_ts_info()
6172 info->phc_index = -1; in tg3_get_ts_info()
6174 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); in tg3_get_ts_info()
6176 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | in tg3_get_ts_info()
6216 tp->ptp_adjust += delta; in tg3_ptp_adjtime()
6230 ns += tp->ptp_adjust; in tg3_ptp_gettimex()
6248 tp->ptp_adjust = 0; in tg3_ptp_settime()
6261 switch (rq->type) { in tg3_ptp_enable()
6264 if (rq->perout.flags) in tg3_ptp_enable()
6265 return -EOPNOTSUPP; in tg3_ptp_enable()
6267 if (rq->perout.index != 0) in tg3_ptp_enable()
6268 return -EINVAL; in tg3_ptp_enable()
6277 nsec = rq->perout.start.sec * 1000000000ULL + in tg3_ptp_enable()
6278 rq->perout.start.nsec; in tg3_ptp_enable()
6280 if (rq->perout.period.sec || rq->perout.period.nsec) { in tg3_ptp_enable()
6281 netdev_warn(tp->dev, in tg3_ptp_enable()
6282 "Device supports only a one-shot timesync output, period must be 0\n"); in tg3_ptp_enable()
6283 rval = -EINVAL; in tg3_ptp_enable()
6288 netdev_warn(tp->dev, in tg3_ptp_enable()
6290 rval = -EINVAL; in tg3_ptp_enable()
6314 return -EOPNOTSUPP; in tg3_ptp_enable()
6321 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) + in tg3_hwclock_to_timestamp()
6322 tp->ptp_adjust); in tg3_hwclock_to_timestamp()
6337 if (tp->ptp_txts_retrycnt > 2) in tg3_ptp_ts_aux_work()
6342 if (hwclock != tp->pre_tx_ts) { in tg3_ptp_ts_aux_work()
6344 skb_tstamp_tx(tp->tx_tstamp_skb, ×tamp); in tg3_ptp_ts_aux_work()
6347 tp->ptp_txts_retrycnt++; in tg3_ptp_ts_aux_work()
6350 dev_consume_skb_any(tp->tx_tstamp_skb); in tg3_ptp_ts_aux_work()
6351 tp->tx_tstamp_skb = NULL; in tg3_ptp_ts_aux_work()
6352 tp->ptp_txts_retrycnt = 0; in tg3_ptp_ts_aux_work()
6353 tp->pre_tx_ts = 0; in tg3_ptp_ts_aux_work()
6354 return -1; in tg3_ptp_ts_aux_work()
6374 /* tp->lock must be held */
6382 tp->ptp_adjust = 0; in tg3_ptp_init()
6383 tp->ptp_info = tg3_ptp_caps; in tg3_ptp_init()
6386 /* tp->lock must be held */
6392 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust); in tg3_ptp_resume()
6393 tp->ptp_adjust = 0; in tg3_ptp_resume()
6398 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock) in tg3_ptp_fini()
6401 ptp_clock_unregister(tp->ptp_clock); in tg3_ptp_fini()
6402 tp->ptp_clock = NULL; in tg3_ptp_fini()
6403 tp->ptp_adjust = 0; in tg3_ptp_fini()
6404 dev_consume_skb_any(tp->tx_tstamp_skb); in tg3_ptp_fini()
6405 tp->tx_tstamp_skb = NULL; in tg3_ptp_fini()
6410 return tp->irq_sync; in tg3_irq_sync()
6480 if (tp->pdev->error_state != pci_channel_io_normal) { in tg3_dump_state()
6481 netdev_err(tp->dev, "PCI channel ERROR!\n"); in tg3_dump_state()
6501 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", in tg3_dump_state()
6508 for (i = 0; i < tp->irq_cnt; i++) { in tg3_dump_state()
6509 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_dump_state()
6512 netdev_err(tp->dev, in tg3_dump_state()
6515 tnapi->hw_status->status, in tg3_dump_state()
6516 tnapi->hw_status->status_tag, in tg3_dump_state()
6517 tnapi->hw_status->rx_jumbo_consumer, in tg3_dump_state()
6518 tnapi->hw_status->rx_consumer, in tg3_dump_state()
6519 tnapi->hw_status->rx_mini_consumer, in tg3_dump_state()
6520 tnapi->hw_status->idx[0].rx_producer, in tg3_dump_state()
6521 tnapi->hw_status->idx[0].tx_consumer); in tg3_dump_state()
6523 netdev_err(tp->dev, in tg3_dump_state()
6526 tnapi->last_tag, tnapi->last_irq_tag, in tg3_dump_state()
6527 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending, in tg3_dump_state()
6528 tnapi->rx_rcb_ptr, in tg3_dump_state()
6529 tnapi->prodring.rx_std_prod_idx, in tg3_dump_state()
6530 tnapi->prodring.rx_std_cons_idx, in tg3_dump_state()
6531 tnapi->prodring.rx_jmb_prod_idx, in tg3_dump_state()
6532 tnapi->prodring.rx_jmb_cons_idx); in tg3_dump_state()
6536 /* This is called whenever we suspect that the system chipset is re-
6545 tp->write32_tx_mbox == tg3_write_indirect_mbox); in tg3_tx_recover()
6547 netdev_warn(tp->dev, in tg3_tx_recover()
6548 "The system may be re-ordering memory-mapped I/O " in tg3_tx_recover()
6560 return tnapi->tx_pending - in tg3_tx_avail()
6561 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1)); in tg3_tx_avail()
6570 struct tg3 *tp = tnapi->tp; in tg3_tx()
6571 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer; in tg3_tx()
6572 u32 sw_idx = tnapi->tx_cons; in tg3_tx()
6574 int index = tnapi - tp->napi; in tg3_tx()
6578 index--; in tg3_tx()
6580 txq = netdev_get_tx_queue(tp->dev, index); in tg3_tx()
6583 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx]; in tg3_tx()
6585 struct sk_buff *skb = ri->skb; in tg3_tx()
6593 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) { in tg3_tx()
6598 if (hwclock != tp->pre_tx_ts) { in tg3_tx()
6601 tp->pre_tx_ts = 0; in tg3_tx()
6603 tp->tx_tstamp_skb = skb; in tg3_tx()
6608 dma_unmap_single(&tp->pdev->dev, dma_unmap_addr(ri, mapping), in tg3_tx()
6611 ri->skb = NULL; in tg3_tx()
6613 while (ri->fragmented) { in tg3_tx()
6614 ri->fragmented = false; in tg3_tx()
6616 ri = &tnapi->tx_buffers[sw_idx]; in tg3_tx()
6621 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { in tg3_tx()
6622 ri = &tnapi->tx_buffers[sw_idx]; in tg3_tx()
6623 if (unlikely(ri->skb != NULL || sw_idx == hw_idx)) in tg3_tx()
6626 dma_unmap_page(&tp->pdev->dev, in tg3_tx()
6628 skb_frag_size(&skb_shinfo(skb)->frags[i]), in tg3_tx()
6631 while (ri->fragmented) { in tg3_tx()
6632 ri->fragmented = false; in tg3_tx()
6634 ri = &tnapi->tx_buffers[sw_idx]; in tg3_tx()
6641 bytes_compl += skb->len; in tg3_tx()
6646 ptp_schedule_worker(tp->ptp_clock, 0); in tg3_tx()
6656 tnapi->tx_cons = sw_idx; in tg3_tx()
6688 if (!ri->data) in tg3_rx_data_free()
6691 dma_unmap_single(&tp->pdev->dev, dma_unmap_addr(ri, mapping), map_sz, in tg3_rx_data_free()
6693 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data); in tg3_rx_data_free()
6694 ri->data = NULL; in tg3_rx_data_free()
6721 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; in tg3_alloc_rx_data()
6722 desc = &tpr->rx_std[dest_idx]; in tg3_alloc_rx_data()
6723 map = &tpr->rx_std_buffers[dest_idx]; in tg3_alloc_rx_data()
6724 data_size = tp->rx_pkt_map_sz; in tg3_alloc_rx_data()
6728 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; in tg3_alloc_rx_data()
6729 desc = &tpr->rx_jmb[dest_idx].std; in tg3_alloc_rx_data()
6730 map = &tpr->rx_jmb_buffers[dest_idx]; in tg3_alloc_rx_data()
6735 return -EINVAL; in tg3_alloc_rx_data()
6754 return -ENOMEM; in tg3_alloc_rx_data()
6756 mapping = dma_map_single(&tp->pdev->dev, data + TG3_RX_OFFSET(tp), in tg3_alloc_rx_data()
6758 if (unlikely(dma_mapping_error(&tp->pdev->dev, mapping))) { in tg3_alloc_rx_data()
6760 return -EIO; in tg3_alloc_rx_data()
6763 map->data = data; in tg3_alloc_rx_data()
6766 desc->addr_hi = ((u64)mapping >> 32); in tg3_alloc_rx_data()
6767 desc->addr_lo = ((u64)mapping & 0xffffffff); in tg3_alloc_rx_data()
6781 struct tg3 *tp = tnapi->tp; in tg3_recycle_rx()
6784 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring; in tg3_recycle_rx()
6789 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; in tg3_recycle_rx()
6790 dest_desc = &dpr->rx_std[dest_idx]; in tg3_recycle_rx()
6791 dest_map = &dpr->rx_std_buffers[dest_idx]; in tg3_recycle_rx()
6792 src_desc = &spr->rx_std[src_idx]; in tg3_recycle_rx()
6793 src_map = &spr->rx_std_buffers[src_idx]; in tg3_recycle_rx()
6797 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; in tg3_recycle_rx()
6798 dest_desc = &dpr->rx_jmb[dest_idx].std; in tg3_recycle_rx()
6799 dest_map = &dpr->rx_jmb_buffers[dest_idx]; in tg3_recycle_rx()
6800 src_desc = &spr->rx_jmb[src_idx].std; in tg3_recycle_rx()
6801 src_map = &spr->rx_jmb_buffers[src_idx]; in tg3_recycle_rx()
6808 dest_map->data = src_map->data; in tg3_recycle_rx()
6811 dest_desc->addr_hi = src_desc->addr_hi; in tg3_recycle_rx()
6812 dest_desc->addr_lo = src_desc->addr_lo; in tg3_recycle_rx()
6819 src_map->data = NULL; in tg3_recycle_rx()
6834 * it is first placed into the on-chip ram. When the packet's length
6842 * rings, then cache lines never move beyond shared-modified state.
6848 struct tg3 *tp = tnapi->tp; in tg3_rx()
6851 u32 sw_idx = tnapi->rx_rcb_ptr; in tg3_rx()
6854 struct tg3_rx_prodring_set *tpr = &tnapi->prodring; in tg3_rx()
6856 hw_idx = *(tnapi->rx_rcb_prod_idx); in tg3_rx()
6864 std_prod_idx = tpr->rx_std_prod_idx; in tg3_rx()
6865 jmb_prod_idx = tpr->rx_jmb_prod_idx; in tg3_rx()
6868 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx]; in tg3_rx()
6876 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; in tg3_rx()
6877 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; in tg3_rx()
6879 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx]; in tg3_rx()
6881 data = ri->data; in tg3_rx()
6885 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx]; in tg3_rx()
6887 data = ri->data; in tg3_rx()
6894 if (desc->err_vlan & RXD_ERR_MASK) { in tg3_rx()
6900 tnapi->rx_dropped++; in tg3_rx()
6905 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - in tg3_rx()
6908 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) == in tg3_rx()
6910 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) == in tg3_rx()
6925 dma_unmap_single(&tp->pdev->dev, dma_addr, skb_size, in tg3_rx()
6933 ri->data = NULL; in tg3_rx()
6948 skb = netdev_alloc_skb(tp->dev, in tg3_rx()
6954 dma_sync_single_for_cpu(&tp->pdev->dev, dma_addr, len, in tg3_rx()
6956 memcpy(skb->data, in tg3_rx()
6959 dma_sync_single_for_device(&tp->pdev->dev, dma_addr, in tg3_rx()
6968 if ((tp->dev->features & NETIF_F_RXCSUM) && in tg3_rx()
6969 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && in tg3_rx()
6970 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK) in tg3_rx()
6972 skb->ip_summed = CHECKSUM_UNNECESSARY; in tg3_rx()
6976 skb->protocol = eth_type_trans(skb, tp->dev); in tg3_rx()
6978 if (len > (tp->dev->mtu + ETH_HLEN) && in tg3_rx()
6979 skb->protocol != htons(ETH_P_8021Q) && in tg3_rx()
6980 skb->protocol != htons(ETH_P_8021AD)) { in tg3_rx()
6985 if (desc->type_flags & RXD_FLAG_VLAN && in tg3_rx()
6986 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) in tg3_rx()
6988 desc->err_vlan & RXD_VLAN_MASK); in tg3_rx()
6990 napi_gro_receive(&tnapi->napi, skb); in tg3_rx()
6993 budget--; in tg3_rx()
6998 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) { in tg3_rx()
6999 tpr->rx_std_prod_idx = std_prod_idx & in tg3_rx()
7000 tp->rx_std_ring_mask; in tg3_rx()
7002 tpr->rx_std_prod_idx); in tg3_rx()
7008 sw_idx &= tp->rx_ret_ring_mask; in tg3_rx()
7012 hw_idx = *(tnapi->rx_rcb_prod_idx); in tg3_rx()
7018 tnapi->rx_rcb_ptr = sw_idx; in tg3_rx()
7019 tw32_rx_mbox(tnapi->consmbox, sw_idx); in tg3_rx()
7027 tpr->rx_std_prod_idx = std_prod_idx & in tg3_rx()
7028 tp->rx_std_ring_mask; in tg3_rx()
7030 tpr->rx_std_prod_idx); in tg3_rx()
7033 tpr->rx_jmb_prod_idx = jmb_prod_idx & in tg3_rx()
7034 tp->rx_jmb_ring_mask; in tg3_rx()
7036 tpr->rx_jmb_prod_idx); in tg3_rx()
7044 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask; in tg3_rx()
7045 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask; in tg3_rx()
7047 if (tnapi != &tp->napi[1]) { in tg3_rx()
7048 tp->rx_refill = true; in tg3_rx()
7049 napi_schedule(&tp->napi[1].napi); in tg3_rx()
7060 struct tg3_hw_status *sblk = tp->napi[0].hw_status; in tg3_poll_link()
7062 if (sblk->status & SD_STATUS_LINK_CHG) { in tg3_poll_link()
7063 sblk->status = SD_STATUS_UPDATED | in tg3_poll_link()
7064 (sblk->status & ~SD_STATUS_LINK_CHG); in tg3_poll_link()
7065 spin_lock(&tp->lock); in tg3_poll_link()
7075 spin_unlock(&tp->lock); in tg3_poll_link()
7088 src_prod_idx = spr->rx_std_prod_idx; in tg3_rx_prodring_xfer()
7095 if (spr->rx_std_cons_idx == src_prod_idx) in tg3_rx_prodring_xfer()
7098 if (spr->rx_std_cons_idx < src_prod_idx) in tg3_rx_prodring_xfer()
7099 cpycnt = src_prod_idx - spr->rx_std_cons_idx; in tg3_rx_prodring_xfer()
7101 cpycnt = tp->rx_std_ring_mask + 1 - in tg3_rx_prodring_xfer()
7102 spr->rx_std_cons_idx; in tg3_rx_prodring_xfer()
7105 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx); in tg3_rx_prodring_xfer()
7107 si = spr->rx_std_cons_idx; in tg3_rx_prodring_xfer()
7108 di = dpr->rx_std_prod_idx; in tg3_rx_prodring_xfer()
7111 if (dpr->rx_std_buffers[i].data) { in tg3_rx_prodring_xfer()
7112 cpycnt = i - di; in tg3_rx_prodring_xfer()
7113 err = -ENOSPC; in tg3_rx_prodring_xfer()
7127 memcpy(&dpr->rx_std_buffers[di], in tg3_rx_prodring_xfer()
7128 &spr->rx_std_buffers[si], in tg3_rx_prodring_xfer()
7133 sbd = &spr->rx_std[si]; in tg3_rx_prodring_xfer()
7134 dbd = &dpr->rx_std[di]; in tg3_rx_prodring_xfer()
7135 dbd->addr_hi = sbd->addr_hi; in tg3_rx_prodring_xfer()
7136 dbd->addr_lo = sbd->addr_lo; in tg3_rx_prodring_xfer()
7139 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) & in tg3_rx_prodring_xfer()
7140 tp->rx_std_ring_mask; in tg3_rx_prodring_xfer()
7141 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) & in tg3_rx_prodring_xfer()
7142 tp->rx_std_ring_mask; in tg3_rx_prodring_xfer()
7146 src_prod_idx = spr->rx_jmb_prod_idx; in tg3_rx_prodring_xfer()
7153 if (spr->rx_jmb_cons_idx == src_prod_idx) in tg3_rx_prodring_xfer()
7156 if (spr->rx_jmb_cons_idx < src_prod_idx) in tg3_rx_prodring_xfer()
7157 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx; in tg3_rx_prodring_xfer()
7159 cpycnt = tp->rx_jmb_ring_mask + 1 - in tg3_rx_prodring_xfer()
7160 spr->rx_jmb_cons_idx; in tg3_rx_prodring_xfer()
7163 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx); in tg3_rx_prodring_xfer()
7165 si = spr->rx_jmb_cons_idx; in tg3_rx_prodring_xfer()
7166 di = dpr->rx_jmb_prod_idx; in tg3_rx_prodring_xfer()
7169 if (dpr->rx_jmb_buffers[i].data) { in tg3_rx_prodring_xfer()
7170 cpycnt = i - di; in tg3_rx_prodring_xfer()
7171 err = -ENOSPC; in tg3_rx_prodring_xfer()
7185 memcpy(&dpr->rx_jmb_buffers[di], in tg3_rx_prodring_xfer()
7186 &spr->rx_jmb_buffers[si], in tg3_rx_prodring_xfer()
7191 sbd = &spr->rx_jmb[si].std; in tg3_rx_prodring_xfer()
7192 dbd = &dpr->rx_jmb[di].std; in tg3_rx_prodring_xfer()
7193 dbd->addr_hi = sbd->addr_hi; in tg3_rx_prodring_xfer()
7194 dbd->addr_lo = sbd->addr_lo; in tg3_rx_prodring_xfer()
7197 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) & in tg3_rx_prodring_xfer()
7198 tp->rx_jmb_ring_mask; in tg3_rx_prodring_xfer()
7199 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) & in tg3_rx_prodring_xfer()
7200 tp->rx_jmb_ring_mask; in tg3_rx_prodring_xfer()
7208 struct tg3 *tp = tnapi->tp; in tg3_poll_work()
7211 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) { in tg3_poll_work()
7217 if (!tnapi->rx_rcb_prod_idx) in tg3_poll_work()
7222 * code synchronizes with tg3->napi.poll() in tg3_poll_work()
7224 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) in tg3_poll_work()
7225 work_done += tg3_rx(tnapi, budget - work_done); in tg3_poll_work()
7227 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) { in tg3_poll_work()
7228 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring; in tg3_poll_work()
7230 u32 std_prod_idx = dpr->rx_std_prod_idx; in tg3_poll_work()
7231 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx; in tg3_poll_work()
7233 tp->rx_refill = false; in tg3_poll_work()
7234 for (i = 1; i <= tp->rxq_cnt; i++) in tg3_poll_work()
7236 &tp->napi[i].prodring); in tg3_poll_work()
7240 if (std_prod_idx != dpr->rx_std_prod_idx) in tg3_poll_work()
7242 dpr->rx_std_prod_idx); in tg3_poll_work()
7244 if (jmb_prod_idx != dpr->rx_jmb_prod_idx) in tg3_poll_work()
7246 dpr->rx_jmb_prod_idx); in tg3_poll_work()
7249 tw32_f(HOSTCC_MODE, tp->coal_now); in tg3_poll_work()
7257 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags)) in tg3_reset_task_schedule()
7258 schedule_work(&tp->reset_task); in tg3_reset_task_schedule()
7263 if (test_and_clear_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags)) in tg3_reset_task_cancel()
7264 cancel_work_sync(&tp->reset_task); in tg3_reset_task_cancel()
7271 struct tg3 *tp = tnapi->tp; in tg3_poll_msix()
7273 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_poll_msix()
7284 /* tp->last_tag is used in tg3_int_reenable() below in tg3_poll_msix()
7288 tnapi->last_tag = sblk->status_tag; in tg3_poll_msix()
7289 tnapi->last_irq_tag = tnapi->last_tag; in tg3_poll_msix()
7293 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons && in tg3_poll_msix()
7294 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) { in tg3_poll_msix()
7299 if (tnapi == &tp->napi[1] && tp->rx_refill) in tg3_poll_msix()
7304 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_poll_msix()
7309 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) { in tg3_poll_msix()
7310 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_poll_msix()
7312 tnapi->coal_now); in tg3_poll_msix()
7339 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n"); in tg3_process_error()
7344 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n"); in tg3_process_error()
7349 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n"); in tg3_process_error()
7365 struct tg3 *tp = tnapi->tp; in tg3_poll()
7367 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_poll()
7370 if (sblk->status & SD_STATUS_ERROR) in tg3_poll()
7384 /* tp->last_tag is used in tg3_int_reenable() below in tg3_poll()
7388 tnapi->last_tag = sblk->status_tag; in tg3_poll()
7389 tnapi->last_irq_tag = tnapi->last_tag; in tg3_poll()
7392 sblk->status &= ~SD_STATUS_UPDATED; in tg3_poll()
7415 for (i = tp->irq_cnt - 1; i >= 0; i--) in tg3_napi_disable()
7416 napi_disable(&tp->napi[i].napi); in tg3_napi_disable()
7423 for (i = 0; i < tp->irq_cnt; i++) in tg3_napi_enable()
7424 napi_enable(&tp->napi[i].napi); in tg3_napi_enable()
7431 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll); in tg3_napi_init()
7432 for (i = 1; i < tp->irq_cnt; i++) in tg3_napi_init()
7433 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix); in tg3_napi_init()
7440 for (i = 0; i < tp->irq_cnt; i++) in tg3_napi_fini()
7441 netif_napi_del(&tp->napi[i].napi); in tg3_napi_fini()
7446 netif_trans_update(tp->dev); /* prevent tx timeout */ in tg3_netif_stop()
7448 netif_carrier_off(tp->dev); in tg3_netif_stop()
7449 netif_tx_disable(tp->dev); in tg3_netif_stop()
7452 /* tp->lock must be held */
7461 netif_tx_wake_all_queues(tp->dev); in tg3_netif_start()
7463 if (tp->link_up) in tg3_netif_start()
7464 netif_carrier_on(tp->dev); in tg3_netif_start()
7467 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED; in tg3_netif_start()
7472 __releases(tp->lock) in tg3_irq_quiesce()
7473 __acquires(tp->lock) in tg3_irq_quiesce()
7477 BUG_ON(tp->irq_sync); in tg3_irq_quiesce()
7479 tp->irq_sync = 1; in tg3_irq_quiesce()
7482 spin_unlock_bh(&tp->lock); in tg3_irq_quiesce()
7484 for (i = 0; i < tp->irq_cnt; i++) in tg3_irq_quiesce()
7485 synchronize_irq(tp->napi[i].irq_vec); in tg3_irq_quiesce()
7487 spin_lock_bh(&tp->lock); in tg3_irq_quiesce()
7491 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7497 spin_lock_bh(&tp->lock); in tg3_full_lock()
7504 spin_unlock_bh(&tp->lock); in tg3_full_unlock()
7507 /* One-shot MSI handler - Chip automatically disables interrupt
7513 struct tg3 *tp = tnapi->tp; in tg3_msi_1shot()
7515 prefetch(tnapi->hw_status); in tg3_msi_1shot()
7516 if (tnapi->rx_rcb) in tg3_msi_1shot()
7517 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); in tg3_msi_1shot()
7520 napi_schedule(&tnapi->napi); in tg3_msi_1shot()
7525 /* MSI ISR - No need to check for interrupt sharing and no need to
7532 struct tg3 *tp = tnapi->tp; in tg3_msi()
7534 prefetch(tnapi->hw_status); in tg3_msi()
7535 if (tnapi->rx_rcb) in tg3_msi()
7536 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); in tg3_msi()
7538 * Writing any value to intr-mbox-0 clears PCI INTA# and in tg3_msi()
7539 * chip-internal interrupt pending events. in tg3_msi()
7540 * Writing non-zero to intr-mbox-0 additional tells the in tg3_msi()
7541 * NIC to stop sending us irqs, engaging "in-intr-handler" in tg3_msi()
7544 tw32_mailbox(tnapi->int_mbox, 0x00000001); in tg3_msi()
7546 napi_schedule(&tnapi->napi); in tg3_msi()
7554 struct tg3 *tp = tnapi->tp; in tg3_interrupt()
7555 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_interrupt()
7563 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) { in tg3_interrupt()
7572 * Writing any value to intr-mbox-0 clears PCI INTA# and in tg3_interrupt()
7573 * chip-internal interrupt pending events. in tg3_interrupt()
7574 * Writing non-zero to intr-mbox-0 additional tells the in tg3_interrupt()
7575 * NIC to stop sending us irqs, engaging "in-intr-handler" in tg3_interrupt()
7578 * Flush the mailbox to de-assert the IRQ immediately to prevent in tg3_interrupt()
7585 sblk->status &= ~SD_STATUS_UPDATED; in tg3_interrupt()
7587 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); in tg3_interrupt()
7588 napi_schedule(&tnapi->napi); in tg3_interrupt()
7590 /* No work, shared interrupt perhaps? re-enable in tg3_interrupt()
7603 struct tg3 *tp = tnapi->tp; in tg3_interrupt_tagged()
7604 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_interrupt_tagged()
7612 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) { in tg3_interrupt_tagged()
7621 * writing any value to intr-mbox-0 clears PCI INTA# and in tg3_interrupt_tagged()
7622 * chip-internal interrupt pending events. in tg3_interrupt_tagged()
7623 * writing non-zero to intr-mbox-0 additional tells the in tg3_interrupt_tagged()
7624 * NIC to stop sending us irqs, engaging "in-intr-handler" in tg3_interrupt_tagged()
7627 * Flush the mailbox to de-assert the IRQ immediately to prevent in tg3_interrupt_tagged()
7639 tnapi->last_irq_tag = sblk->status_tag; in tg3_interrupt_tagged()
7644 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); in tg3_interrupt_tagged()
7646 napi_schedule(&tnapi->napi); in tg3_interrupt_tagged()
7656 struct tg3 *tp = tnapi->tp; in tg3_test_isr()
7657 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_test_isr()
7659 if ((sblk->status & SD_STATUS_UPDATED) || in tg3_test_isr()
7676 for (i = 0; i < tp->irq_cnt; i++) in tg3_poll_controller()
7677 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]); in tg3_poll_controller()
7715 /* Test for DMA addresses > 40-bit */
7732 txbd->addr_hi = ((u64) mapping >> 32); in tg3_tx_set_bd()
7733 txbd->addr_lo = ((u64) mapping & 0xffffffff); in tg3_tx_set_bd()
7734 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff); in tg3_tx_set_bd()
7735 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT); in tg3_tx_set_bd()
7742 struct tg3 *tp = tnapi->tp; in tg3_tx_frag_set()
7757 if (tp->dma_limit) { in tg3_tx_frag_set()
7760 while (len > tp->dma_limit && *budget) { in tg3_tx_frag_set()
7761 u32 frag_len = tp->dma_limit; in tg3_tx_frag_set()
7762 len -= tp->dma_limit; in tg3_tx_frag_set()
7766 len += tp->dma_limit / 2; in tg3_tx_frag_set()
7767 frag_len = tp->dma_limit / 2; in tg3_tx_frag_set()
7770 tnapi->tx_buffers[*entry].fragmented = true; in tg3_tx_frag_set()
7772 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, in tg3_tx_frag_set()
7774 *budget -= 1; in tg3_tx_frag_set()
7783 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, in tg3_tx_frag_set()
7785 *budget -= 1; in tg3_tx_frag_set()
7789 tnapi->tx_buffers[prvidx].fragmented = false; in tg3_tx_frag_set()
7793 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, in tg3_tx_frag_set()
7805 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry]; in tg3_tx_skb_unmap()
7807 skb = txb->skb; in tg3_tx_skb_unmap()
7808 txb->skb = NULL; in tg3_tx_skb_unmap()
7810 dma_unmap_single(&tnapi->tp->pdev->dev, dma_unmap_addr(txb, mapping), in tg3_tx_skb_unmap()
7813 while (txb->fragmented) { in tg3_tx_skb_unmap()
7814 txb->fragmented = false; in tg3_tx_skb_unmap()
7816 txb = &tnapi->tx_buffers[entry]; in tg3_tx_skb_unmap()
7820 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; in tg3_tx_skb_unmap()
7823 txb = &tnapi->tx_buffers[entry]; in tg3_tx_skb_unmap()
7825 dma_unmap_page(&tnapi->tp->pdev->dev, in tg3_tx_skb_unmap()
7829 while (txb->fragmented) { in tg3_tx_skb_unmap()
7830 txb->fragmented = false; in tg3_tx_skb_unmap()
7832 txb = &tnapi->tx_buffers[entry]; in tg3_tx_skb_unmap()
7837 /* Workaround 4GB and 40-bit hardware DMA bugs. */
7843 struct tg3 *tp = tnapi->tp; in tigon3_dma_hwbug_workaround()
7851 int more_headroom = 4 - ((unsigned long)skb->data & 3); in tigon3_dma_hwbug_workaround()
7859 ret = -1; in tigon3_dma_hwbug_workaround()
7862 new_addr = dma_map_single(&tp->pdev->dev, new_skb->data, in tigon3_dma_hwbug_workaround()
7863 new_skb->len, DMA_TO_DEVICE); in tigon3_dma_hwbug_workaround()
7865 if (dma_mapping_error(&tp->pdev->dev, new_addr)) { in tigon3_dma_hwbug_workaround()
7867 ret = -1; in tigon3_dma_hwbug_workaround()
7873 tnapi->tx_buffers[*entry].skb = new_skb; in tigon3_dma_hwbug_workaround()
7874 dma_unmap_addr_set(&tnapi->tx_buffers[*entry], in tigon3_dma_hwbug_workaround()
7878 new_skb->len, base_flags, in tigon3_dma_hwbug_workaround()
7880 tg3_tx_skb_unmap(tnapi, save_entry, -1); in tigon3_dma_hwbug_workaround()
7882 ret = -1; in tigon3_dma_hwbug_workaround()
7897 return skb_shinfo(skb)->gso_segs < tnapi->tx_pending / 3; in tg3_tso_bug_gso_check()
7908 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3; in tg3_tso_bug()
7927 segs = skb_gso_segment(skb, tp->dev->features & in tg3_tso_bug()
7930 tnapi->tx_dropped++; in tg3_tso_bug()
7936 __tg3_start_xmit(seg, tp->dev); in tg3_tso_bug()
7951 int i = -1, would_hit_hwbug; in __tg3_start_xmit()
7962 tnapi = &tp->napi[skb_get_queue_mapping(skb)]; in __tg3_start_xmit()
7969 * and TX reclaim runs via tp->napi.poll inside of a software in __tg3_start_xmit()
7973 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) { in __tg3_start_xmit()
7984 entry = tnapi->tx_prod; in __tg3_start_xmit()
7987 mss = skb_shinfo(skb)->gso_size; in __tg3_start_xmit()
7997 hdr_len = skb_tcp_all_headers(skb) - ETH_HLEN; in __tg3_start_xmit()
8002 if (skb->protocol == htons(ETH_P_8021Q) || in __tg3_start_xmit()
8003 skb->protocol == htons(ETH_P_8021AD)) { in __tg3_start_xmit()
8016 ip_csum = iph->check; in __tg3_start_xmit()
8017 ip_tot_len = iph->tot_len; in __tg3_start_xmit()
8018 iph->check = 0; in __tg3_start_xmit()
8019 iph->tot_len = htons(mss + hdr_len); in __tg3_start_xmit()
8026 tcp_csum = tcph->check; in __tg3_start_xmit()
8031 tcph->check = 0; in __tg3_start_xmit()
8034 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, in __tg3_start_xmit()
8047 if (tcp_opt_len || iph->ihl > 5) { in __tg3_start_xmit()
8050 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); in __tg3_start_xmit()
8054 if (tcp_opt_len || iph->ihl > 5) { in __tg3_start_xmit()
8057 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); in __tg3_start_xmit()
8061 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { in __tg3_start_xmit()
8065 if (skb->protocol == htons(ETH_P_8021Q) || in __tg3_start_xmit()
8066 skb->protocol == htons(ETH_P_8021AD)) { in __tg3_start_xmit()
8075 !mss && skb->len > VLAN_ETH_FRAME_LEN) in __tg3_start_xmit()
8083 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) && in __tg3_start_xmit()
8086 if (!tp->pre_tx_ts) { in __tg3_start_xmit()
8087 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; in __tg3_start_xmit()
8089 tg3_read_tx_tstamp(tp, &tp->pre_tx_ts); in __tg3_start_xmit()
8096 mapping = dma_map_single(&tp->pdev->dev, skb->data, len, in __tg3_start_xmit()
8098 if (dma_mapping_error(&tp->pdev->dev, mapping)) in __tg3_start_xmit()
8102 tnapi->tx_buffers[entry].skb = skb; in __tg3_start_xmit()
8103 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping); in __tg3_start_xmit()
8111 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0), in __tg3_start_xmit()
8114 } else if (skb_shinfo(skb)->nr_frags > 0) { in __tg3_start_xmit()
8125 last = skb_shinfo(skb)->nr_frags - 1; in __tg3_start_xmit()
8127 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; in __tg3_start_xmit()
8130 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0, in __tg3_start_xmit()
8133 tnapi->tx_buffers[entry].skb = NULL; in __tg3_start_xmit()
8134 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, in __tg3_start_xmit()
8136 if (dma_mapping_error(&tp->pdev->dev, mapping)) in __tg3_start_xmit()
8151 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i); in __tg3_start_xmit()
8158 iph->check = ip_csum; in __tg3_start_xmit()
8159 iph->tot_len = ip_tot_len; in __tg3_start_xmit()
8161 tcph->check = tcp_csum; in __tg3_start_xmit()
8168 entry = tnapi->tx_prod; in __tg3_start_xmit()
8176 netdev_tx_sent_queue(txq, skb->len); in __tg3_start_xmit()
8181 tnapi->tx_prod = entry; in __tg3_start_xmit()
8198 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i); in __tg3_start_xmit()
8199 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL; in __tg3_start_xmit()
8203 tnapi->tx_dropped++; in __tg3_start_xmit()
8232 tnapi = &tp->napi[skb_queue_mapping]; in tg3_start_xmit()
8237 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod); in tg3_start_xmit()
8246 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX | in tg3_mac_loopback()
8249 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK; in tg3_mac_loopback()
8252 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_mac_loopback()
8254 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_mac_loopback()
8255 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_mac_loopback()
8257 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_mac_loopback()
8259 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK; in tg3_mac_loopback()
8262 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) || in tg3_mac_loopback()
8264 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; in tg3_mac_loopback()
8267 tw32(MAC_MODE, tp->mac_mode); in tg3_mac_loopback()
8279 return -EIO; in tg3_phy_lpbk_set()
8290 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_lpbk_set()
8300 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_phy_lpbk_set()
8316 if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_phy_lpbk_set()
8321 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && in tg3_phy_lpbk_set()
8332 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_phy_lpbk_set()
8336 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_phy_lpbk_set()
8339 mac_mode = tp->mac_mode & in tg3_phy_lpbk_set()
8347 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK; in tg3_phy_lpbk_set()
8369 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK) in tg3_set_loopback()
8372 spin_lock_bh(&tp->lock); in tg3_set_loopback()
8374 netif_carrier_on(tp->dev); in tg3_set_loopback()
8375 spin_unlock_bh(&tp->lock); in tg3_set_loopback()
8378 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) in tg3_set_loopback()
8381 spin_lock_bh(&tp->lock); in tg3_set_loopback()
8385 spin_unlock_bh(&tp->lock); in tg3_set_loopback()
8395 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS)) in tg3_fix_features()
8403 netdev_features_t changed = dev->features ^ features; in tg3_set_features()
8416 if (tpr != &tp->napi[0].prodring) { in tg3_rx_prodring_free()
8417 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx; in tg3_rx_prodring_free()
8418 i = (i + 1) & tp->rx_std_ring_mask) in tg3_rx_prodring_free()
8419 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], in tg3_rx_prodring_free()
8420 tp->rx_pkt_map_sz); in tg3_rx_prodring_free()
8423 for (i = tpr->rx_jmb_cons_idx; in tg3_rx_prodring_free()
8424 i != tpr->rx_jmb_prod_idx; in tg3_rx_prodring_free()
8425 i = (i + 1) & tp->rx_jmb_ring_mask) { in tg3_rx_prodring_free()
8426 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], in tg3_rx_prodring_free()
8434 for (i = 0; i <= tp->rx_std_ring_mask; i++) in tg3_rx_prodring_free()
8435 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], in tg3_rx_prodring_free()
8436 tp->rx_pkt_map_sz); in tg3_rx_prodring_free()
8439 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) in tg3_rx_prodring_free()
8440 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], in tg3_rx_prodring_free()
8449 * end up in the driver. tp->{tx,}lock are held and thus
8457 tpr->rx_std_cons_idx = 0; in tg3_rx_prodring_alloc()
8458 tpr->rx_std_prod_idx = 0; in tg3_rx_prodring_alloc()
8459 tpr->rx_jmb_cons_idx = 0; in tg3_rx_prodring_alloc()
8460 tpr->rx_jmb_prod_idx = 0; in tg3_rx_prodring_alloc()
8462 if (tpr != &tp->napi[0].prodring) { in tg3_rx_prodring_alloc()
8463 memset(&tpr->rx_std_buffers[0], 0, in tg3_rx_prodring_alloc()
8465 if (tpr->rx_jmb_buffers) in tg3_rx_prodring_alloc()
8466 memset(&tpr->rx_jmb_buffers[0], 0, in tg3_rx_prodring_alloc()
8472 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp)); in tg3_rx_prodring_alloc()
8476 tp->dev->mtu > ETH_DATA_LEN) in tg3_rx_prodring_alloc()
8478 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz); in tg3_rx_prodring_alloc()
8484 for (i = 0; i <= tp->rx_std_ring_mask; i++) { in tg3_rx_prodring_alloc()
8487 rxd = &tpr->rx_std[i]; in tg3_rx_prodring_alloc()
8488 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT; in tg3_rx_prodring_alloc()
8489 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT); in tg3_rx_prodring_alloc()
8490 rxd->opaque = (RXD_OPAQUE_RING_STD | in tg3_rx_prodring_alloc()
8495 for (i = 0; i < tp->rx_pending; i++) { in tg3_rx_prodring_alloc()
8500 netdev_warn(tp->dev, in tg3_rx_prodring_alloc()
8503 "successfully\n", i, tp->rx_pending); in tg3_rx_prodring_alloc()
8506 tp->rx_pending = i; in tg3_rx_prodring_alloc()
8514 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp)); in tg3_rx_prodring_alloc()
8519 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) { in tg3_rx_prodring_alloc()
8522 rxd = &tpr->rx_jmb[i].std; in tg3_rx_prodring_alloc()
8523 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT; in tg3_rx_prodring_alloc()
8524 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) | in tg3_rx_prodring_alloc()
8526 rxd->opaque = (RXD_OPAQUE_RING_JUMBO | in tg3_rx_prodring_alloc()
8530 for (i = 0; i < tp->rx_jumbo_pending; i++) { in tg3_rx_prodring_alloc()
8535 netdev_warn(tp->dev, in tg3_rx_prodring_alloc()
8538 "successfully\n", i, tp->rx_jumbo_pending); in tg3_rx_prodring_alloc()
8541 tp->rx_jumbo_pending = i; in tg3_rx_prodring_alloc()
8551 return -ENOMEM; in tg3_rx_prodring_alloc()
8557 kfree(tpr->rx_std_buffers); in tg3_rx_prodring_fini()
8558 tpr->rx_std_buffers = NULL; in tg3_rx_prodring_fini()
8559 kfree(tpr->rx_jmb_buffers); in tg3_rx_prodring_fini()
8560 tpr->rx_jmb_buffers = NULL; in tg3_rx_prodring_fini()
8561 if (tpr->rx_std) { in tg3_rx_prodring_fini()
8562 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp), in tg3_rx_prodring_fini()
8563 tpr->rx_std, tpr->rx_std_mapping); in tg3_rx_prodring_fini()
8564 tpr->rx_std = NULL; in tg3_rx_prodring_fini()
8566 if (tpr->rx_jmb) { in tg3_rx_prodring_fini()
8567 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp), in tg3_rx_prodring_fini()
8568 tpr->rx_jmb, tpr->rx_jmb_mapping); in tg3_rx_prodring_fini()
8569 tpr->rx_jmb = NULL; in tg3_rx_prodring_fini()
8576 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp), in tg3_rx_prodring_init()
8578 if (!tpr->rx_std_buffers) in tg3_rx_prodring_init()
8579 return -ENOMEM; in tg3_rx_prodring_init()
8581 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev, in tg3_rx_prodring_init()
8583 &tpr->rx_std_mapping, in tg3_rx_prodring_init()
8585 if (!tpr->rx_std) in tg3_rx_prodring_init()
8589 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp), in tg3_rx_prodring_init()
8591 if (!tpr->rx_jmb_buffers) in tg3_rx_prodring_init()
8594 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev, in tg3_rx_prodring_init()
8596 &tpr->rx_jmb_mapping, in tg3_rx_prodring_init()
8598 if (!tpr->rx_jmb) in tg3_rx_prodring_init()
8606 return -ENOMEM; in tg3_rx_prodring_init()
8613 * end up in the driver. tp->{tx,}lock is not held and we are not
8620 for (j = 0; j < tp->irq_cnt; j++) { in tg3_free_rings()
8621 struct tg3_napi *tnapi = &tp->napi[j]; in tg3_free_rings()
8623 tg3_rx_prodring_free(tp, &tnapi->prodring); in tg3_free_rings()
8625 if (!tnapi->tx_buffers) in tg3_free_rings()
8629 struct sk_buff *skb = tnapi->tx_buffers[i].skb; in tg3_free_rings()
8635 skb_shinfo(skb)->nr_frags - 1); in tg3_free_rings()
8639 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j)); in tg3_free_rings()
8647 * end up in the driver. tp->{tx,}lock are held and thus
8657 for (i = 0; i < tp->irq_cnt; i++) { in tg3_init_rings()
8658 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_init_rings()
8660 tnapi->last_tag = 0; in tg3_init_rings()
8661 tnapi->last_irq_tag = 0; in tg3_init_rings()
8662 tnapi->hw_status->status = 0; in tg3_init_rings()
8663 tnapi->hw_status->status_tag = 0; in tg3_init_rings()
8664 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_init_rings()
8666 tnapi->tx_prod = 0; in tg3_init_rings()
8667 tnapi->tx_cons = 0; in tg3_init_rings()
8668 if (tnapi->tx_ring) in tg3_init_rings()
8669 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES); in tg3_init_rings()
8671 tnapi->rx_rcb_ptr = 0; in tg3_init_rings()
8672 if (tnapi->rx_rcb) in tg3_init_rings()
8673 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); in tg3_init_rings()
8675 if (tnapi->prodring.rx_std && in tg3_init_rings()
8676 tg3_rx_prodring_alloc(tp, &tnapi->prodring)) { in tg3_init_rings()
8678 return -ENOMEM; in tg3_init_rings()
8689 for (i = 0; i < tp->irq_max; i++) { in tg3_mem_tx_release()
8690 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_tx_release()
8692 if (tnapi->tx_ring) { in tg3_mem_tx_release()
8693 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES, in tg3_mem_tx_release()
8694 tnapi->tx_ring, tnapi->tx_desc_mapping); in tg3_mem_tx_release()
8695 tnapi->tx_ring = NULL; in tg3_mem_tx_release()
8698 kfree(tnapi->tx_buffers); in tg3_mem_tx_release()
8699 tnapi->tx_buffers = NULL; in tg3_mem_tx_release()
8706 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_mem_tx_acquire()
8714 for (i = 0; i < tp->txq_cnt; i++, tnapi++) { in tg3_mem_tx_acquire()
8715 tnapi->tx_buffers = kcalloc(TG3_TX_RING_SIZE, in tg3_mem_tx_acquire()
8718 if (!tnapi->tx_buffers) in tg3_mem_tx_acquire()
8721 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev, in tg3_mem_tx_acquire()
8723 &tnapi->tx_desc_mapping, in tg3_mem_tx_acquire()
8725 if (!tnapi->tx_ring) in tg3_mem_tx_acquire()
8733 return -ENOMEM; in tg3_mem_tx_acquire()
8740 for (i = 0; i < tp->irq_max; i++) { in tg3_mem_rx_release()
8741 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_rx_release()
8743 tg3_rx_prodring_fini(tp, &tnapi->prodring); in tg3_mem_rx_release()
8745 if (!tnapi->rx_rcb) in tg3_mem_rx_release()
8748 dma_free_coherent(&tp->pdev->dev, in tg3_mem_rx_release()
8750 tnapi->rx_rcb, in tg3_mem_rx_release()
8751 tnapi->rx_rcb_mapping); in tg3_mem_rx_release()
8752 tnapi->rx_rcb = NULL; in tg3_mem_rx_release()
8760 limit = tp->rxq_cnt; in tg3_mem_rx_acquire()
8769 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_rx_acquire()
8771 if (tg3_rx_prodring_init(tp, &tnapi->prodring)) in tg3_mem_rx_acquire()
8781 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev, in tg3_mem_rx_acquire()
8783 &tnapi->rx_rcb_mapping, in tg3_mem_rx_acquire()
8785 if (!tnapi->rx_rcb) in tg3_mem_rx_acquire()
8793 return -ENOMEM; in tg3_mem_rx_acquire()
8804 for (i = 0; i < tp->irq_cnt; i++) { in tg3_free_consistent()
8805 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_free_consistent()
8807 if (tnapi->hw_status) { in tg3_free_consistent()
8808 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE, in tg3_free_consistent()
8809 tnapi->hw_status, in tg3_free_consistent()
8810 tnapi->status_mapping); in tg3_free_consistent()
8811 tnapi->hw_status = NULL; in tg3_free_consistent()
8818 /* tp->hw_stats can be referenced safely: in tg3_free_consistent()
8820 * 2. or under tp->lock if TG3_FLAG_INIT_COMPLETE is set. in tg3_free_consistent()
8822 if (tp->hw_stats) { in tg3_free_consistent()
8823 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats), in tg3_free_consistent()
8824 tp->hw_stats, tp->stats_mapping); in tg3_free_consistent()
8825 tp->hw_stats = NULL; in tg3_free_consistent()
8837 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev, in tg3_alloc_consistent()
8839 &tp->stats_mapping, GFP_KERNEL); in tg3_alloc_consistent()
8840 if (!tp->hw_stats) in tg3_alloc_consistent()
8843 for (i = 0; i < tp->irq_cnt; i++) { in tg3_alloc_consistent()
8844 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_alloc_consistent()
8847 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev, in tg3_alloc_consistent()
8849 &tnapi->status_mapping, in tg3_alloc_consistent()
8851 if (!tnapi->hw_status) in tg3_alloc_consistent()
8854 sblk = tnapi->hw_status; in tg3_alloc_consistent()
8867 prodptr = &sblk->idx[0].rx_producer; in tg3_alloc_consistent()
8870 prodptr = &sblk->rx_jumbo_consumer; in tg3_alloc_consistent()
8873 prodptr = &sblk->reserved; in tg3_alloc_consistent()
8876 prodptr = &sblk->rx_mini_consumer; in tg3_alloc_consistent()
8879 tnapi->rx_rcb_prod_idx = prodptr; in tg3_alloc_consistent()
8881 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer; in tg3_alloc_consistent()
8892 return -ENOMEM; in tg3_alloc_consistent()
8898 * clears. tp->lock is held.
8927 if (pci_channel_offline(tp->pdev)) { in tg3_stop_block()
8928 dev_err(&tp->pdev->dev, in tg3_stop_block()
8932 return -ENODEV; in tg3_stop_block()
8942 dev_err(&tp->pdev->dev, in tg3_stop_block()
8945 return -ENODEV; in tg3_stop_block()
8951 /* tp->lock is held. */
8958 if (pci_channel_offline(tp->pdev)) { in tg3_abort_hw()
8959 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE); in tg3_abort_hw()
8960 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; in tg3_abort_hw()
8961 err = -ENODEV; in tg3_abort_hw()
8965 tp->rx_mode &= ~RX_MODE_ENABLE; in tg3_abort_hw()
8966 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_abort_hw()
8984 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; in tg3_abort_hw()
8985 tw32_f(MAC_MODE, tp->mac_mode); in tg3_abort_hw()
8988 tp->tx_mode &= ~TX_MODE_ENABLE; in tg3_abort_hw()
8989 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_abort_hw()
8997 dev_err(&tp->pdev->dev, in tg3_abort_hw()
9000 err |= -ENODEV; in tg3_abort_hw()
9014 for (i = 0; i < tp->irq_cnt; i++) { in tg3_abort_hw()
9015 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_abort_hw()
9016 if (tnapi->hw_status) in tg3_abort_hw()
9017 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_abort_hw()
9026 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd); in tg3_save_pci_state()
9034 /* Re-enable indirect register accesses. */ in tg3_restore_pci_state()
9035 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_restore_pci_state()
9036 tp->misc_host_ctrl); in tg3_restore_pci_state()
9048 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); in tg3_restore_pci_state()
9050 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); in tg3_restore_pci_state()
9053 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, in tg3_restore_pci_state()
9054 tp->pci_cacheline_sz); in tg3_restore_pci_state()
9055 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_restore_pci_state()
9056 tp->pci_lat_timer); in tg3_restore_pci_state()
9059 /* Make sure PCI-X relaxed ordering bit is clear. */ in tg3_restore_pci_state()
9063 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_restore_pci_state()
9066 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_restore_pci_state()
9078 pci_read_config_word(tp->pdev, in tg3_restore_pci_state()
9079 tp->msi_cap + PCI_MSI_FLAGS, in tg3_restore_pci_state()
9081 pci_write_config_word(tp->pdev, in tg3_restore_pci_state()
9082 tp->msi_cap + PCI_MSI_FLAGS, in tg3_restore_pci_state()
9133 /* tp->lock is held. */
9135 __releases(tp->lock) in tg3_chip_reset()
9136 __acquires(tp->lock) in tg3_chip_reset()
9142 if (!pci_device_is_present(tp->pdev)) in tg3_chip_reset()
9143 return -ENODEV; in tg3_chip_reset()
9152 tp->nvram_lock_cnt = 0; in tg3_chip_reset()
9170 write_op = tp->write32; in tg3_chip_reset()
9172 tp->write32 = tg3_write32; in tg3_chip_reset()
9181 for (i = 0; i < tp->irq_cnt; i++) { in tg3_chip_reset()
9182 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_chip_reset()
9183 if (tnapi->hw_status) { in tg3_chip_reset()
9184 tnapi->hw_status->status = 0; in tg3_chip_reset()
9185 tnapi->hw_status->status_tag = 0; in tg3_chip_reset()
9187 tnapi->last_tag = 0; in tg3_chip_reset()
9188 tnapi->last_irq_tag = 0; in tg3_chip_reset()
9194 for (i = 0; i < tp->irq_cnt; i++) in tg3_chip_reset()
9195 synchronize_irq(tp->napi[i].irq_vec); in tg3_chip_reset()
9241 tp->write32 = write_op; in tg3_chip_reset()
9264 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); in tg3_chip_reset()
9268 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) { in tg3_chip_reset()
9279 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); in tg3_chip_reset()
9280 pci_write_config_dword(tp->pdev, 0xc4, in tg3_chip_reset()
9292 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16); in tg3_chip_reset()
9295 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA, in tg3_chip_reset()
9331 tw32(GRC_MODE, tp->grc_mode); in tg3_chip_reset()
9339 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && in tg3_chip_reset()
9341 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE; in tg3_chip_reset()
9343 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN; in tg3_chip_reset()
9344 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); in tg3_chip_reset()
9347 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_chip_reset()
9348 tp->mac_mode = MAC_MODE_PORT_MODE_TBI; in tg3_chip_reset()
9349 val = tp->mac_mode; in tg3_chip_reset()
9350 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { in tg3_chip_reset()
9351 tp->mac_mode = MAC_MODE_PORT_MODE_GMII; in tg3_chip_reset()
9352 val = tp->mac_mode; in tg3_chip_reset()
9385 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK | in tg3_chip_reset()
9396 tp->last_event_jiffies = jiffies; in tg3_chip_reset()
9402 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK; in tg3_chip_reset()
9404 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN; in tg3_chip_reset()
9415 /* tp->lock is held. */
9432 if (tp->hw_stats) { in tg3_halt()
9434 tg3_get_nstats(tp, &tp->net_stats_prev); in tg3_halt()
9435 tg3_get_estats(tp, &tp->estats_prev); in tg3_halt()
9438 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); in tg3_halt()
9441 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_halt()
9443 tnapi->rx_dropped = 0; in tg3_halt()
9444 tnapi->tx_dropped = 0; in tg3_halt()
9458 if (!is_valid_ether_addr(addr->sa_data)) in tg3_set_mac_addr()
9459 return -EADDRNOTAVAIL; in tg3_set_mac_addr()
9461 eth_hw_addr_set(dev, addr->sa_data); in tg3_set_mac_addr()
9479 spin_lock_bh(&tp->lock); in tg3_set_mac_addr()
9482 spin_unlock_bh(&tp->lock); in tg3_set_mac_addr()
9487 /* tp->lock is held. */
9514 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs); in tg3_coal_tx_init()
9515 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames); in tg3_coal_tx_init()
9516 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq); in tg3_coal_tx_init()
9522 for (; i < tp->txq_cnt; i++) { in tg3_coal_tx_init()
9526 tw32(reg, ec->tx_coalesce_usecs); in tg3_coal_tx_init()
9528 tw32(reg, ec->tx_max_coalesced_frames); in tg3_coal_tx_init()
9530 tw32(reg, ec->tx_max_coalesced_frames_irq); in tg3_coal_tx_init()
9534 for (; i < tp->irq_max - 1; i++) { in tg3_coal_tx_init()
9544 u32 limit = tp->rxq_cnt; in tg3_coal_rx_init()
9547 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs); in tg3_coal_rx_init()
9548 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames); in tg3_coal_rx_init()
9549 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq); in tg3_coal_rx_init()
9550 limit--; in tg3_coal_rx_init()
9561 tw32(reg, ec->rx_coalesce_usecs); in tg3_coal_rx_init()
9563 tw32(reg, ec->rx_max_coalesced_frames); in tg3_coal_rx_init()
9565 tw32(reg, ec->rx_max_coalesced_frames_irq); in tg3_coal_rx_init()
9568 for (; i < tp->irq_max - 1; i++) { in tg3_coal_rx_init()
9581 u32 val = ec->stats_block_coalesce_usecs; in __tg3_set_coalesce()
9583 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq); in __tg3_set_coalesce()
9584 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq); in __tg3_set_coalesce()
9586 if (!tp->link_up) in __tg3_set_coalesce()
9593 /* tp->lock is held. */
9615 /* tp->lock is held. */
9624 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) { in tg3_tx_rcbs_init()
9625 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_tx_rcbs_init()
9627 if (!tnapi->tx_ring) in tg3_tx_rcbs_init()
9630 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, in tg3_tx_rcbs_init()
9636 /* tp->lock is held. */
9659 /* tp->lock is held. */
9668 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) { in tg3_rx_ret_rcbs_init()
9669 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_rx_ret_rcbs_init()
9671 if (!tnapi->rx_rcb) in tg3_rx_ret_rcbs_init()
9674 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, in tg3_rx_ret_rcbs_init()
9675 (tp->rx_ret_ring_mask + 1) << in tg3_rx_ret_rcbs_init()
9680 /* tp->lock is held. */
9685 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_rings_reset()
9692 tw32_mailbox_f(tp->napi[0].int_mbox, 1); in tg3_rings_reset()
9693 tp->napi[0].chk_msi_cnt = 0; in tg3_rings_reset()
9694 tp->napi[0].last_rx_cons = 0; in tg3_rings_reset()
9695 tp->napi[0].last_tx_cons = 0; in tg3_rings_reset()
9699 for (i = 1; i < tp->irq_max; i++) { in tg3_rings_reset()
9700 tp->napi[i].tx_prod = 0; in tg3_rings_reset()
9701 tp->napi[i].tx_cons = 0; in tg3_rings_reset()
9703 tw32_mailbox(tp->napi[i].prodmbox, 0); in tg3_rings_reset()
9704 tw32_rx_mbox(tp->napi[i].consmbox, 0); in tg3_rings_reset()
9705 tw32_mailbox_f(tp->napi[i].int_mbox, 1); in tg3_rings_reset()
9706 tp->napi[i].chk_msi_cnt = 0; in tg3_rings_reset()
9707 tp->napi[i].last_rx_cons = 0; in tg3_rings_reset()
9708 tp->napi[i].last_tx_cons = 0; in tg3_rings_reset()
9711 tw32_mailbox(tp->napi[0].prodmbox, 0); in tg3_rings_reset()
9713 tp->napi[0].tx_prod = 0; in tg3_rings_reset()
9714 tp->napi[0].tx_cons = 0; in tg3_rings_reset()
9715 tw32_mailbox(tp->napi[0].prodmbox, 0); in tg3_rings_reset()
9716 tw32_rx_mbox(tp->napi[0].consmbox, 0); in tg3_rings_reset()
9719 /* Make sure the NIC-based send BD rings are disabled. */ in tg3_rings_reset()
9727 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_rings_reset()
9731 ((u64) tnapi->status_mapping >> 32)); in tg3_rings_reset()
9733 ((u64) tnapi->status_mapping & 0xffffffff)); in tg3_rings_reset()
9737 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) { in tg3_rings_reset()
9738 u64 mapping = (u64)tnapi->status_mapping; in tg3_rings_reset()
9744 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_rings_reset()
9767 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post); in tg3_setup_rxbd_thresholds()
9768 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1); in tg3_setup_rxbd_thresholds()
9781 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1); in tg3_setup_rxbd_thresholds()
9828 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC | in __tg3_set_rx_mode()
9839 if (dev->flags & IFF_PROMISC) { in __tg3_set_rx_mode()
9842 } else if (dev->flags & IFF_ALLMULTI) { in __tg3_set_rx_mode()
9857 crc = calc_crc(ha->addr, ETH_ALEN); in __tg3_set_rx_mode()
9872 } else if (!(dev->flags & IFF_PROMISC)) { in __tg3_set_rx_mode()
9878 __tg3_set_one_mac_addr(tp, ha->addr, in __tg3_set_rx_mode()
9884 if (rx_mode != tp->rx_mode) { in __tg3_set_rx_mode()
9885 tp->rx_mode = rx_mode; in __tg3_set_rx_mode()
9896 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt); in tg3_rss_init_dflt_indir_tbl()
9906 if (tp->rxq_cnt == 1) { in tg3_rss_check_indir_tbl()
9907 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl)); in tg3_rss_check_indir_tbl()
9913 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt) in tg3_rss_check_indir_tbl()
9918 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt); in tg3_rss_check_indir_tbl()
9927 u32 val = tp->rss_ind_tbl[i]; in tg3_rss_write_indir_tbl()
9931 val |= tp->rss_ind_tbl[i]; in tg3_rss_write_indir_tbl()
9946 /* tp->lock is held. */
9951 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; in tg3_reset_hw()
9962 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_reset_hw()
9963 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) { in tg3_reset_hw()
9966 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_reset_hw()
9970 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) in tg3_reset_hw()
10079 * other revision. But do not set this on PCI Express in tg3_reset_hw()
10084 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; in tg3_reset_hw()
10085 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); in tg3_reset_hw()
10131 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); in tg3_reset_hw()
10137 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_reset_hw()
10140 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS | in tg3_reset_hw()
10144 tp->grc_mode |= GRC_MODE_HOST_SENDBDS; in tg3_reset_hw()
10146 /* Pseudo-header checksum is done by hardware logic and not in tg3_reset_hw()
10147 * the offload processers, so make the chip do the pseudo- in tg3_reset_hw()
10149 * convenient to do the pseudo-header checksum in software in tg3_reset_hw()
10152 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM; in tg3_reset_hw()
10155 if (tp->rxptpctl) in tg3_reset_hw()
10157 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK); in tg3_reset_hw()
10162 tw32(GRC_MODE, tp->grc_mode | val); in tg3_reset_hw()
10168 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && in tg3_reset_hw()
10169 tp->pdev->subsystem_device == TG3PCI_SUBDEVICE_ID_DELL_5762) { in tg3_reset_hw()
10194 fw_len = tp->fw_len; in tg3_reset_hw()
10195 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1); in tg3_reset_hw()
10199 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00); in tg3_reset_hw()
10202 if (tp->dev->mtu <= ETH_DATA_LEN) { in tg3_reset_hw()
10204 tp->bufmgr_config.mbuf_read_dma_low_water); in tg3_reset_hw()
10206 tp->bufmgr_config.mbuf_mac_rx_low_water); in tg3_reset_hw()
10208 tp->bufmgr_config.mbuf_high_water); in tg3_reset_hw()
10211 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo); in tg3_reset_hw()
10213 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo); in tg3_reset_hw()
10215 tp->bufmgr_config.mbuf_high_water_jumbo); in tg3_reset_hw()
10218 tp->bufmgr_config.dma_low_water); in tg3_reset_hw()
10220 tp->bufmgr_config.dma_high_water); in tg3_reset_hw()
10237 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__); in tg3_reset_hw()
10238 return -ENODEV; in tg3_reset_hw()
10264 ((u64) tpr->rx_std_mapping >> 32)); in tg3_reset_hw()
10266 ((u64) tpr->rx_std_mapping & 0xffffffff)); in tg3_reset_hw()
10284 ((u64) tpr->rx_jmb_mapping >> 32)); in tg3_reset_hw()
10286 ((u64) tpr->rx_jmb_mapping & 0xffffffff)); in tg3_reset_hw()
10312 tpr->rx_std_prod_idx = tp->rx_pending; in tg3_reset_hw()
10313 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx); in tg3_reset_hw()
10315 tpr->rx_jmb_prod_idx = in tg3_reset_hw()
10316 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0; in tg3_reset_hw()
10317 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx); in tg3_reset_hw()
10326 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); in tg3_reset_hw()
10380 tp->dma_limit = 0; in tg3_reset_hw()
10381 if (tp->dev->mtu <= ETH_DATA_LEN) { in tg3_reset_hw()
10383 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K; in tg3_reset_hw()
10469 __tg3_set_coalesce(tp, &tp->coal); in tg3_reset_hw()
10477 ((u64) tp->stats_mapping >> 32)); in tg3_reset_hw()
10479 ((u64) tp->stats_mapping & 0xffffffff)); in tg3_reset_hw()
10493 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode); in tg3_reset_hw()
10500 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { in tg3_reset_hw()
10501 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_reset_hw()
10507 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | in tg3_reset_hw()
10511 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; in tg3_reset_hw()
10513 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_reset_hw()
10515 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_reset_hw()
10516 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); in tg3_reset_hw()
10519 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants(). in tg3_reset_hw()
10539 tp->grc_local_ctrl &= ~gpio_mask; in tg3_reset_hw()
10540 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; in tg3_reset_hw()
10544 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | in tg3_reset_hw()
10547 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_reset_hw()
10553 if (tp->irq_cnt > 1) in tg3_reset_hw()
10596 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_reset_hw()
10605 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_reset_hw()
10672 tp->tx_mode = TX_MODE_ENABLE; in tg3_reset_hw()
10676 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX; in tg3_reset_hw()
10681 tp->tx_mode &= ~val; in tg3_reset_hw()
10682 tp->tx_mode |= tr32(MAC_TX_MODE) & val; in tg3_reset_hw()
10685 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_reset_hw()
10699 tp->rx_mode = RX_MODE_ENABLE; in tg3_reset_hw()
10701 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; in tg3_reset_hw()
10704 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX; in tg3_reset_hw()
10707 tp->rx_mode |= RX_MODE_RSS_ENABLE | in tg3_reset_hw()
10714 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_reset_hw()
10717 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_reset_hw()
10720 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_reset_hw()
10724 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_reset_hw()
10727 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_reset_hw()
10729 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) { in tg3_reset_hw()
10731 /* only if the signal pre-emphasis bit is not set */ in tg3_reset_hw()
10751 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_reset_hw()
10752 /* Use hardware link auto-negotiation */ in tg3_reset_hw()
10756 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_reset_hw()
10762 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT; in tg3_reset_hw()
10763 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT; in tg3_reset_hw()
10764 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_reset_hw()
10768 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_reset_hw()
10769 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; in tg3_reset_hw()
10775 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_reset_hw()
10776 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_reset_hw()
10788 __tg3_set_rx_mode(tp->dev); in tg3_reset_hw()
10801 limit -= 4; in tg3_reset_hw()
10861 * packet processing. Invoked with tp->lock held.
10888 if (ocir->signature != TG3_OCIR_SIG_MAGIC || in tg3_sd_scan_scratchpad()
10889 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE)) in tg3_sd_scan_scratchpad()
10902 spin_lock_bh(&tp->lock); in tg3_show_temp()
10903 tg3_ape_scratchpad_read(tp, &temperature, attr->index, in tg3_show_temp()
10905 spin_unlock_bh(&tp->lock); in tg3_show_temp()
10927 if (tp->hwmon_dev) { in tg3_hwmon_close()
10928 hwmon_device_unregister(tp->hwmon_dev); in tg3_hwmon_close()
10929 tp->hwmon_dev = NULL; in tg3_hwmon_close()
10937 struct pci_dev *pdev = tp->pdev; in tg3_hwmon_open()
10953 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3", in tg3_hwmon_open()
10955 if (IS_ERR(tp->hwmon_dev)) { in tg3_hwmon_open()
10956 tp->hwmon_dev = NULL; in tg3_hwmon_open()
10957 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n"); in tg3_hwmon_open()
10968 (PSTAT)->low += __val; \
10969 if ((PSTAT)->low < __val) \
10970 (PSTAT)->high += 1; \
10975 struct tg3_hw_stats *sp = tp->hw_stats; in tg3_periodic_fetch_stats()
10977 if (!tp->link_up) in tg3_periodic_fetch_stats()
10980 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS); in tg3_periodic_fetch_stats()
10981 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS); in tg3_periodic_fetch_stats()
10982 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT); in tg3_periodic_fetch_stats()
10983 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT); in tg3_periodic_fetch_stats()
10984 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS); in tg3_periodic_fetch_stats()
10985 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS); in tg3_periodic_fetch_stats()
10986 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS); in tg3_periodic_fetch_stats()
10987 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED); in tg3_periodic_fetch_stats()
10988 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL); in tg3_periodic_fetch_stats()
10989 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL); in tg3_periodic_fetch_stats()
10990 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST); in tg3_periodic_fetch_stats()
10991 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST); in tg3_periodic_fetch_stats()
10992 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST); in tg3_periodic_fetch_stats()
10994 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low + in tg3_periodic_fetch_stats()
10995 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) { in tg3_periodic_fetch_stats()
11004 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS); in tg3_periodic_fetch_stats()
11005 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS); in tg3_periodic_fetch_stats()
11006 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST); in tg3_periodic_fetch_stats()
11007 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST); in tg3_periodic_fetch_stats()
11008 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST); in tg3_periodic_fetch_stats()
11009 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS); in tg3_periodic_fetch_stats()
11010 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS); in tg3_periodic_fetch_stats()
11011 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD); in tg3_periodic_fetch_stats()
11012 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD); in tg3_periodic_fetch_stats()
11013 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD); in tg3_periodic_fetch_stats()
11014 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED); in tg3_periodic_fetch_stats()
11015 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG); in tg3_periodic_fetch_stats()
11016 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS); in tg3_periodic_fetch_stats()
11017 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE); in tg3_periodic_fetch_stats()
11019 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT); in tg3_periodic_fetch_stats()
11024 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT); in tg3_periodic_fetch_stats()
11030 sp->rx_discards.low += val; in tg3_periodic_fetch_stats()
11031 if (sp->rx_discards.low < val) in tg3_periodic_fetch_stats()
11032 sp->rx_discards.high += 1; in tg3_periodic_fetch_stats()
11034 sp->mbuf_lwm_thresh_hit = sp->rx_discards; in tg3_periodic_fetch_stats()
11036 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT); in tg3_periodic_fetch_stats()
11043 for (i = 0; i < tp->irq_cnt; i++) { in tg3_chk_missed_msi()
11044 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_chk_missed_msi()
11047 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr && in tg3_chk_missed_msi()
11048 tnapi->last_tx_cons == tnapi->tx_cons) { in tg3_chk_missed_msi()
11049 if (tnapi->chk_msi_cnt < 1) { in tg3_chk_missed_msi()
11050 tnapi->chk_msi_cnt++; in tg3_chk_missed_msi()
11056 tnapi->chk_msi_cnt = 0; in tg3_chk_missed_msi()
11057 tnapi->last_rx_cons = tnapi->rx_rcb_ptr; in tg3_chk_missed_msi()
11058 tnapi->last_tx_cons = tnapi->tx_cons; in tg3_chk_missed_msi()
11066 spin_lock(&tp->lock); in tg3_timer()
11068 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING)) { in tg3_timer()
11069 spin_unlock(&tp->lock); in tg3_timer()
11083 /* All of this garbage is because when using non-tagged in tg3_timer()
11087 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) { in tg3_timer()
11089 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); in tg3_timer()
11091 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_timer()
11096 spin_unlock(&tp->lock); in tg3_timer()
11103 if (!--tp->timer_counter) { in tg3_timer()
11107 if (tp->setlpicnt && !--tp->setlpicnt) in tg3_timer()
11117 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) { in tg3_timer()
11129 if (tp->link_up && in tg3_timer()
11133 if (!tp->link_up && in tg3_timer()
11139 if (!tp->serdes_counter) { in tg3_timer()
11141 (tp->mac_mode & in tg3_timer()
11144 tw32_f(MAC_MODE, tp->mac_mode); in tg3_timer()
11149 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_timer()
11157 if (link_up != tp->link_up) in tg3_timer()
11161 tp->timer_counter = tp->timer_multiplier; in tg3_timer()
11181 if (!--tp->asf_counter) { in tg3_timer()
11193 tp->asf_counter = tp->asf_multiplier; in tg3_timer()
11199 spin_unlock(&tp->lock); in tg3_timer()
11202 tp->timer.expires = jiffies + tp->timer_offset; in tg3_timer()
11203 add_timer(&tp->timer); in tg3_timer()
11211 tp->timer_offset = HZ; in tg3_timer_init()
11213 tp->timer_offset = HZ / 10; in tg3_timer_init()
11215 BUG_ON(tp->timer_offset > HZ); in tg3_timer_init()
11217 tp->timer_multiplier = (HZ / tp->timer_offset); in tg3_timer_init()
11218 tp->asf_multiplier = (HZ / tp->timer_offset) * in tg3_timer_init()
11221 timer_setup(&tp->timer, tg3_timer, 0); in tg3_timer_init()
11226 tp->asf_counter = tp->asf_multiplier; in tg3_timer_start()
11227 tp->timer_counter = tp->timer_multiplier; in tg3_timer_start()
11229 tp->timer.expires = jiffies + tp->timer_offset; in tg3_timer_start()
11230 add_timer(&tp->timer); in tg3_timer_start()
11235 del_timer_sync(&tp->timer); in tg3_timer_stop()
11238 /* Restart hardware after configuration changes, self-test, etc.
11239 * Invoked with tp->lock held.
11242 __releases(tp->lock) in tg3_restart_hw()
11243 __acquires(tp->lock) in tg3_restart_hw()
11249 netdev_err(tp->dev, in tg3_restart_hw()
11250 "Failed to re-initialize device, aborting\n"); in tg3_restart_hw()
11254 tp->irq_sync = 0; in tg3_restart_hw()
11256 dev_close(tp->dev); in tg3_restart_hw()
11270 if (tp->pcierr_recovery || !netif_running(tp->dev) || in tg3_reset_task()
11271 tp->pdev->error_state != pci_channel_io_normal) { in tg3_reset_task()
11287 tp->write32_tx_mbox = tg3_write32_tx_mbox; in tg3_reset_task()
11288 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_reset_task()
11297 tp->irq_sync = 0; in tg3_reset_task()
11303 dev_close(tp->dev); in tg3_reset_task()
11320 struct tg3_napi *tnapi = &tp->napi[irq_num]; in tg3_request_irq()
11322 if (tp->irq_cnt == 1) in tg3_request_irq()
11323 name = tp->dev->name; in tg3_request_irq()
11325 name = &tnapi->irq_lbl[0]; in tg3_request_irq()
11326 if (tnapi->tx_buffers && tnapi->rx_rcb) in tg3_request_irq()
11328 "%s-txrx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11329 else if (tnapi->tx_buffers) in tg3_request_irq()
11331 "%s-tx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11332 else if (tnapi->rx_rcb) in tg3_request_irq()
11334 "%s-rx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11337 "%s-%d", tp->dev->name, irq_num); in tg3_request_irq()
11338 name[IFNAMSIZ-1] = 0; in tg3_request_irq()
11353 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi); in tg3_request_irq()
11358 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_test_interrupt()
11359 struct net_device *dev = tp->dev; in tg3_test_interrupt()
11364 return -ENODEV; in tg3_test_interrupt()
11368 free_irq(tnapi->irq_vec, tnapi); in tg3_test_interrupt()
11379 err = request_irq(tnapi->irq_vec, tg3_test_isr, in tg3_test_interrupt()
11380 IRQF_SHARED, dev->name, tnapi); in tg3_test_interrupt()
11384 tnapi->hw_status->status &= ~SD_STATUS_UPDATED; in tg3_test_interrupt()
11387 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_test_interrupt()
11388 tnapi->coal_now); in tg3_test_interrupt()
11393 int_mbox = tr32_mailbox(tnapi->int_mbox); in tg3_test_interrupt()
11403 tnapi->hw_status->status_tag != tnapi->last_tag) in tg3_test_interrupt()
11404 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_test_interrupt()
11411 free_irq(tnapi->irq_vec, tnapi); in tg3_test_interrupt()
11427 return -EIO; in tg3_test_interrupt()
11444 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_test_msi()
11445 pci_write_config_word(tp->pdev, PCI_COMMAND, in tg3_test_msi()
11450 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_test_msi()
11456 if (err != -EIO) in tg3_test_msi()
11460 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching " in tg3_test_msi()
11464 free_irq(tp->napi[0].irq_vec, &tp->napi[0]); in tg3_test_msi()
11466 pci_disable_msi(tp->pdev); in tg3_test_msi()
11469 tp->napi[0].irq_vec = tp->pdev->irq; in tg3_test_msi()
11486 free_irq(tp->napi[0].irq_vec, &tp->napi[0]); in tg3_test_msi()
11495 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { in tg3_request_firmware()
11496 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n", in tg3_request_firmware()
11497 tp->fw_needed); in tg3_request_firmware()
11498 return -ENOENT; in tg3_request_firmware()
11501 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_request_firmware()
11508 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */ in tg3_request_firmware()
11509 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) { in tg3_request_firmware()
11510 netdev_err(tp->dev, "bogus length %d in \"%s\"\n", in tg3_request_firmware()
11511 tp->fw_len, tp->fw_needed); in tg3_request_firmware()
11512 release_firmware(tp->fw); in tg3_request_firmware()
11513 tp->fw = NULL; in tg3_request_firmware()
11514 return -EINVAL; in tg3_request_firmware()
11518 tp->fw_needed = NULL; in tg3_request_firmware()
11524 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt); in tg3_irq_count()
11528 * In multiqueue MSI-X mode, the first MSI-X vector in tg3_irq_count()
11532 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max); in tg3_irq_count()
11543 tp->txq_cnt = tp->txq_req; in tg3_enable_msix()
11544 tp->rxq_cnt = tp->rxq_req; in tg3_enable_msix()
11545 if (!tp->rxq_cnt) in tg3_enable_msix()
11546 tp->rxq_cnt = netif_get_num_default_rss_queues(); in tg3_enable_msix()
11547 if (tp->rxq_cnt > tp->rxq_max) in tg3_enable_msix()
11548 tp->rxq_cnt = tp->rxq_max; in tg3_enable_msix()
11550 /* Disable multiple TX rings by default. Simple round-robin hardware in tg3_enable_msix()
11554 if (!tp->txq_req) in tg3_enable_msix()
11555 tp->txq_cnt = 1; in tg3_enable_msix()
11557 tp->irq_cnt = tg3_irq_count(tp); in tg3_enable_msix()
11559 for (i = 0; i < tp->irq_max; i++) { in tg3_enable_msix()
11564 rc = pci_enable_msix_range(tp->pdev, msix_ent, 1, tp->irq_cnt); in tg3_enable_msix()
11567 } else if (rc < tp->irq_cnt) { in tg3_enable_msix()
11568 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n", in tg3_enable_msix()
11569 tp->irq_cnt, rc); in tg3_enable_msix()
11570 tp->irq_cnt = rc; in tg3_enable_msix()
11571 tp->rxq_cnt = max(rc - 1, 1); in tg3_enable_msix()
11572 if (tp->txq_cnt) in tg3_enable_msix()
11573 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max); in tg3_enable_msix()
11576 for (i = 0; i < tp->irq_max; i++) in tg3_enable_msix()
11577 tp->napi[i].irq_vec = msix_ent[i].vector; in tg3_enable_msix()
11579 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) { in tg3_enable_msix()
11580 pci_disable_msix(tp->pdev); in tg3_enable_msix()
11584 if (tp->irq_cnt == 1) in tg3_enable_msix()
11589 if (tp->txq_cnt > 1) in tg3_enable_msix()
11592 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt); in tg3_enable_msix()
11604 netdev_warn(tp->dev, in tg3_ints_init()
11611 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0) in tg3_ints_init()
11616 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) in tg3_ints_init()
11624 tp->irq_cnt = 1; in tg3_ints_init()
11625 tp->napi[0].irq_vec = tp->pdev->irq; in tg3_ints_init()
11628 if (tp->irq_cnt == 1) { in tg3_ints_init()
11629 tp->txq_cnt = 1; in tg3_ints_init()
11630 tp->rxq_cnt = 1; in tg3_ints_init()
11631 netif_set_real_num_tx_queues(tp->dev, 1); in tg3_ints_init()
11632 netif_set_real_num_rx_queues(tp->dev, 1); in tg3_ints_init()
11639 pci_disable_msix(tp->pdev); in tg3_ints_fini()
11641 pci_disable_msi(tp->pdev); in tg3_ints_fini()
11651 struct net_device *dev = tp->dev; in tg3_start()
11673 for (i = 0; i < tp->irq_cnt; i++) { in tg3_start()
11676 for (i--; i >= 0; i--) { in tg3_start()
11677 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_start()
11679 free_irq(tnapi->irq_vec, tnapi); in tg3_start()
11741 if (dev->features & NETIF_F_LOOPBACK) in tg3_start()
11742 tg3_set_loopback(dev, dev->features); in tg3_start()
11747 for (i = tp->irq_cnt - 1; i >= 0; i--) { in tg3_start()
11748 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_start()
11749 free_irq(tnapi->irq_vec, tnapi); in tg3_start()
11786 for (i = tp->irq_cnt - 1; i >= 0; i--) { in tg3_stop()
11787 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_stop()
11788 free_irq(tnapi->irq_vec, tnapi); in tg3_stop()
11803 if (tp->pcierr_recovery) { in tg3_open()
11806 return -EAGAIN; in tg3_open()
11809 if (tp->fw_needed) { in tg3_open()
11813 netdev_warn(tp->dev, "EEE capability disabled\n"); in tg3_open()
11814 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; in tg3_open()
11815 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_open()
11816 netdev_warn(tp->dev, "EEE capability restored\n"); in tg3_open()
11817 tp->phy_flags |= TG3_PHYFLG_EEE_CAP; in tg3_open()
11823 netdev_warn(tp->dev, "TSO capability disabled\n"); in tg3_open()
11826 netdev_notice(tp->dev, "TSO capability restored\n"); in tg3_open()
11845 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN), in tg3_open()
11849 pci_set_power_state(tp->pdev, PCI_D3hot); in tg3_open()
11859 if (tp->pcierr_recovery) { in tg3_close()
11862 return -EAGAIN; in tg3_close()
11867 if (pci_device_is_present(tp->pdev)) { in tg3_close()
11877 return ((u64)val->high << 32) | ((u64)val->low); in get_stat64()
11882 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_calc_crc_errors()
11884 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_calc_crc_errors()
11896 tp->phy_crc_errors += val; in tg3_calc_crc_errors()
11898 return tp->phy_crc_errors; in tg3_calc_crc_errors()
11901 return get_stat64(&hw_stats->rx_fcs_errors); in tg3_calc_crc_errors()
11905 estats->member = old_estats->member + \
11906 get_stat64(&hw_stats->member)
11910 struct tg3_ethtool_stats *old_estats = &tp->estats_prev; in tg3_get_estats()
11911 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_get_estats()
11994 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev; in tg3_get_nstats()
11995 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_get_nstats()
12000 stats->rx_packets = old_stats->rx_packets + in tg3_get_nstats()
12001 get_stat64(&hw_stats->rx_ucast_packets) + in tg3_get_nstats()
12002 get_stat64(&hw_stats->rx_mcast_packets) + in tg3_get_nstats()
12003 get_stat64(&hw_stats->rx_bcast_packets); in tg3_get_nstats()
12005 stats->tx_packets = old_stats->tx_packets + in tg3_get_nstats()
12006 get_stat64(&hw_stats->tx_ucast_packets) + in tg3_get_nstats()
12007 get_stat64(&hw_stats->tx_mcast_packets) + in tg3_get_nstats()
12008 get_stat64(&hw_stats->tx_bcast_packets); in tg3_get_nstats()
12010 stats->rx_bytes = old_stats->rx_bytes + in tg3_get_nstats()
12011 get_stat64(&hw_stats->rx_octets); in tg3_get_nstats()
12012 stats->tx_bytes = old_stats->tx_bytes + in tg3_get_nstats()
12013 get_stat64(&hw_stats->tx_octets); in tg3_get_nstats()
12015 stats->rx_errors = old_stats->rx_errors + in tg3_get_nstats()
12016 get_stat64(&hw_stats->rx_errors); in tg3_get_nstats()
12017 stats->tx_errors = old_stats->tx_errors + in tg3_get_nstats()
12018 get_stat64(&hw_stats->tx_errors) + in tg3_get_nstats()
12019 get_stat64(&hw_stats->tx_mac_errors) + in tg3_get_nstats()
12020 get_stat64(&hw_stats->tx_carrier_sense_errors) + in tg3_get_nstats()
12021 get_stat64(&hw_stats->tx_discards); in tg3_get_nstats()
12023 stats->multicast = old_stats->multicast + in tg3_get_nstats()
12024 get_stat64(&hw_stats->rx_mcast_packets); in tg3_get_nstats()
12025 stats->collisions = old_stats->collisions + in tg3_get_nstats()
12026 get_stat64(&hw_stats->tx_collisions); in tg3_get_nstats()
12028 stats->rx_length_errors = old_stats->rx_length_errors + in tg3_get_nstats()
12029 get_stat64(&hw_stats->rx_frame_too_long_errors) + in tg3_get_nstats()
12030 get_stat64(&hw_stats->rx_undersize_packets); in tg3_get_nstats()
12032 stats->rx_frame_errors = old_stats->rx_frame_errors + in tg3_get_nstats()
12033 get_stat64(&hw_stats->rx_align_errors); in tg3_get_nstats()
12034 stats->tx_aborted_errors = old_stats->tx_aborted_errors + in tg3_get_nstats()
12035 get_stat64(&hw_stats->tx_discards); in tg3_get_nstats()
12036 stats->tx_carrier_errors = old_stats->tx_carrier_errors + in tg3_get_nstats()
12037 get_stat64(&hw_stats->tx_carrier_sense_errors); in tg3_get_nstats()
12039 stats->rx_crc_errors = old_stats->rx_crc_errors + in tg3_get_nstats()
12042 stats->rx_missed_errors = old_stats->rx_missed_errors + in tg3_get_nstats()
12043 get_stat64(&hw_stats->rx_discards); in tg3_get_nstats()
12045 /* Aggregate per-queue counters. The per-queue counters are updated in tg3_get_nstats()
12046 * by a single writer, race-free. The result computed by this loop in tg3_get_nstats()
12053 rx_dropped = (unsigned long)(old_stats->rx_dropped); in tg3_get_nstats()
12054 tx_dropped = (unsigned long)(old_stats->tx_dropped); in tg3_get_nstats()
12056 for (i = 0; i < tp->irq_cnt; i++) { in tg3_get_nstats()
12057 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_get_nstats()
12059 rx_dropped += tnapi->rx_dropped; in tg3_get_nstats()
12060 tx_dropped += tnapi->tx_dropped; in tg3_get_nstats()
12063 stats->rx_dropped = rx_dropped; in tg3_get_nstats()
12064 stats->tx_dropped = tx_dropped; in tg3_get_nstats()
12077 regs->version = 0; in tg3_get_regs()
12081 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_get_regs()
12095 return tp->nvram_size; in tg3_get_eeprom_len()
12107 return -EINVAL; in tg3_get_eeprom()
12109 offset = eeprom->offset; in tg3_get_eeprom()
12110 len = eeprom->len; in tg3_get_eeprom()
12111 eeprom->len = 0; in tg3_get_eeprom()
12113 eeprom->magic = TG3_EEPROM_MAGIC; in tg3_get_eeprom()
12131 b_count = 4 - b_offset; in tg3_get_eeprom()
12136 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val); in tg3_get_eeprom()
12140 len -= b_count; in tg3_get_eeprom()
12142 eeprom->len += b_count; in tg3_get_eeprom()
12146 pd = &data[eeprom->len]; in tg3_get_eeprom()
12147 for (i = 0; i < (len - (len & 3)); i += 4) { in tg3_get_eeprom()
12151 i -= 4; in tg3_get_eeprom()
12152 eeprom->len += i; in tg3_get_eeprom()
12158 eeprom->len += i; in tg3_get_eeprom()
12159 ret = -EINTR; in tg3_get_eeprom()
12165 eeprom->len += i; in tg3_get_eeprom()
12169 pd = &data[eeprom->len]; in tg3_get_eeprom()
12171 b_offset = offset + len - b_count; in tg3_get_eeprom()
12176 eeprom->len += b_count; in tg3_get_eeprom()
12198 eeprom->magic != TG3_EEPROM_MAGIC) in tg3_set_eeprom()
12199 return -EINVAL; in tg3_set_eeprom()
12201 offset = eeprom->offset; in tg3_set_eeprom()
12202 len = eeprom->len; in tg3_set_eeprom()
12206 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start); in tg3_set_eeprom()
12220 ret = tg3_nvram_read_be32(tp, offset+len-4, &end); in tg3_set_eeprom()
12229 return -ENOMEM; in tg3_set_eeprom()
12233 memcpy(buf+len-4, &end, 4); in tg3_set_eeprom()
12234 memcpy(buf + b_offset, data, eeprom->len); in tg3_set_eeprom()
12253 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_get_link_ksettings()
12254 return -EAGAIN; in tg3_get_link_ksettings()
12255 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_get_link_ksettings()
12263 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_get_link_ksettings()
12267 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_get_link_ksettings()
12273 cmd->base.port = PORT_TP; in tg3_get_link_ksettings()
12276 cmd->base.port = PORT_FIBRE; in tg3_get_link_ksettings()
12278 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, in tg3_get_link_ksettings()
12281 advertising = tp->link_config.advertising; in tg3_get_link_ksettings()
12283 if (tp->link_config.flowctrl & FLOW_CTRL_RX) { in tg3_get_link_ksettings()
12284 if (tp->link_config.flowctrl & FLOW_CTRL_TX) { in tg3_get_link_ksettings()
12290 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) { in tg3_get_link_ksettings()
12294 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, in tg3_get_link_ksettings()
12297 if (netif_running(dev) && tp->link_up) { in tg3_get_link_ksettings()
12298 cmd->base.speed = tp->link_config.active_speed; in tg3_get_link_ksettings()
12299 cmd->base.duplex = tp->link_config.active_duplex; in tg3_get_link_ksettings()
12301 cmd->link_modes.lp_advertising, in tg3_get_link_ksettings()
12302 tp->link_config.rmt_adv); in tg3_get_link_ksettings()
12304 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_get_link_ksettings()
12305 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE) in tg3_get_link_ksettings()
12306 cmd->base.eth_tp_mdix = ETH_TP_MDI_X; in tg3_get_link_ksettings()
12308 cmd->base.eth_tp_mdix = ETH_TP_MDI; in tg3_get_link_ksettings()
12311 cmd->base.speed = SPEED_UNKNOWN; in tg3_get_link_ksettings()
12312 cmd->base.duplex = DUPLEX_UNKNOWN; in tg3_get_link_ksettings()
12313 cmd->base.eth_tp_mdix = ETH_TP_MDI_INVALID; in tg3_get_link_ksettings()
12315 cmd->base.phy_address = tp->phy_addr; in tg3_get_link_ksettings()
12316 cmd->base.autoneg = tp->link_config.autoneg; in tg3_get_link_ksettings()
12324 u32 speed = cmd->base.speed; in tg3_set_link_ksettings()
12329 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_set_link_ksettings()
12330 return -EAGAIN; in tg3_set_link_ksettings()
12331 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_set_link_ksettings()
12335 if (cmd->base.autoneg != AUTONEG_ENABLE && in tg3_set_link_ksettings()
12336 cmd->base.autoneg != AUTONEG_DISABLE) in tg3_set_link_ksettings()
12337 return -EINVAL; in tg3_set_link_ksettings()
12339 if (cmd->base.autoneg == AUTONEG_DISABLE && in tg3_set_link_ksettings()
12340 cmd->base.duplex != DUPLEX_FULL && in tg3_set_link_ksettings()
12341 cmd->base.duplex != DUPLEX_HALF) in tg3_set_link_ksettings()
12342 return -EINVAL; in tg3_set_link_ksettings()
12345 cmd->link_modes.advertising); in tg3_set_link_ksettings()
12347 if (cmd->base.autoneg == AUTONEG_ENABLE) { in tg3_set_link_ksettings()
12352 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_set_link_ksettings()
12356 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_set_link_ksettings()
12366 return -EINVAL; in tg3_set_link_ksettings()
12377 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) { in tg3_set_link_ksettings()
12379 return -EINVAL; in tg3_set_link_ksettings()
12381 if (cmd->base.duplex != DUPLEX_FULL) in tg3_set_link_ksettings()
12382 return -EINVAL; in tg3_set_link_ksettings()
12386 return -EINVAL; in tg3_set_link_ksettings()
12392 tp->link_config.autoneg = cmd->base.autoneg; in tg3_set_link_ksettings()
12393 if (cmd->base.autoneg == AUTONEG_ENABLE) { in tg3_set_link_ksettings()
12394 tp->link_config.advertising = (advertising | in tg3_set_link_ksettings()
12396 tp->link_config.speed = SPEED_UNKNOWN; in tg3_set_link_ksettings()
12397 tp->link_config.duplex = DUPLEX_UNKNOWN; in tg3_set_link_ksettings()
12399 tp->link_config.advertising = 0; in tg3_set_link_ksettings()
12400 tp->link_config.speed = speed; in tg3_set_link_ksettings()
12401 tp->link_config.duplex = cmd->base.duplex; in tg3_set_link_ksettings()
12404 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_link_ksettings()
12420 strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); in tg3_get_drvinfo()
12421 strscpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version)); in tg3_get_drvinfo()
12422 strscpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info)); in tg3_get_drvinfo()
12429 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev)) in tg3_get_wol()
12430 wol->supported = WAKE_MAGIC; in tg3_get_wol()
12432 wol->supported = 0; in tg3_get_wol()
12433 wol->wolopts = 0; in tg3_get_wol()
12434 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev)) in tg3_get_wol()
12435 wol->wolopts = WAKE_MAGIC; in tg3_get_wol()
12436 memset(&wol->sopass, 0, sizeof(wol->sopass)); in tg3_get_wol()
12442 struct device *dp = &tp->pdev->dev; in tg3_set_wol()
12444 if (wol->wolopts & ~WAKE_MAGIC) in tg3_set_wol()
12445 return -EINVAL; in tg3_set_wol()
12446 if ((wol->wolopts & WAKE_MAGIC) && in tg3_set_wol()
12448 return -EINVAL; in tg3_set_wol()
12450 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC); in tg3_set_wol()
12463 return tp->msg_enable; in tg3_get_msglevel()
12469 tp->msg_enable = value; in tg3_set_msglevel()
12478 return -EAGAIN; in tg3_nway_reset()
12480 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_nway_reset()
12481 return -EINVAL; in tg3_nway_reset()
12486 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_nway_reset()
12487 return -EAGAIN; in tg3_nway_reset()
12488 r = phy_start_aneg(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_nway_reset()
12492 spin_lock_bh(&tp->lock); in tg3_nway_reset()
12493 r = -EINVAL; in tg3_nway_reset()
12497 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) { in tg3_nway_reset()
12502 spin_unlock_bh(&tp->lock); in tg3_nway_reset()
12515 ering->rx_max_pending = tp->rx_std_ring_mask; in tg3_get_ringparam()
12517 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask; in tg3_get_ringparam()
12519 ering->rx_jumbo_max_pending = 0; in tg3_get_ringparam()
12521 ering->tx_max_pending = TG3_TX_RING_SIZE - 1; in tg3_get_ringparam()
12523 ering->rx_pending = tp->rx_pending; in tg3_get_ringparam()
12525 ering->rx_jumbo_pending = tp->rx_jumbo_pending; in tg3_get_ringparam()
12527 ering->rx_jumbo_pending = 0; in tg3_get_ringparam()
12529 ering->tx_pending = tp->napi[0].tx_pending; in tg3_get_ringparam()
12541 if ((ering->rx_pending > tp->rx_std_ring_mask) || in tg3_set_ringparam()
12542 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) || in tg3_set_ringparam()
12543 (ering->tx_pending > TG3_TX_RING_SIZE - 1) || in tg3_set_ringparam()
12544 (ering->tx_pending <= MAX_SKB_FRAGS) || in tg3_set_ringparam()
12546 (ering->tx_pending <= (MAX_SKB_FRAGS * 3)))) in tg3_set_ringparam()
12547 return -EINVAL; in tg3_set_ringparam()
12557 tp->rx_pending = ering->rx_pending; in tg3_set_ringparam()
12560 tp->rx_pending > 63) in tg3_set_ringparam()
12561 tp->rx_pending = 63; in tg3_set_ringparam()
12564 tp->rx_jumbo_pending = ering->rx_jumbo_pending; in tg3_set_ringparam()
12566 for (i = 0; i < tp->irq_max; i++) in tg3_set_ringparam()
12567 tp->napi[i].tx_pending = ering->tx_pending; in tg3_set_ringparam()
12594 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG); in tg3_get_pauseparam()
12596 if (tp->link_config.flowctrl & FLOW_CTRL_RX) in tg3_get_pauseparam()
12597 epause->rx_pause = 1; in tg3_get_pauseparam()
12599 epause->rx_pause = 0; in tg3_get_pauseparam()
12601 if (tp->link_config.flowctrl & FLOW_CTRL_TX) in tg3_get_pauseparam()
12602 epause->tx_pause = 1; in tg3_get_pauseparam()
12604 epause->tx_pause = 0; in tg3_get_pauseparam()
12613 if (tp->link_config.autoneg == AUTONEG_ENABLE) in tg3_set_pauseparam()
12619 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_set_pauseparam()
12622 return -EINVAL; in tg3_set_pauseparam()
12624 tp->link_config.flowctrl = 0; in tg3_set_pauseparam()
12625 phy_set_asym_pause(phydev, epause->rx_pause, epause->tx_pause); in tg3_set_pauseparam()
12626 if (epause->rx_pause) { in tg3_set_pauseparam()
12627 tp->link_config.flowctrl |= FLOW_CTRL_RX; in tg3_set_pauseparam()
12629 if (epause->tx_pause) { in tg3_set_pauseparam()
12630 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12632 } else if (epause->tx_pause) { in tg3_set_pauseparam()
12633 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12636 if (epause->autoneg) in tg3_set_pauseparam()
12641 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { in tg3_set_pauseparam()
12642 if (phydev->autoneg) { in tg3_set_pauseparam()
12653 if (!epause->autoneg) in tg3_set_pauseparam()
12666 if (epause->autoneg) in tg3_set_pauseparam()
12670 if (epause->rx_pause) in tg3_set_pauseparam()
12671 tp->link_config.flowctrl |= FLOW_CTRL_RX; in tg3_set_pauseparam()
12673 tp->link_config.flowctrl &= ~FLOW_CTRL_RX; in tg3_set_pauseparam()
12674 if (epause->tx_pause) in tg3_set_pauseparam()
12675 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12677 tp->link_config.flowctrl &= ~FLOW_CTRL_TX; in tg3_set_pauseparam()
12695 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_pauseparam()
12708 return -EOPNOTSUPP; in tg3_get_sset_count()
12718 return -EOPNOTSUPP; in tg3_get_rxnfc()
12720 switch (info->cmd) { in tg3_get_rxnfc()
12722 if (netif_running(tp->dev)) in tg3_get_rxnfc()
12723 info->data = tp->rxq_cnt; in tg3_get_rxnfc()
12725 info->data = num_online_cpus(); in tg3_get_rxnfc()
12726 if (info->data > TG3_RSS_MAX_NUM_QS) in tg3_get_rxnfc()
12727 info->data = TG3_RSS_MAX_NUM_QS; in tg3_get_rxnfc()
12733 return -EOPNOTSUPP; in tg3_get_rxnfc()
12753 rxfh->hfunc = ETH_RSS_HASH_TOP; in tg3_get_rxfh()
12754 if (!rxfh->indir) in tg3_get_rxfh()
12758 rxfh->indir[i] = tp->rss_ind_tbl[i]; in tg3_get_rxfh()
12772 if (rxfh->key || in tg3_set_rxfh()
12773 (rxfh->hfunc != ETH_RSS_HASH_NO_CHANGE && in tg3_set_rxfh()
12774 rxfh->hfunc != ETH_RSS_HASH_TOP)) in tg3_set_rxfh()
12775 return -EOPNOTSUPP; in tg3_set_rxfh()
12777 if (!rxfh->indir) in tg3_set_rxfh()
12781 tp->rss_ind_tbl[i] = rxfh->indir[i]; in tg3_set_rxfh()
12802 channel->max_rx = tp->rxq_max; in tg3_get_channels()
12803 channel->max_tx = tp->txq_max; in tg3_get_channels()
12806 channel->rx_count = tp->rxq_cnt; in tg3_get_channels()
12807 channel->tx_count = tp->txq_cnt; in tg3_get_channels()
12809 if (tp->rxq_req) in tg3_get_channels()
12810 channel->rx_count = tp->rxq_req; in tg3_get_channels()
12812 channel->rx_count = min(deflt_qs, tp->rxq_max); in tg3_get_channels()
12814 if (tp->txq_req) in tg3_get_channels()
12815 channel->tx_count = tp->txq_req; in tg3_get_channels()
12817 channel->tx_count = min(deflt_qs, tp->txq_max); in tg3_get_channels()
12827 return -EOPNOTSUPP; in tg3_set_channels()
12829 if (channel->rx_count > tp->rxq_max || in tg3_set_channels()
12830 channel->tx_count > tp->txq_max) in tg3_set_channels()
12831 return -EINVAL; in tg3_set_channels()
12833 tp->rxq_req = channel->rx_count; in tg3_set_channels()
12834 tp->txq_req = channel->tx_count; in tg3_set_channels()
12888 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_set_phys_id()
12900 if (tp->hw_stats) in tg3_get_ethtool_stats()
12946 /* The data is in little-endian format in NVRAM. in tg3_vpd_readblock()
12947 * Use the big-endian read routines to preserve in tg3_vpd_readblock()
12955 buf = pci_vpd_alloc(tp->pdev, vpdlen); in tg3_vpd_readblock()
12988 return -EIO; in tg3_test_nvram()
13015 return -EIO; in tg3_test_nvram()
13022 return -EIO; in tg3_test_nvram()
13026 return -ENOMEM; in tg3_test_nvram()
13028 err = -EIO; in tg3_test_nvram()
13060 err = -EIO; in tg3_test_nvram()
13094 err = -EIO; in tg3_test_nvram()
13107 err = -EIO; in tg3_test_nvram()
13123 return -ENOMEM; in tg3_test_nvram()
13141 if (!netif_running(tp->dev)) in tg3_test_link()
13142 return -ENODEV; in tg3_test_link()
13144 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_test_link()
13150 if (tp->link_up) in tg3_test_link()
13157 return -EIO; in tg3_test_link()
13338 /* Determine the read-only value. */ in tg3_test_registers()
13341 /* Write zero to the register, then make sure the read-only bits in tg3_test_registers()
13348 /* Test the read-only and read/write bits. */ in tg3_test_registers()
13353 * make sure the read-only bits are not changed and the in tg3_test_registers()
13360 /* Test the read-only bits. */ in tg3_test_registers()
13375 netdev_err(tp->dev, in tg3_test_registers()
13378 return -EIO; in tg3_test_registers()
13394 return -EIO; in tg3_do_mem_test()
13504 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; in tg3_run_loopback()
13506 tnapi = &tp->napi[0]; in tg3_run_loopback()
13507 rnapi = &tp->napi[0]; in tg3_run_loopback()
13508 if (tp->irq_cnt > 1) { in tg3_run_loopback()
13510 rnapi = &tp->napi[1]; in tg3_run_loopback()
13512 tnapi = &tp->napi[1]; in tg3_run_loopback()
13514 coal_now = tnapi->coal_now | rnapi->coal_now; in tg3_run_loopback()
13516 err = -EIO; in tg3_run_loopback()
13519 skb = netdev_alloc_skb(tp->dev, tx_len); in tg3_run_loopback()
13521 return -ENOMEM; in tg3_run_loopback()
13524 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN); in tg3_run_loopback()
13539 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header); in tg3_run_loopback()
13543 iph->tot_len = htons((u16)(mss + hdr_len)); in tg3_run_loopback()
13554 th->check = 0; in tg3_run_loopback()
13585 map = dma_map_single(&tp->pdev->dev, skb->data, tx_len, DMA_TO_DEVICE); in tg3_run_loopback()
13586 if (dma_mapping_error(&tp->pdev->dev, map)) { in tg3_run_loopback()
13588 return -EIO; in tg3_run_loopback()
13591 val = tnapi->tx_prod; in tg3_run_loopback()
13592 tnapi->tx_buffers[val].skb = skb; in tg3_run_loopback()
13593 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map); in tg3_run_loopback()
13595 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_run_loopback()
13596 rnapi->coal_now); in tg3_run_loopback()
13600 rx_start_idx = rnapi->hw_status->idx[0].rx_producer; in tg3_run_loopback()
13605 tnapi->tx_buffers[val].skb = NULL; in tg3_run_loopback()
13607 return -EIO; in tg3_run_loopback()
13610 tnapi->tx_prod++; in tg3_run_loopback()
13615 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod); in tg3_run_loopback()
13616 tr32_mailbox(tnapi->prodmbox); in tg3_run_loopback()
13622 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_run_loopback()
13627 tx_idx = tnapi->hw_status->idx[0].tx_consumer; in tg3_run_loopback()
13628 rx_idx = rnapi->hw_status->idx[0].rx_producer; in tg3_run_loopback()
13629 if ((tx_idx == tnapi->tx_prod) && in tg3_run_loopback()
13634 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1); in tg3_run_loopback()
13637 if (tx_idx != tnapi->tx_prod) in tg3_run_loopback()
13645 desc = &rnapi->rx_rcb[rx_start_idx++]; in tg3_run_loopback()
13646 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; in tg3_run_loopback()
13647 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; in tg3_run_loopback()
13649 if ((desc->err_vlan & RXD_ERR_MASK) != 0 && in tg3_run_loopback()
13650 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) in tg3_run_loopback()
13653 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) in tg3_run_loopback()
13654 - ETH_FCS_LEN; in tg3_run_loopback()
13660 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) { in tg3_run_loopback()
13667 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && in tg3_run_loopback()
13668 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK) in tg3_run_loopback()
13674 rx_data = tpr->rx_std_buffers[desc_idx].data; in tg3_run_loopback()
13675 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], in tg3_run_loopback()
13678 rx_data = tpr->rx_jmb_buffers[desc_idx].data; in tg3_run_loopback()
13679 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx], in tg3_run_loopback()
13684 dma_sync_single_for_cpu(&tp->pdev->dev, map, rx_len, in tg3_run_loopback()
13711 int err = -EIO; in tg3_test_loopback()
13715 if (tp->dma_limit) in tg3_test_loopback()
13716 jmb_pkt_sz = tp->dma_limit - ETH_HLEN; in tg3_test_loopback()
13718 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP; in tg3_test_loopback()
13719 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; in tg3_test_loopback()
13721 if (!netif_running(tp->dev)) { in tg3_test_loopback()
13747 /* HW errata - mac loopback fails in some cases on 5780. in tg3_test_loopback()
13766 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_test_loopback()
13810 /* Re-enable gphy autopowerdown. */ in tg3_test_loopback()
13811 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) in tg3_test_loopback()
13816 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0; in tg3_test_loopback()
13819 tp->phy_flags |= eee_cap; in tg3_test_loopback()
13828 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB; in tg3_self_test()
13830 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { in tg3_self_test()
13832 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13842 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13846 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13849 if (etest->flags & ETH_TEST_FL_OFFLINE) { in tg3_self_test()
13867 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_self_test()
13871 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13876 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13881 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; in tg3_self_test()
13884 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13889 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13908 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_self_test()
13919 return -EOPNOTSUPP; in tg3_hwtstamp_set()
13921 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf))) in tg3_hwtstamp_set()
13922 return -EFAULT; in tg3_hwtstamp_set()
13926 return -ERANGE; in tg3_hwtstamp_set()
13930 tp->rxptpctl = 0; in tg3_hwtstamp_set()
13933 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13937 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13941 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13945 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13949 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13953 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13957 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13961 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13965 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13969 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13973 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13977 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13981 return -ERANGE; in tg3_hwtstamp_set()
13984 if (netif_running(dev) && tp->rxptpctl) in tg3_hwtstamp_set()
13986 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK); in tg3_hwtstamp_set()
13993 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ? in tg3_hwtstamp_set()
13994 -EFAULT : 0; in tg3_hwtstamp_set()
14003 return -EOPNOTSUPP; in tg3_hwtstamp_get()
14009 switch (tp->rxptpctl) { in tg3_hwtstamp_get()
14051 return -ERANGE; in tg3_hwtstamp_get()
14054 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ? in tg3_hwtstamp_get()
14055 -EFAULT : 0; in tg3_hwtstamp_get()
14066 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_ioctl()
14067 return -EAGAIN; in tg3_ioctl()
14068 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_ioctl()
14074 data->phy_id = tp->phy_addr; in tg3_ioctl()
14080 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_ioctl()
14084 return -EAGAIN; in tg3_ioctl()
14086 spin_lock_bh(&tp->lock); in tg3_ioctl()
14087 err = __tg3_readphy(tp, data->phy_id & 0x1f, in tg3_ioctl()
14088 data->reg_num & 0x1f, &mii_regval); in tg3_ioctl()
14089 spin_unlock_bh(&tp->lock); in tg3_ioctl()
14091 data->val_out = mii_regval; in tg3_ioctl()
14097 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_ioctl()
14101 return -EAGAIN; in tg3_ioctl()
14103 spin_lock_bh(&tp->lock); in tg3_ioctl()
14104 err = __tg3_writephy(tp, data->phy_id & 0x1f, in tg3_ioctl()
14105 data->reg_num & 0x1f, data->val_in); in tg3_ioctl()
14106 spin_unlock_bh(&tp->lock); in tg3_ioctl()
14120 return -EOPNOTSUPP; in tg3_ioctl()
14130 memcpy(ec, &tp->coal, sizeof(*ec)); in tg3_get_coalesce()
14150 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) || in tg3_set_coalesce()
14151 (!ec->rx_coalesce_usecs) || in tg3_set_coalesce()
14152 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) || in tg3_set_coalesce()
14153 (!ec->tx_coalesce_usecs) || in tg3_set_coalesce()
14154 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) || in tg3_set_coalesce()
14155 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) || in tg3_set_coalesce()
14156 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) || in tg3_set_coalesce()
14157 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) || in tg3_set_coalesce()
14158 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) || in tg3_set_coalesce()
14159 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) || in tg3_set_coalesce()
14160 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) || in tg3_set_coalesce()
14161 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks)) in tg3_set_coalesce()
14162 return -EINVAL; in tg3_set_coalesce()
14165 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs; in tg3_set_coalesce()
14166 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs; in tg3_set_coalesce()
14167 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames; in tg3_set_coalesce()
14168 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames; in tg3_set_coalesce()
14169 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq; in tg3_set_coalesce()
14170 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq; in tg3_set_coalesce()
14171 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq; in tg3_set_coalesce()
14172 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq; in tg3_set_coalesce()
14173 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs; in tg3_set_coalesce()
14177 __tg3_set_coalesce(tp, &tp->coal); in tg3_set_coalesce()
14187 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_set_eee()
14188 netdev_warn(tp->dev, "Board does not support EEE!\n"); in tg3_set_eee()
14189 return -EOPNOTSUPP; in tg3_set_eee()
14192 if (edata->advertised != tp->eee.advertised) { in tg3_set_eee()
14193 netdev_warn(tp->dev, in tg3_set_eee()
14195 return -EINVAL; in tg3_set_eee()
14198 if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) { in tg3_set_eee()
14199 netdev_warn(tp->dev, in tg3_set_eee()
14202 return -EINVAL; in tg3_set_eee()
14205 tp->eee = *edata; in tg3_set_eee()
14207 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_eee()
14210 if (netif_running(tp->dev)) { in tg3_set_eee()
14224 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_get_eee()
14225 netdev_warn(tp->dev, in tg3_get_eee()
14227 return -EOPNOTSUPP; in tg3_get_eee()
14230 *edata = tp->eee; in tg3_get_eee()
14281 spin_lock_bh(&tp->lock); in tg3_get_stats64()
14282 if (!tp->hw_stats || !tg3_flag(tp, INIT_COMPLETE)) { in tg3_get_stats64()
14283 *stats = tp->net_stats_prev; in tg3_get_stats64()
14284 spin_unlock_bh(&tp->lock); in tg3_get_stats64()
14289 spin_unlock_bh(&tp->lock); in tg3_get_stats64()
14307 dev->mtu = new_mtu; in tg3_set_mtu()
14393 tp->nvram_size = EEPROM_CHIP_SIZE; in tg3_get_eeprom_size()
14410 while (cursize < tp->nvram_size) { in tg3_get_eeprom_size()
14420 tp->nvram_size = cursize; in tg3_get_eeprom_size()
14439 * 16-bit value at offset 0xf2. The tg3_nvram_read() in tg3_get_nvram_size()
14443 * want will always reside in the lower 16-bits. in tg3_get_nvram_size()
14446 * opposite the endianness of the CPU. The 16-bit in tg3_get_nvram_size()
14449 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; in tg3_get_nvram_size()
14453 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_nvram_size()
14472 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14473 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; in tg3_get_nvram_info()
14477 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14478 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE; in tg3_get_nvram_info()
14481 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14482 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_nvram_info()
14486 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_nvram_info()
14487 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE; in tg3_get_nvram_info()
14491 tp->nvram_jedecnum = JEDEC_SAIFUN; in tg3_get_nvram_info()
14492 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE; in tg3_get_nvram_info()
14496 tp->nvram_jedecnum = JEDEC_SST; in tg3_get_nvram_info()
14497 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE; in tg3_get_nvram_info()
14501 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14502 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; in tg3_get_nvram_info()
14511 tp->nvram_pagesize = 256; in tg3_nvram_get_pagesize()
14514 tp->nvram_pagesize = 512; in tg3_nvram_get_pagesize()
14517 tp->nvram_pagesize = 1024; in tg3_nvram_get_pagesize()
14520 tp->nvram_pagesize = 2048; in tg3_nvram_get_pagesize()
14523 tp->nvram_pagesize = 4096; in tg3_nvram_get_pagesize()
14526 tp->nvram_pagesize = 264; in tg3_nvram_get_pagesize()
14529 tp->nvram_pagesize = 528; in tg3_nvram_get_pagesize()
14547 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5752_nvram_info()
14551 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5752_nvram_info()
14558 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5752_nvram_info()
14568 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5752_nvram_info()
14593 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5755_nvram_info()
14596 tp->nvram_pagesize = 264; in tg3_get_5755_nvram_info()
14599 tp->nvram_size = (protect ? 0x3e200 : in tg3_get_5755_nvram_info()
14602 tp->nvram_size = (protect ? 0x1f200 : in tg3_get_5755_nvram_info()
14605 tp->nvram_size = (protect ? 0x1f200 : in tg3_get_5755_nvram_info()
14611 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5755_nvram_info()
14614 tp->nvram_pagesize = 256; in tg3_get_5755_nvram_info()
14616 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14620 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14624 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14642 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5787_nvram_info()
14644 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5787_nvram_info()
14653 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5787_nvram_info()
14656 tp->nvram_pagesize = 264; in tg3_get_5787_nvram_info()
14661 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5787_nvram_info()
14664 tp->nvram_pagesize = 256; in tg3_get_5787_nvram_info()
14691 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5761_nvram_info()
14695 tp->nvram_pagesize = 256; in tg3_get_5761_nvram_info()
14705 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5761_nvram_info()
14708 tp->nvram_pagesize = 256; in tg3_get_5761_nvram_info()
14713 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); in tg3_get_5761_nvram_info()
14720 tp->nvram_size = TG3_NVRAM_SIZE_2MB; in tg3_get_5761_nvram_info()
14726 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5761_nvram_info()
14732 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5761_nvram_info()
14738 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5761_nvram_info()
14746 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5906_nvram_info()
14748 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5906_nvram_info()
14760 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_57780_nvram_info()
14762 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_57780_nvram_info()
14774 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_57780_nvram_info()
14782 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_57780_nvram_info()
14786 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_57780_nvram_info()
14790 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_57780_nvram_info()
14797 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_57780_nvram_info()
14803 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_57780_nvram_info()
14806 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_57780_nvram_info()
14809 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_57780_nvram_info()
14819 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_57780_nvram_info()
14833 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5717_nvram_info()
14835 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5717_nvram_info()
14847 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5717_nvram_info()
14857 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5717_nvram_info()
14860 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5717_nvram_info()
14874 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5717_nvram_info()
14885 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5717_nvram_info()
14888 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5717_nvram_info()
14898 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_5717_nvram_info()
14921 tp->nvram_pagesize = 4096; in tg3_get_5720_nvram_info()
14922 tp->nvram_jedecnum = JEDEC_MACRONIX; in tg3_get_5720_nvram_info()
14927 tp->nvram_size = in tg3_get_5720_nvram_info()
14951 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5720_nvram_info()
14957 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5720_nvram_info()
14959 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE; in tg3_get_5720_nvram_info()
14973 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5720_nvram_info()
14981 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5720_nvram_info()
14986 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5720_nvram_info()
14990 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5720_nvram_info()
14994 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5720_nvram_info()
15016 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5720_nvram_info()
15025 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5720_nvram_info()
15031 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5720_nvram_info()
15037 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5720_nvram_info()
15041 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5720_nvram_info()
15051 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_5720_nvram_info()
15094 netdev_warn(tp->dev, in tg3_nvram_init()
15101 tp->nvram_size = 0; in tg3_nvram_init()
15127 if (tp->nvram_size == 0) in tg3_nvram_init()
15216 tp->pdev->subsystem_vendor) && in tg3_lookup_by_subsys()
15218 tp->pdev->subsystem_device)) in tg3_lookup_by_subsys()
15228 tp->phy_id = TG3_PHY_ID_INVALID; in tg3_get_eeprom_hw_cfg()
15229 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15246 device_set_wakeup_enable(&tp->pdev->dev, true); in tg3_get_eeprom_hw_cfg()
15259 tp->nic_sram_data_cfg = nic_cfg; in tg3_get_eeprom_hw_cfg()
15284 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK; in tg3_get_eeprom_hw_cfg() local
15287 eeprom_phy_id |= (id2 & 0xfc00) << 16; in tg3_get_eeprom_hw_cfg()
15288 eeprom_phy_id |= (id2 & 0x03ff) << 0; in tg3_get_eeprom_hw_cfg()
15292 tp->phy_id = eeprom_phy_id; in tg3_get_eeprom_hw_cfg()
15295 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_get_eeprom_hw_cfg()
15297 tp->phy_flags |= TG3_PHYFLG_MII_SERDES; in tg3_get_eeprom_hw_cfg()
15309 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15313 tp->led_ctrl = LED_CTRL_MODE_PHY_2; in tg3_get_eeprom_hw_cfg()
15317 tp->led_ctrl = LED_CTRL_MODE_MAC; in tg3_get_eeprom_hw_cfg()
15324 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15329 tp->led_ctrl = LED_CTRL_MODE_SHARED; in tg3_get_eeprom_hw_cfg()
15332 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | in tg3_get_eeprom_hw_cfg()
15337 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE | in tg3_get_eeprom_hw_cfg()
15343 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC; in tg3_get_eeprom_hw_cfg()
15347 tp->led_ctrl = LED_CTRL_MODE_COMBO; in tg3_get_eeprom_hw_cfg()
15349 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | in tg3_get_eeprom_hw_cfg()
15357 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) in tg3_get_eeprom_hw_cfg()
15358 tp->led_ctrl = LED_CTRL_MODE_PHY_2; in tg3_get_eeprom_hw_cfg()
15361 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15365 if ((tp->pdev->subsystem_vendor == in tg3_get_eeprom_hw_cfg()
15367 (tp->pdev->subsystem_device == 0x205a || in tg3_get_eeprom_hw_cfg()
15368 tp->pdev->subsystem_device == 0x2063)) in tg3_get_eeprom_hw_cfg()
15385 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES && in tg3_get_eeprom_hw_cfg()
15392 device_set_wakeup_enable(&tp->pdev->dev, true); in tg3_get_eeprom_hw_cfg()
15396 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING; in tg3_get_eeprom_hw_cfg()
15398 /* serdes signal pre-emphasis in register 0x590 set by */ in tg3_get_eeprom_hw_cfg()
15401 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS; in tg3_get_eeprom_hw_cfg()
15407 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD; in tg3_get_eeprom_hw_cfg()
15418 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN; in tg3_get_eeprom_hw_cfg()
15420 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK; in tg3_get_eeprom_hw_cfg()
15431 tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV; in tg3_get_eeprom_hw_cfg()
15435 device_set_wakeup_enable(&tp->pdev->dev, in tg3_get_eeprom_hw_cfg()
15438 device_set_wakeup_capable(&tp->pdev->dev, false); in tg3_get_eeprom_hw_cfg()
15471 return -EBUSY; in tg3_ape_otp_read()
15490 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY; in tg3_issue_otp_command()
15494 * configuration is a 32-bit value that straddles the alignment boundary.
15495 * We do two 32-bit reads and then shift and merge the results.
15527 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_init_link_config()
15528 if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV)) in tg3_phy_init_link_config()
15533 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_phy_init_link_config()
15542 tp->link_config.advertising = adv; in tg3_phy_init_link_config()
15543 tp->link_config.speed = SPEED_UNKNOWN; in tg3_phy_init_link_config()
15544 tp->link_config.duplex = DUPLEX_UNKNOWN; in tg3_phy_init_link_config()
15545 tp->link_config.autoneg = AUTONEG_ENABLE; in tg3_phy_init_link_config()
15546 tp->link_config.active_speed = SPEED_UNKNOWN; in tg3_phy_init_link_config()
15547 tp->link_config.active_duplex = DUPLEX_UNKNOWN; in tg3_phy_init_link_config()
15549 tp->old_link = -1; in tg3_phy_init_link_config()
15560 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; in tg3_phy_probe()
15563 switch (tp->pci_fn) { in tg3_phy_probe()
15565 tp->phy_ape_lock = TG3_APE_LOCK_PHY0; in tg3_phy_probe()
15568 tp->phy_ape_lock = TG3_APE_LOCK_PHY1; in tg3_phy_probe()
15571 tp->phy_ape_lock = TG3_APE_LOCK_PHY2; in tg3_phy_probe()
15574 tp->phy_ape_lock = TG3_APE_LOCK_PHY3; in tg3_phy_probe()
15580 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15581 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_phy_probe()
15582 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK | in tg3_phy_probe()
15597 * to either the hard-coded table based PHY_ID and failing in tg3_phy_probe()
15611 tp->phy_id = hw_phy_id; in tg3_phy_probe()
15613 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15615 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15617 if (tp->phy_id != TG3_PHY_ID_INVALID) { in tg3_phy_probe()
15629 tp->phy_id = p->phy_id; in tg3_phy_probe()
15638 return -ENODEV; in tg3_phy_probe()
15641 if (!tp->phy_id || in tg3_phy_probe()
15642 tp->phy_id == TG3_PHY_ID_BCM8002) in tg3_phy_probe()
15643 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15647 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15656 tp->phy_flags |= TG3_PHYFLG_EEE_CAP; in tg3_phy_probe()
15658 tp->eee.supported = SUPPORTED_100baseT_Full | in tg3_phy_probe()
15660 tp->eee.advertised = ADVERTISED_100baseT_Full | in tg3_phy_probe()
15662 tp->eee.eee_enabled = 1; in tg3_phy_probe()
15663 tp->eee.tx_lpi_enabled = 1; in tg3_phy_probe()
15664 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US; in tg3_phy_probe()
15669 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_phy_probe()
15670 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15687 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising, in tg3_phy_probe()
15688 tp->link_config.flowctrl); in tg3_phy_probe()
15696 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_probe()
15730 memset(tp->fw_ver, 0, sizeof(tp->fw_ver)); in tg3_read_vpd()
15731 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len, vpd_data + i); in tg3_read_vpd()
15742 memcpy(tp->board_part_number, &vpd_data[i], len); in tg3_read_vpd()
15746 if (tp->board_part_number[0]) in tg3_read_vpd()
15751 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_read_vpd()
15752 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C) in tg3_read_vpd()
15753 strcpy(tp->board_part_number, "BCM5717"); in tg3_read_vpd()
15754 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718) in tg3_read_vpd()
15755 strcpy(tp->board_part_number, "BCM5718"); in tg3_read_vpd()
15759 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) in tg3_read_vpd()
15760 strcpy(tp->board_part_number, "BCM57780"); in tg3_read_vpd()
15761 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) in tg3_read_vpd()
15762 strcpy(tp->board_part_number, "BCM57760"); in tg3_read_vpd()
15763 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790) in tg3_read_vpd()
15764 strcpy(tp->board_part_number, "BCM57790"); in tg3_read_vpd()
15765 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788) in tg3_read_vpd()
15766 strcpy(tp->board_part_number, "BCM57788"); in tg3_read_vpd()
15770 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761) in tg3_read_vpd()
15771 strcpy(tp->board_part_number, "BCM57761"); in tg3_read_vpd()
15772 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765) in tg3_read_vpd()
15773 strcpy(tp->board_part_number, "BCM57765"); in tg3_read_vpd()
15774 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781) in tg3_read_vpd()
15775 strcpy(tp->board_part_number, "BCM57781"); in tg3_read_vpd()
15776 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785) in tg3_read_vpd()
15777 strcpy(tp->board_part_number, "BCM57785"); in tg3_read_vpd()
15778 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791) in tg3_read_vpd()
15779 strcpy(tp->board_part_number, "BCM57791"); in tg3_read_vpd()
15780 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) in tg3_read_vpd()
15781 strcpy(tp->board_part_number, "BCM57795"); in tg3_read_vpd()
15785 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762) in tg3_read_vpd()
15786 strcpy(tp->board_part_number, "BCM57762"); in tg3_read_vpd()
15787 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766) in tg3_read_vpd()
15788 strcpy(tp->board_part_number, "BCM57766"); in tg3_read_vpd()
15789 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782) in tg3_read_vpd()
15790 strcpy(tp->board_part_number, "BCM57782"); in tg3_read_vpd()
15791 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) in tg3_read_vpd()
15792 strcpy(tp->board_part_number, "BCM57786"); in tg3_read_vpd()
15796 strcpy(tp->board_part_number, "BCM95906"); in tg3_read_vpd()
15799 strcpy(tp->board_part_number, "none"); in tg3_read_vpd()
15839 dst_off = strlen(tp->fw_ver); in tg3_read_bc_ver()
15842 if (TG3_VER_SIZE - dst_off < 16 || in tg3_read_bc_ver()
15846 offset = offset + ver_offset - start; in tg3_read_bc_ver()
15852 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v)); in tg3_read_bc_ver()
15863 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off, in tg3_read_bc_ver()
15881 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor); in tg3_read_hwsb_ver()
15888 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1); in tg3_read_sb_ver()
15928 offset = strlen(tp->fw_ver); in tg3_read_sb_ver()
15929 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset, in tg3_read_sb_ver()
15933 offset = strlen(tp->fw_ver); in tg3_read_sb_ver()
15934 if (offset < TG3_VER_SIZE - 1) in tg3_read_sb_ver()
15935 tp->fw_ver[offset] = 'a' + build - 1; in tg3_read_sb_ver()
15959 else if (tg3_nvram_read(tp, offset - 4, &start)) in tg3_read_mgmtfw_ver()
15967 offset += val - start; in tg3_read_mgmtfw_ver()
15969 vlen = strlen(tp->fw_ver); in tg3_read_mgmtfw_ver()
15971 tp->fw_ver[vlen++] = ','; in tg3_read_mgmtfw_ver()
15972 tp->fw_ver[vlen++] = ' '; in tg3_read_mgmtfw_ver()
15981 if (vlen > TG3_VER_SIZE - sizeof(v)) { in tg3_read_mgmtfw_ver()
15982 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen); in tg3_read_mgmtfw_ver()
15986 memcpy(&tp->fw_ver[vlen], &v, sizeof(v)); in tg3_read_mgmtfw_ver()
16017 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725) in tg3_read_dash_ver()
16022 vlen = strlen(tp->fw_ver); in tg3_read_dash_ver()
16024 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d", in tg3_read_dash_ver()
16052 vlen = strlen(tp->fw_ver); in tg3_read_otp_ver()
16053 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver); in tg3_read_otp_ver()
16062 if (tp->fw_ver[0] != 0) in tg3_read_fw_ver()
16066 strcat(tp->fw_ver, "sb"); in tg3_read_fw_ver()
16091 tp->fw_ver[TG3_VER_SIZE - 1] = 0; in tg3_read_fw_ver()
16114 unsigned int func, devnr = tp->pdev->devfn & ~7; in tg3_find_peer()
16117 peer = pci_get_slot(tp->pdev->bus, devnr | func); in tg3_find_peer()
16118 if (peer && peer != tp->pdev) in tg3_find_peer()
16122 /* 5704 can be configured in single-port mode, set peer to in tg3_find_peer()
16123 * tp->pdev in that case. in tg3_find_peer()
16126 peer = tp->pdev; in tg3_find_peer()
16141 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT; in tg3_detect_asic_rev()
16150 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_detect_asic_rev()
16151 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C || in tg3_detect_asic_rev()
16152 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || in tg3_detect_asic_rev()
16153 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || in tg3_detect_asic_rev()
16154 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 || in tg3_detect_asic_rev()
16155 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 || in tg3_detect_asic_rev()
16156 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 || in tg3_detect_asic_rev()
16157 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 || in tg3_detect_asic_rev()
16158 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 || in tg3_detect_asic_rev()
16159 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 || in tg3_detect_asic_rev()
16160 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) in tg3_detect_asic_rev()
16162 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 || in tg3_detect_asic_rev()
16163 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 || in tg3_detect_asic_rev()
16164 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 || in tg3_detect_asic_rev()
16165 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 || in tg3_detect_asic_rev()
16166 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || in tg3_detect_asic_rev()
16167 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 || in tg3_detect_asic_rev()
16168 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 || in tg3_detect_asic_rev()
16169 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 || in tg3_detect_asic_rev()
16170 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 || in tg3_detect_asic_rev()
16171 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) in tg3_detect_asic_rev()
16176 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id); in tg3_detect_asic_rev()
16183 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; in tg3_detect_asic_rev()
16186 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0; in tg3_detect_asic_rev()
16234 (tp->phy_flags & TG3_PHYFLG_IS_FET)) in tg3_10_100_only_device()
16237 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) { in tg3_10_100_only_device()
16239 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100) in tg3_10_100_only_device()
16264 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16266 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16268 /* Important! -- Make sure register accesses are byteswapped in tg3_get_invariants()
16273 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16275 tp->misc_host_ctrl |= (misc_ctrl_reg & in tg3_get_invariants()
16277 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16278 tp->misc_host_ctrl); in tg3_get_invariants()
16288 * will drive special cycles with non-zero data during the in tg3_get_invariants()
16291 * non-zero address during special cycles. However, only in tg3_get_invariants()
16292 * these ICH bridges are known to drive non-zero addresses in tg3_get_invariants()
16319 while (pci_id->vendor != 0) { in tg3_get_invariants()
16320 bridge = pci_get_device(pci_id->vendor, pci_id->device, in tg3_get_invariants()
16326 if (pci_id->rev != PCI_ANY_ID) { in tg3_get_invariants()
16327 if (bridge->revision > pci_id->rev) in tg3_get_invariants()
16330 if (bridge->subordinate && in tg3_get_invariants()
16331 (bridge->subordinate->number == in tg3_get_invariants()
16332 tp->pdev->bus->number)) { in tg3_get_invariants()
16352 while (pci_id->vendor != 0) { in tg3_get_invariants()
16353 bridge = pci_get_device(pci_id->vendor, in tg3_get_invariants()
16354 pci_id->device, in tg3_get_invariants()
16360 if (bridge->subordinate && in tg3_get_invariants()
16361 (bridge->subordinate->number <= in tg3_get_invariants()
16362 tp->pdev->bus->number) && in tg3_get_invariants()
16363 (bridge->subordinate->busn_res.end >= in tg3_get_invariants()
16364 tp->pdev->bus->number)) { in tg3_get_invariants()
16373 * DMA addresses > 40-bit. This bridge may have other additional in tg3_get_invariants()
16374 * 57xx devices behind it in some 4-port NIC designs for example. in tg3_get_invariants()
16375 * Any tg3 device found behind the bridge will also need the 40-bit in tg3_get_invariants()
16380 tp->msi_cap = tp->pdev->msi_cap; in tg3_get_invariants()
16388 if (bridge && bridge->subordinate && in tg3_get_invariants()
16389 (bridge->subordinate->number <= in tg3_get_invariants()
16390 tp->pdev->bus->number) && in tg3_get_invariants()
16391 (bridge->subordinate->busn_res.end >= in tg3_get_invariants()
16392 tp->pdev->bus->number)) { in tg3_get_invariants()
16402 tp->pdev_peer = tg3_find_peer(tp); in tg3_get_invariants()
16424 tp->fw_needed = FIRMWARE_TG3TSO5; in tg3_get_invariants()
16426 tp->fw_needed = FIRMWARE_TG3TSO; in tg3_get_invariants()
16442 tp->fw_needed = NULL; in tg3_get_invariants()
16446 tp->fw_needed = FIRMWARE_TG3; in tg3_get_invariants()
16449 tp->fw_needed = FIRMWARE_TG357766; in tg3_get_invariants()
16451 tp->irq_max = 1; in tg3_get_invariants()
16459 tp->pdev_peer == tp->pdev)) in tg3_get_invariants()
16469 tp->irq_max = TG3_IRQ_MAX_VECS; in tg3_get_invariants()
16473 tp->txq_max = 1; in tg3_get_invariants()
16474 tp->rxq_max = 1; in tg3_get_invariants()
16475 if (tp->irq_max > 1) { in tg3_get_invariants()
16476 tp->rxq_max = TG3_RSS_MAX_NUM_QS; in tg3_get_invariants()
16481 tp->txq_max = tp->irq_max - 1; in tg3_get_invariants()
16489 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K; in tg3_get_invariants()
16506 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16509 if (pci_is_pcie(tp->pdev)) { in tg3_get_invariants()
16514 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl); in tg3_get_invariants()
16536 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); in tg3_get_invariants()
16537 if (!tp->pcix_cap) { in tg3_get_invariants()
16538 dev_err(&tp->pdev->dev, in tg3_get_invariants()
16539 "Cannot find PCI-X capability, aborting\n"); in tg3_get_invariants()
16540 return -EIO; in tg3_get_invariants()
16557 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, in tg3_get_invariants()
16558 &tp->pci_cacheline_sz); in tg3_get_invariants()
16559 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_get_invariants()
16560 &tp->pci_lat_timer); in tg3_get_invariants()
16562 tp->pci_lat_timer < 64) { in tg3_get_invariants()
16563 tp->pci_lat_timer = 64; in tg3_get_invariants()
16564 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_get_invariants()
16565 tp->pci_lat_timer); in tg3_get_invariants()
16568 /* Important! -- It is critical that the PCI-X hw workaround in tg3_get_invariants()
16577 /* If we are in PCI-X mode, enable register write workaround. in tg3_get_invariants()
16591 pci_read_config_dword(tp->pdev, in tg3_get_invariants()
16592 tp->pdev->pm_cap + PCI_PM_CTRL, in tg3_get_invariants()
16596 pci_write_config_dword(tp->pdev, in tg3_get_invariants()
16597 tp->pdev->pm_cap + PCI_PM_CTRL, in tg3_get_invariants()
16601 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16603 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16612 /* Chip-specific fixup from Broadcom driver */ in tg3_get_invariants()
16616 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); in tg3_get_invariants()
16620 tp->read32 = tg3_read32; in tg3_get_invariants()
16621 tp->write32 = tg3_write32; in tg3_get_invariants()
16622 tp->read32_mbox = tg3_read32; in tg3_get_invariants()
16623 tp->write32_mbox = tg3_write32; in tg3_get_invariants()
16624 tp->write32_tx_mbox = tg3_write32; in tg3_get_invariants()
16625 tp->write32_rx_mbox = tg3_write32; in tg3_get_invariants()
16629 tp->write32 = tg3_write_indirect_reg32; in tg3_get_invariants()
16640 tp->write32 = tg3_write_flush_reg32; in tg3_get_invariants()
16644 tp->write32_tx_mbox = tg3_write32_tx_mbox; in tg3_get_invariants()
16646 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16650 tp->read32 = tg3_read_indirect_reg32; in tg3_get_invariants()
16651 tp->write32 = tg3_write_indirect_reg32; in tg3_get_invariants()
16652 tp->read32_mbox = tg3_read_indirect_mbox; in tg3_get_invariants()
16653 tp->write32_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16654 tp->write32_tx_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16655 tp->write32_rx_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16657 iounmap(tp->regs); in tg3_get_invariants()
16658 tp->regs = NULL; in tg3_get_invariants()
16660 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16662 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16665 tp->read32_mbox = tg3_read32_mbox_5906; in tg3_get_invariants()
16666 tp->write32_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16667 tp->write32_tx_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16668 tp->write32_rx_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16671 if (tp->write32 == tg3_write_indirect_reg32 || in tg3_get_invariants()
16685 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3; in tg3_get_invariants()
16689 pci_read_config_dword(tp->pdev, in tg3_get_invariants()
16690 tp->pcix_cap + PCI_X_STATUS, in tg3_get_invariants()
16692 tp->pci_fn = val & 0x7; in tg3_get_invariants()
16702 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0; in tg3_get_invariants()
16704 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >> in tg3_get_invariants()
16709 tp->write32_tx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16710 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16726 tp->fw_needed = NULL; in tg3_get_invariants()
16736 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16740 tp->ape_hb_interval = in tg3_get_invariants()
16744 /* Set up tp->grc_local_ctrl before calling in tg3_get_invariants()
16749 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; in tg3_get_invariants()
16752 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | in tg3_get_invariants()
16755 * are no pull-up resistors on unused GPIO pins. in tg3_get_invariants()
16758 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; in tg3_get_invariants()
16763 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; in tg3_get_invariants()
16765 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_get_invariants()
16766 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { in tg3_get_invariants()
16768 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; in tg3_get_invariants()
16771 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | in tg3_get_invariants()
16776 tp->grc_local_ctrl |= in tg3_get_invariants()
16785 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS)) in tg3_get_invariants()
16799 tp->phy_flags |= TG3_PHYFLG_IS_FET; in tg3_get_invariants()
16806 (tp->phy_flags & TG3_PHYFLG_IS_FET) || in tg3_get_invariants()
16807 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_get_invariants()
16808 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED; in tg3_get_invariants()
16812 tp->phy_flags |= TG3_PHYFLG_ADC_BUG; in tg3_get_invariants()
16814 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG; in tg3_get_invariants()
16817 !(tp->phy_flags & TG3_PHYFLG_IS_FET) && in tg3_get_invariants()
16825 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && in tg3_get_invariants()
16826 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722) in tg3_get_invariants()
16827 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG; in tg3_get_invariants()
16828 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) in tg3_get_invariants()
16829 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM; in tg3_get_invariants()
16831 tp->phy_flags |= TG3_PHYFLG_BER_BUG; in tg3_get_invariants()
16836 tp->phy_otp = tg3_read_otp_phycfg(tp); in tg3_get_invariants()
16837 if (tp->phy_otp == 0) in tg3_get_invariants()
16838 tp->phy_otp = TG3_OTP_DEFAULT; in tg3_get_invariants()
16842 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; in tg3_get_invariants()
16844 tp->mi_mode = MAC_MI_MODE_BASE; in tg3_get_invariants()
16846 tp->coalesce_mode = 0; in tg3_get_invariants()
16849 tp->coalesce_mode |= HOSTCC_MODE_32BYTE; in tg3_get_invariants()
16856 tp->coalesce_mode |= HOSTCC_MODE_ATTN; in tg3_get_invariants()
16857 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN; in tg3_get_invariants()
16880 tw32(GRC_MODE, val | tp->grc_mode); in tg3_get_invariants()
16890 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16904 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK; in tg3_get_invariants()
16920 tp->fw_needed = NULL; in tg3_get_invariants()
16934 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | in tg3_get_invariants()
16937 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS; in tg3_get_invariants()
16938 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16939 tp->misc_host_ctrl); in tg3_get_invariants()
16944 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; in tg3_get_invariants()
16946 tp->mac_mode = 0; in tg3_get_invariants()
16949 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY; in tg3_get_invariants()
16953 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err); in tg3_get_invariants()
16961 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_get_invariants()
16962 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16965 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16967 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16983 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && in tg3_get_invariants()
16985 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_get_invariants()
16986 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16991 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_get_invariants()
16999 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN; in tg3_get_invariants()
17000 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD; in tg3_get_invariants()
17003 tp->rx_offset = NET_SKB_PAD; in tg3_get_invariants()
17005 tp->rx_copy_thresh = ~(u16)0; in tg3_get_invariants()
17009 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1; in tg3_get_invariants()
17010 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1; in tg3_get_invariants()
17011 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1; in tg3_get_invariants()
17013 tp->rx_std_max_post = tp->rx_std_ring_mask + 1; in tg3_get_invariants()
17021 tp->rx_std_max_post = 8; in tg3_get_invariants()
17024 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & in tg3_get_invariants()
17036 if (!eth_platform_get_mac_address(&tp->pdev->dev, addr)) in tg3_get_device_address()
17040 err = ssb_gige_get_macaddr(tp->pdev, addr); in tg3_get_device_address()
17055 if (tp->pci_fn & 1) in tg3_get_device_address()
17057 if (tp->pci_fn > 1) in tg3_get_device_address()
17100 return -EINVAL; in tg3_get_device_address()
17113 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte); in tg3_calc_dma_bndry()
17146 * when a device tries to burst across a cache-line boundary. in tg3_calc_dma_bndry()
17149 * Unfortunately, for PCI-E there are only limited in tg3_calc_dma_bndry()
17150 * write-side controls for this, and thus for reads in tg3_calc_dma_bndry()
17280 * Broadcom noted the GRC reset will also reset all sub-components. in tg3_do_test_dma()
17299 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, in tg3_do_test_dma()
17301 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_do_test_dma()
17303 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_do_test_dma()
17310 ret = -ENODEV; in tg3_do_test_dma()
17342 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, in tg3_test_dma()
17345 ret = -ENOMEM; in tg3_test_dma()
17349 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | in tg3_test_dma()
17352 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); in tg3_test_dma()
17359 tp->dma_rwctrl |= 0x00180000; in tg3_test_dma()
17363 tp->dma_rwctrl |= 0x003f0000; in tg3_test_dma()
17365 tp->dma_rwctrl |= 0x003f000f; in tg3_test_dma()
17378 tp->dma_rwctrl |= 0x8000; in tg3_test_dma()
17380 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; in tg3_test_dma()
17385 tp->dma_rwctrl |= in tg3_test_dma()
17391 tp->dma_rwctrl |= 0x00144000; in tg3_test_dma()
17394 tp->dma_rwctrl |= 0x00148000; in tg3_test_dma()
17396 tp->dma_rwctrl |= 0x001b000f; in tg3_test_dma()
17400 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; in tg3_test_dma()
17404 tp->dma_rwctrl &= 0xfffffff0; in tg3_test_dma()
17409 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; in tg3_test_dma()
17419 * on those chips to enable a PCI-X workaround. in tg3_test_dma()
17421 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE; in tg3_test_dma()
17424 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17434 saved_dma_rwctrl = tp->dma_rwctrl; in tg3_test_dma()
17435 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17436 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17447 dev_err(&tp->pdev->dev, in tg3_test_dma()
17456 dev_err(&tp->pdev->dev, "%s: Buffer read failed. " in tg3_test_dma()
17466 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != in tg3_test_dma()
17468 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17469 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; in tg3_test_dma()
17470 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17473 dev_err(&tp->pdev->dev, in tg3_test_dma()
17476 ret = -ENODEV; in tg3_test_dma()
17487 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != in tg3_test_dma()
17494 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17495 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; in tg3_test_dma()
17498 tp->dma_rwctrl = saved_dma_rwctrl; in tg3_test_dma()
17501 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17505 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma); in tg3_test_dma()
17513 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17515 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17517 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17520 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17522 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17524 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17527 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17529 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17531 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17534 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17536 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17540 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17542 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17544 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17547 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17549 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17551 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17554 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17556 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17558 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17562 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER; in tg3_init_bufmgr_config()
17563 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER; in tg3_init_bufmgr_config()
17568 switch (tp->phy_id & TG3_PHY_ID_MASK) { in tg3_phy_string()
17628 strcat(str, ":32-bit"); in tg3_bus_string()
17630 strcat(str, ":64-bit"); in tg3_bus_string()
17636 struct ethtool_coalesce *ec = &tp->coal; in tg3_init_coal()
17639 ec->cmd = ETHTOOL_GCOALESCE; in tg3_init_coal()
17640 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS; in tg3_init_coal()
17641 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS; in tg3_init_coal()
17642 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES; in tg3_init_coal()
17643 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES; in tg3_init_coal()
17644 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT; in tg3_init_coal()
17645 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT; in tg3_init_coal()
17646 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT; in tg3_init_coal()
17647 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT; in tg3_init_coal()
17648 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS; in tg3_init_coal()
17650 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD | in tg3_init_coal()
17652 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS; in tg3_init_coal()
17653 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS; in tg3_init_coal()
17654 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS; in tg3_init_coal()
17655 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS; in tg3_init_coal()
17659 ec->rx_coalesce_usecs_irq = 0; in tg3_init_coal()
17660 ec->tx_coalesce_usecs_irq = 0; in tg3_init_coal()
17661 ec->stats_block_coalesce_usecs = 0; in tg3_init_coal()
17679 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); in tg3_init_one()
17685 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); in tg3_init_one()
17693 err = -ENOMEM; in tg3_init_one()
17697 SET_NETDEV_DEV(dev, &pdev->dev); in tg3_init_one()
17700 tp->pdev = pdev; in tg3_init_one()
17701 tp->dev = dev; in tg3_init_one()
17702 tp->rx_mode = TG3_DEF_RX_MODE; in tg3_init_one()
17703 tp->tx_mode = TG3_DEF_TX_MODE; in tg3_init_one()
17704 tp->irq_sync = 1; in tg3_init_one()
17705 tp->pcierr_recovery = false; in tg3_init_one()
17708 tp->msg_enable = tg3_debug; in tg3_init_one()
17710 tp->msg_enable = TG3_DEF_MSG_ENABLE; in tg3_init_one()
17730 tp->misc_host_ctrl = in tg3_init_one()
17736 /* The NONFRM (non-frame) byte/word swap controls take effect in tg3_init_one()
17740 * are running in big-endian mode. in tg3_init_one()
17742 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA | in tg3_init_one()
17745 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; in tg3_init_one()
17747 spin_lock_init(&tp->lock); in tg3_init_one()
17748 spin_lock_init(&tp->indirect_lock); in tg3_init_one()
17749 INIT_WORK(&tp->reset_task, tg3_reset_task); in tg3_init_one()
17751 tp->regs = pci_ioremap_bar(pdev, BAR_0); in tg3_init_one()
17752 if (!tp->regs) { in tg3_init_one()
17753 dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); in tg3_init_one()
17754 err = -ENOMEM; in tg3_init_one()
17758 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_init_one()
17759 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E || in tg3_init_one()
17760 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S || in tg3_init_one()
17761 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE || in tg3_init_one()
17762 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_init_one()
17763 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C || in tg3_init_one()
17764 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || in tg3_init_one()
17765 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || in tg3_init_one()
17766 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 || in tg3_init_one()
17767 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 || in tg3_init_one()
17768 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 || in tg3_init_one()
17769 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 || in tg3_init_one()
17770 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 || in tg3_init_one()
17771 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 || in tg3_init_one()
17772 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) { in tg3_init_one()
17774 tp->aperegs = pci_ioremap_bar(pdev, BAR_2); in tg3_init_one()
17775 if (!tp->aperegs) { in tg3_init_one()
17776 dev_err(&pdev->dev, in tg3_init_one()
17778 err = -ENOMEM; in tg3_init_one()
17783 tp->rx_pending = TG3_DEF_RX_RING_PENDING; in tg3_init_one()
17784 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; in tg3_init_one()
17786 dev->ethtool_ops = &tg3_ethtool_ops; in tg3_init_one()
17787 dev->watchdog_timeo = TG3_TX_TIMEOUT; in tg3_init_one()
17788 dev->netdev_ops = &tg3_netdev_ops; in tg3_init_one()
17789 dev->irq = pdev->irq; in tg3_init_one()
17793 dev_err(&pdev->dev, in tg3_init_one()
17799 * device behind the EPB cannot support DMA addresses > 40-bit. in tg3_init_one()
17800 * On 64-bit systems with IOMMU, use 40-bit dma_mask. in tg3_init_one()
17801 * On 64-bit systems without IOMMU, use 64-bit dma_mask and in tg3_init_one()
17816 err = dma_set_mask(&pdev->dev, dma_mask); in tg3_init_one()
17819 err = dma_set_coherent_mask(&pdev->dev, in tg3_init_one()
17822 dev_err(&pdev->dev, "Unable to obtain 64 bit " in tg3_init_one()
17829 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); in tg3_init_one()
17831 dev_err(&pdev->dev, in tg3_init_one()
17870 dev->features |= features | NETIF_F_HW_VLAN_CTAG_TX | in tg3_init_one()
17872 dev->vlan_features |= features; in tg3_init_one()
17876 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY in tg3_init_one()
17884 dev->hw_features |= features; in tg3_init_one()
17885 dev->priv_flags |= IFF_UNICAST_FLT; in tg3_init_one()
17887 /* MTU range: 60 - 9000 or 1500, depending on hardware */ in tg3_init_one()
17888 dev->min_mtu = TG3_MIN_MTU; in tg3_init_one()
17889 dev->max_mtu = TG3_MAX_MTU(tp); in tg3_init_one()
17895 tp->rx_pending = 63; in tg3_init_one()
17900 dev_err(&pdev->dev, in tg3_init_one()
17909 for (i = 0; i < tp->irq_max; i++) { in tg3_init_one()
17910 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_init_one()
17912 tnapi->tp = tp; in tg3_init_one()
17913 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING; in tg3_init_one()
17915 tnapi->int_mbox = intmbx; in tg3_init_one()
17918 tnapi->consmbox = rcvmbx; in tg3_init_one()
17919 tnapi->prodmbox = sndmbx; in tg3_init_one()
17922 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1); in tg3_init_one()
17924 tnapi->coal_now = HOSTCC_MODE_NOW; in tg3_init_one()
17942 sndmbx -= 0x4; in tg3_init_one()
17962 dev_err(&pdev->dev, "DMA engine test failed, aborting\n"); in tg3_init_one()
17981 dev_err(&pdev->dev, "Cannot register net device, aborting\n"); in tg3_init_one()
17987 tp->ptp_clock = ptp_clock_register(&tp->ptp_info, in tg3_init_one()
17988 &tp->pdev->dev); in tg3_init_one()
17989 if (IS_ERR(tp->ptp_clock)) in tg3_init_one()
17990 tp->ptp_clock = NULL; in tg3_init_one()
17994 tp->board_part_number, in tg3_init_one()
17997 dev->dev_addr); in tg3_init_one()
17999 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) { in tg3_init_one()
18002 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_init_one()
18003 ethtype = "10/100Base-TX"; in tg3_init_one()
18004 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_init_one()
18005 ethtype = "1000Base-SX"; in tg3_init_one()
18007 ethtype = "10/100/1000Base-T"; in tg3_init_one()
18012 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0, in tg3_init_one()
18013 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0); in tg3_init_one()
18017 (dev->features & NETIF_F_RXCSUM) != 0, in tg3_init_one()
18019 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0, in tg3_init_one()
18022 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n", in tg3_init_one()
18023 tp->dma_rwctrl, in tg3_init_one()
18024 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 : in tg3_init_one()
18025 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64); in tg3_init_one()
18032 if (tp->aperegs) { in tg3_init_one()
18033 iounmap(tp->aperegs); in tg3_init_one()
18034 tp->aperegs = NULL; in tg3_init_one()
18038 if (tp->regs) { in tg3_init_one()
18039 iounmap(tp->regs); in tg3_init_one()
18040 tp->regs = NULL; in tg3_init_one()
18064 release_firmware(tp->fw); in tg3_remove_one()
18074 if (tp->aperegs) { in tg3_remove_one()
18075 iounmap(tp->aperegs); in tg3_remove_one()
18076 tp->aperegs = NULL; in tg3_remove_one()
18078 if (tp->regs) { in tg3_remove_one()
18079 iounmap(tp->regs); in tg3_remove_one()
18080 tp->regs = NULL; in tg3_remove_one()
18164 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)); in tg3_resume()
18209 * tg3_io_error_detected - called when PCI error is detected
18231 if (!netdev || tp->pcierr_recovery || !netif_running(netdev)) in tg3_io_error_detected()
18236 tp->pcierr_recovery = true; in tg3_io_error_detected()
18268 * tg3_io_slot_reset - called after the pci bus has been reset.
18271 * Restart the card from scratch, as if from a cold-boot.
18286 dev_err(&pdev->dev, in tg3_io_slot_reset()
18287 "Cannot re-enable PCI device after reset.\n"); in tg3_io_slot_reset()
18317 * tg3_io_resume - called when traffic can start flowing again.
18355 tp->pcierr_recovery = false; in tg3_io_resume()