broadcom/bnxt/bnxt.h

1 /* Broadcom NetXtreme-C/E network driver.
3  * Copyright (c) 2014-2016 Broadcom Corporation
4  * Copyright (c) 2016-2018 Broadcom Limited
32 #include <linux/io-64-nonatomic-lo-hi.h>
71 	(((txr)->tx_napi_idx << TX_OPAQUE_RING_SHIFT) |			\
72 	 ((bds) << TX_OPAQUE_BDS_SHIFT) | ((idx) & (bp)->tx_ring_mask))
80 				 (bp)->tx_ring_mask)
182 	(le32_to_cpu((txcmp)->sq_cons_idx) & TX_CMP_SQ_CONS_IDX_MASK)
236 	((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
241 	(((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
245 	((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_V3_RSS_EXT_OP_LEGACY) >>\
249 	((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_V3_RSS_EXT_OP_NEW) >>\
253 	(((bp)->rss_cap & BNXT_RSS_CAP_RSS_TCAM) ?		\
263 	((rxcmp)->rx_cmp_misc_v1 & cpu_to_le32(RX_CMP_METADATA1_VALID))
266 	(le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_METADATA1_TPID_SEL)
332 	    (((rxcmp1)->rx_cmp_flags2 &	RX_CMP_L4_CS_BITS) &&		\
333 	     !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
336 	    ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) &			\
340 	((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) &		\
344 	((le32_to_cpu((rxcmp1)->rx_cmp_cfa_code_errors_v2) &		\
361 	((le32_to_cpu((rx_agg)->rx_agg_cmp_v) &		\
406 	((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type &		\
410 	(((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &	\
415 	(((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &	\
420 	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &	\
424 	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &	\
428 	((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type &		\
432 	((rx_tpa_start)->rx_tpa_start_cmp_misc_v1 &			\
436 	(le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &	\
471 	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) &	\
475 	(!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 &		\
479 	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) &	\
484 	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) &	\
525 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
529 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
533 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
537 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
541 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
549 	((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type &			\
553 	(!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta &			\
582 	((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 &			\
586 	((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) &	\
591 	((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) &	\
652 	(((cpr)->cp_ring_type << BNXT_NQ_HDL_TYPE_SHIFT) | (cpr)->cp_idx)
671 /* 64-bit doorbell */
699 #define INVALID_HW_RING_ID	((u16)-1)
716 /* The RXBD length is 16-bit so we can only support page sizes < 64K */
727 /* First RX buffer page in XDP multi-buf mode
729  * +-------------------------------------------------------------------------+
730  * | XDP_PACKET_HEADROOM | bp->rx_buf_use_size              | skb_shared_info|
731  * | (bp->rx_dma_offset) |                                  |                |
732  * +-------------------------------------------------------------------------+
735 	((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN -	\
738 	(BNXT_MAX_PAGE_MODE_MTU_SBUF - \
748 #define MAX_TPA_P5_MASK	(MAX_TPA_P5 - 1)
779 #define BNXT_MAX_RX_DESC_CNT		(RX_DESC_CNT * MAX_RX_PAGES - 1)
780 #define BNXT_MAX_RX_DESC_CNT_JUM_ENA	(RX_DESC_CNT * MAX_RX_PAGES_AGG_ENA - 1)
781 #define BNXT_MAX_RX_JUM_DESC_CNT	(RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
782 #define BNXT_MAX_TX_DESC_CNT		(TX_DESC_CNT * MAX_TX_PAGES - 1)
789 #define RX_RING(bp, x)	(((x) & (bp)->rx_ring_mask) >> (BNXT_PAGE_SHIFT - 4))
790 #define RX_AGG_RING(bp, x)	(((x) & (bp)->rx_agg_ring_mask) >>	\
791 				 (BNXT_PAGE_SHIFT - 4))
792 #define RX_IDX(x)	((x) & (RX_DESC_CNT - 1))
794 #define TX_RING(bp, x)	(((x) & (bp)->tx_ring_mask) >> (BNXT_PAGE_SHIFT - 4))
795 #define TX_IDX(x)	((x) & (TX_DESC_CNT - 1))
797 #define CP_RING(x)	(((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
798 #define CP_IDX(x)	((x) & (CP_DESC_CNT - 1))
801 	(!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) ==	\
802 	 !((raw_cons) & bp->cp_bit))
805 	(!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
806 	 !((raw_cons) & bp->cp_bit))
809 	(!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) ==	\
810 	 !((raw_cons) & bp->cp_bit))
813 	(!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit))
816 	(le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
819 	(le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
821 #define RING_RX(bp, idx)	((idx) & (bp)->rx_ring_mask)
824 #define RING_RX_AGG(bp, idx)	((idx) & (bp)->rx_agg_ring_mask)
827 #define RING_TX(bp, idx)	((idx) & (bp)->tx_ring_mask)
832 #define RING_CMP(idx)		((idx) & bp->cp_ring_mask)
926 #define DB_EPOCH(db, idx)	(((idx) & (db)->db_epoch_mask) <<	\
927 				 ((db)->db_epoch_shift))
931 #define DB_RING_IDX(db, idx)	(((idx) & (db)->db_ring_mask) |		\
1167 	for (iter = 0, txr = (bnapi)->tx_ring[0]; txr;	\
1168 	     txr = (iter < BNXT_MAX_TXR_PER_NAPI - 1) ?	\
1169 	     (bnapi)->tx_ring[++iter] : NULL)
1206 #define INVALID_STATS_CTX_ID	-1
1420 #define BNXT_LINK_IS_UP(bp)	((bp)->link_info.link_state == BNXT_LINK_STATE_UP)
1522 	u32			preemphasis;  member
1587 	((link_info)->support_pam4_speeds)
1641 	((bp->flags & BNXT_FLAG_CHIP_P5_PLUS) ? 0x80000000 : 0xb1000000)
1709 	/* Stat counter mask (width) */
1824 #define BNXT_CTX_INV	((u16)-1)
2116 #define BNXT_PF(bp)		(!((bp)->flags & BNXT_FLAG_VF))
2117 #define BNXT_VF(bp)		((bp)->flags & BNXT_FLAG_VF)
2118 #define BNXT_NPAR(bp)		((bp)->port_partition_type)
2119 #define BNXT_MH(bp)		((bp)->flags & BNXT_FLAG_MULTI_HOST)
2122 				 ((bp)->phy_flags & BNXT_PHY_FL_SHARED_PORT_CFG))
2125 				 (bp)->link_info.phy_state == BNXT_PHY_STATE_ENABLED)
2126 #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
2127 #define BNXT_RX_PAGE_MODE(bp)	((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
2129 				 (!((bp)->flags & BNXT_FLAG_CHIP_P5_PLUS) ||\
2130 				  (bp)->max_tpa_v2) && !is_kdump_kernel())
2131 #define BNXT_RX_JUMBO_MODE(bp)	((bp)->flags & BNXT_FLAG_JUMBO)
2134 	((bp)->chip_num == CHIP_NUM_57608)
2137 	((bp)->chip_num == CHIP_NUM_57508 ||	\
2138 	 (bp)->chip_num == CHIP_NUM_57504 ||	\
2139 	 (bp)->chip_num == CHIP_NUM_57502)
2147 	(BNXT_CHIP_NUM_57X1X((bp)->chip_num) ||	\
2148 	 BNXT_CHIP_NUM_5745X((bp)->chip_num) ||	\
2149 	 BNXT_CHIP_NUM_588XX((bp)->chip_num) ||	\
2150 	 (BNXT_CHIP_NUM_58700((bp)->chip_num) &&	\
2254 	(test_bit(BNXT_STATE_FW_FATAL_COND, &(bp)->state) ||	\
2255 	 pci_channel_offline((bp)->pdev))
2307 #define BNXT_NEW_RM(bp)		((bp)->fw_cap & BNXT_FW_CAP_NEW_RM)
2309 				 ((bp)->fw_cap & BNXT_FW_CAP_PTP_RTC))
2336 #define PHY_VER_STR_LEN         (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
2343 #define BNXT_FW_MAJ(bp)		((bp)->fw_ver_code >> 48)
2344 #define BNXT_FW_BLD(bp)		(((bp)->fw_ver_code >> 16) & 0xffff)
2416 	/* ensure atomic 64-bit doorbell writes on 32-bit systems. */
2425 #define BNXT_NTP_FLTR_HASH_MASK	(BNXT_NTP_FLTR_HASH_SIZE - 1)
2434 #define BNXT_L2_FLTR_HASH_MASK	(BNXT_L2_FLTR_HASH_SIZE - 1)
2481 	/* devlink interface and vf-rep structs */
2485 	struct bnxt_vf_rep	**vf_reps; /* array of vf-rep ptrs */
2486 	u16			*cfa_code_map; /* cfa_code -> vf_idx map */
2564 	u32 used = READ_ONCE(txr->tx_prod) - READ_ONCE(txr->tx_cons);  in bnxt_tx_avail()
2566 	return bp->tx_ring_size - (used & bp->tx_ring_mask);  in bnxt_tx_avail()
2573 	spin_lock(&bp->db_lock);  in bnxt_writeq()
2575 	spin_unlock(&bp->db_lock);  in bnxt_writeq()
2585 	spin_lock(&bp->db_lock);  in bnxt_writeq_relaxed()
2587 	spin_unlock(&bp->db_lock);  in bnxt_writeq_relaxed()
2597 	if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {  in bnxt_db_write_relaxed()
2598 		bnxt_writeq_relaxed(bp, db->db_key64 | DB_RING_IDX(db, idx),  in bnxt_db_write_relaxed()
2599 				    db->doorbell);  in bnxt_db_write_relaxed()
2601 		u32 db_val = db->db_key32 | DB_RING_IDX(db, idx);  in bnxt_db_write_relaxed()
2603 		writel_relaxed(db_val, db->doorbell);  in bnxt_db_write_relaxed()
2604 		if (bp->flags & BNXT_FLAG_DOUBLE_DB)  in bnxt_db_write_relaxed()
2605 			writel_relaxed(db_val, db->doorbell);  in bnxt_db_write_relaxed()
2613 	if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {  in bnxt_db_write()
2614 		bnxt_writeq(bp, db->db_key64 | DB_RING_IDX(db, idx),  in bnxt_db_write()
2615 			    db->doorbell);  in bnxt_db_write()
2617 		u32 db_val = db->db_key32 | DB_RING_IDX(db, idx);  in bnxt_db_write()
2619 		writel(db_val, db->doorbell);  in bnxt_db_write()
2620 		if (bp->flags & BNXT_FLAG_DOUBLE_DB)  in bnxt_db_write()
2621 			writel(db_val, db->doorbell);  in bnxt_db_write()
2629 	return BNXT_PF(bp) && (bp->pf.active_vfs || bp->sriov_cfg);  in bnxt_sriov_cfg()