Lines Matching +full:adv +full:- +full:extra +full:- +full:delay
3 * Copyright (c) 2004-2014 Broadcom Corporation
4 * Copyright (c) 2014-2015 QLogic Corporation
30 #include <linux/dma-mapping.h>
34 #include <linux/delay.h>
61 #define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-6.2.3.fw"
62 #define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-6.0.15.fw"
63 #define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-6.2.1b.fw"
64 #define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-6.0.17.fw"
65 #define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-6.0.17.fw"
104 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
107 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
109 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
110 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
111 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
112 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
113 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
114 { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
151 "EEPROM - slow"},
157 /* Saifun SA25F010 (non-buffered flash) */
162 "Non-buffered flash (128kB)"},
163 /* Saifun SA25F020 (non-buffered flash) */
168 "Non-buffered flash (256kB)"},
174 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
178 "Entry 0101: ST M45PE10 (128kB non-buffered)"},
179 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
183 "Entry 0110: ST M45PE20 (256kB non-buffered)"},
184 /* Saifun SA25F005 (non-buffered flash) */
189 "Non-buffered flash (64kB)"},
194 "EEPROM - fast"},
253 diff = READ_ONCE(txr->tx_prod) - READ_ONCE(txr->tx_cons); in bnx2_tx_avail()
259 return bp->tx_ring_size - diff; in bnx2_tx_avail()
268 spin_lock_irqsave(&bp->indirect_lock, flags); in bnx2_reg_rd_ind()
271 spin_unlock_irqrestore(&bp->indirect_lock, flags); in bnx2_reg_rd_ind()
280 spin_lock_irqsave(&bp->indirect_lock, flags); in bnx2_reg_wr_ind()
283 spin_unlock_irqrestore(&bp->indirect_lock, flags); in bnx2_reg_wr_ind()
289 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val); in bnx2_shmem_wr()
295 return bnx2_reg_rd_ind(bp, bp->shmem_base + offset); in bnx2_shmem_rd()
304 spin_lock_irqsave(&bp->indirect_lock, flags); in bnx2_ctx_wr()
321 spin_unlock_irqrestore(&bp->indirect_lock, flags); in bnx2_ctx_wr()
329 struct drv_ctl_io *io = &info->data.io; in bnx2_drv_ctl()
331 switch (info->cmd) { in bnx2_drv_ctl()
333 bnx2_reg_wr_ind(bp, io->offset, io->data); in bnx2_drv_ctl()
336 io->data = bnx2_reg_rd_ind(bp, io->offset); in bnx2_drv_ctl()
339 bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data); in bnx2_drv_ctl()
342 return -EINVAL; in bnx2_drv_ctl()
349 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; in bnx2_setup_cnic_irq_info()
350 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; in bnx2_setup_cnic_irq_info()
353 if (bp->flags & BNX2_FLAG_USING_MSIX) { in bnx2_setup_cnic_irq_info()
354 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; in bnx2_setup_cnic_irq_info()
355 bnapi->cnic_present = 0; in bnx2_setup_cnic_irq_info()
356 sb_id = bp->irq_nvecs; in bnx2_setup_cnic_irq_info()
357 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; in bnx2_setup_cnic_irq_info()
359 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; in bnx2_setup_cnic_irq_info()
360 bnapi->cnic_tag = bnapi->last_status_idx; in bnx2_setup_cnic_irq_info()
361 bnapi->cnic_present = 1; in bnx2_setup_cnic_irq_info()
363 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; in bnx2_setup_cnic_irq_info()
366 cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector; in bnx2_setup_cnic_irq_info()
367 cp->irq_arr[0].status_blk = (void *) in bnx2_setup_cnic_irq_info()
368 ((unsigned long) bnapi->status_blk.msi + in bnx2_setup_cnic_irq_info()
370 cp->irq_arr[0].status_blk_num = sb_id; in bnx2_setup_cnic_irq_info()
371 cp->num_irq = 1; in bnx2_setup_cnic_irq_info()
378 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; in bnx2_register_cnic()
381 return -EINVAL; in bnx2_register_cnic()
383 if (cp->drv_state & CNIC_DRV_STATE_REGD) in bnx2_register_cnic()
384 return -EBUSY; in bnx2_register_cnic()
387 return -ENODEV; in bnx2_register_cnic()
389 bp->cnic_data = data; in bnx2_register_cnic()
390 rcu_assign_pointer(bp->cnic_ops, ops); in bnx2_register_cnic()
392 cp->num_irq = 0; in bnx2_register_cnic()
393 cp->drv_state = CNIC_DRV_STATE_REGD; in bnx2_register_cnic()
403 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; in bnx2_unregister_cnic()
404 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; in bnx2_unregister_cnic()
406 mutex_lock(&bp->cnic_lock); in bnx2_unregister_cnic()
407 cp->drv_state = 0; in bnx2_unregister_cnic()
408 bnapi->cnic_present = 0; in bnx2_unregister_cnic()
409 RCU_INIT_POINTER(bp->cnic_ops, NULL); in bnx2_unregister_cnic()
410 mutex_unlock(&bp->cnic_lock); in bnx2_unregister_cnic()
418 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; in bnx2_cnic_probe()
420 if (!cp->max_iscsi_conn) in bnx2_cnic_probe()
423 cp->drv_owner = THIS_MODULE; in bnx2_cnic_probe()
424 cp->chip_id = bp->chip_id; in bnx2_cnic_probe()
425 cp->pdev = bp->pdev; in bnx2_cnic_probe()
426 cp->io_base = bp->regview; in bnx2_cnic_probe()
427 cp->drv_ctl = bnx2_drv_ctl; in bnx2_cnic_probe()
428 cp->drv_register_cnic = bnx2_register_cnic; in bnx2_cnic_probe()
429 cp->drv_unregister_cnic = bnx2_unregister_cnic; in bnx2_cnic_probe()
440 mutex_lock(&bp->cnic_lock); in bnx2_cnic_stop()
441 c_ops = rcu_dereference_protected(bp->cnic_ops, in bnx2_cnic_stop()
442 lockdep_is_held(&bp->cnic_lock)); in bnx2_cnic_stop()
445 c_ops->cnic_ctl(bp->cnic_data, &info); in bnx2_cnic_stop()
447 mutex_unlock(&bp->cnic_lock); in bnx2_cnic_stop()
456 mutex_lock(&bp->cnic_lock); in bnx2_cnic_start()
457 c_ops = rcu_dereference_protected(bp->cnic_ops, in bnx2_cnic_start()
458 lockdep_is_held(&bp->cnic_lock)); in bnx2_cnic_start()
460 if (!(bp->flags & BNX2_FLAG_USING_MSIX)) { in bnx2_cnic_start()
461 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; in bnx2_cnic_start()
463 bnapi->cnic_tag = bnapi->last_status_idx; in bnx2_cnic_start()
466 c_ops->cnic_ctl(bp->cnic_data, &info); in bnx2_cnic_start()
468 mutex_unlock(&bp->cnic_lock); in bnx2_cnic_start()
491 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { in bnx2_read_phy()
501 val1 = (bp->phy_addr << 21) | (reg << 16) | in bnx2_read_phy()
522 ret = -EBUSY; in bnx2_read_phy()
529 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { in bnx2_read_phy()
548 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { in bnx2_write_phy()
558 val1 = (bp->phy_addr << 21) | (reg << 16) | val | in bnx2_write_phy()
574 ret = -EBUSY; in bnx2_write_phy()
578 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { in bnx2_write_phy()
597 for (i = 0; i < bp->irq_nvecs; i++) { in bnx2_disable_int()
598 bnapi = &bp->bnx2_napi[i]; in bnx2_disable_int()
599 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | in bnx2_disable_int()
611 for (i = 0; i < bp->irq_nvecs; i++) { in bnx2_enable_int()
612 bnapi = &bp->bnx2_napi[i]; in bnx2_enable_int()
614 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | in bnx2_enable_int()
617 bnapi->last_status_idx); in bnx2_enable_int()
619 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | in bnx2_enable_int()
621 bnapi->last_status_idx); in bnx2_enable_int()
623 BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW); in bnx2_enable_int()
631 atomic_inc(&bp->intr_sem); in bnx2_disable_int_sync()
632 if (!netif_running(bp->dev)) in bnx2_disable_int_sync()
636 for (i = 0; i < bp->irq_nvecs; i++) in bnx2_disable_int_sync()
637 synchronize_irq(bp->irq_tbl[i].vector); in bnx2_disable_int_sync()
645 for (i = 0; i < bp->irq_nvecs; i++) in bnx2_napi_disable()
646 napi_disable(&bp->bnx2_napi[i].napi); in bnx2_napi_disable()
654 for (i = 0; i < bp->irq_nvecs; i++) in bnx2_napi_enable()
655 napi_enable(&bp->bnx2_napi[i].napi); in bnx2_napi_enable()
663 if (netif_running(bp->dev)) { in bnx2_netif_stop()
665 netif_tx_disable(bp->dev); in bnx2_netif_stop()
668 netif_carrier_off(bp->dev); /* prevent tx timeout */ in bnx2_netif_stop()
674 if (atomic_dec_and_test(&bp->intr_sem)) { in bnx2_netif_start()
675 if (netif_running(bp->dev)) { in bnx2_netif_start()
676 netif_tx_wake_all_queues(bp->dev); in bnx2_netif_start()
677 spin_lock_bh(&bp->phy_lock); in bnx2_netif_start()
678 if (bp->link_up) in bnx2_netif_start()
679 netif_carrier_on(bp->dev); in bnx2_netif_start()
680 spin_unlock_bh(&bp->phy_lock); in bnx2_netif_start()
694 for (i = 0; i < bp->num_tx_rings; i++) { in bnx2_free_tx_mem()
695 struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; in bnx2_free_tx_mem()
696 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; in bnx2_free_tx_mem()
698 if (txr->tx_desc_ring) { in bnx2_free_tx_mem()
699 dma_free_coherent(&bp->pdev->dev, TXBD_RING_SIZE, in bnx2_free_tx_mem()
700 txr->tx_desc_ring, in bnx2_free_tx_mem()
701 txr->tx_desc_mapping); in bnx2_free_tx_mem()
702 txr->tx_desc_ring = NULL; in bnx2_free_tx_mem()
704 kfree(txr->tx_buf_ring); in bnx2_free_tx_mem()
705 txr->tx_buf_ring = NULL; in bnx2_free_tx_mem()
714 for (i = 0; i < bp->num_rx_rings; i++) { in bnx2_free_rx_mem()
715 struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; in bnx2_free_rx_mem()
716 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; in bnx2_free_rx_mem()
719 for (j = 0; j < bp->rx_max_ring; j++) { in bnx2_free_rx_mem()
720 if (rxr->rx_desc_ring[j]) in bnx2_free_rx_mem()
721 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE, in bnx2_free_rx_mem()
722 rxr->rx_desc_ring[j], in bnx2_free_rx_mem()
723 rxr->rx_desc_mapping[j]); in bnx2_free_rx_mem()
724 rxr->rx_desc_ring[j] = NULL; in bnx2_free_rx_mem()
726 vfree(rxr->rx_buf_ring); in bnx2_free_rx_mem()
727 rxr->rx_buf_ring = NULL; in bnx2_free_rx_mem()
729 for (j = 0; j < bp->rx_max_pg_ring; j++) { in bnx2_free_rx_mem()
730 if (rxr->rx_pg_desc_ring[j]) in bnx2_free_rx_mem()
731 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE, in bnx2_free_rx_mem()
732 rxr->rx_pg_desc_ring[j], in bnx2_free_rx_mem()
733 rxr->rx_pg_desc_mapping[j]); in bnx2_free_rx_mem()
734 rxr->rx_pg_desc_ring[j] = NULL; in bnx2_free_rx_mem()
736 vfree(rxr->rx_pg_ring); in bnx2_free_rx_mem()
737 rxr->rx_pg_ring = NULL; in bnx2_free_rx_mem()
746 for (i = 0; i < bp->num_tx_rings; i++) { in bnx2_alloc_tx_mem()
747 struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; in bnx2_alloc_tx_mem()
748 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; in bnx2_alloc_tx_mem()
750 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL); in bnx2_alloc_tx_mem()
751 if (!txr->tx_buf_ring) in bnx2_alloc_tx_mem()
752 return -ENOMEM; in bnx2_alloc_tx_mem()
754 txr->tx_desc_ring = in bnx2_alloc_tx_mem()
755 dma_alloc_coherent(&bp->pdev->dev, TXBD_RING_SIZE, in bnx2_alloc_tx_mem()
756 &txr->tx_desc_mapping, GFP_KERNEL); in bnx2_alloc_tx_mem()
757 if (!txr->tx_desc_ring) in bnx2_alloc_tx_mem()
758 return -ENOMEM; in bnx2_alloc_tx_mem()
768 for (i = 0; i < bp->num_rx_rings; i++) { in bnx2_alloc_rx_mem()
769 struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; in bnx2_alloc_rx_mem()
770 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; in bnx2_alloc_rx_mem()
773 rxr->rx_buf_ring = in bnx2_alloc_rx_mem()
774 vzalloc(array_size(SW_RXBD_RING_SIZE, bp->rx_max_ring)); in bnx2_alloc_rx_mem()
775 if (!rxr->rx_buf_ring) in bnx2_alloc_rx_mem()
776 return -ENOMEM; in bnx2_alloc_rx_mem()
778 for (j = 0; j < bp->rx_max_ring; j++) { in bnx2_alloc_rx_mem()
779 rxr->rx_desc_ring[j] = in bnx2_alloc_rx_mem()
780 dma_alloc_coherent(&bp->pdev->dev, in bnx2_alloc_rx_mem()
782 &rxr->rx_desc_mapping[j], in bnx2_alloc_rx_mem()
784 if (!rxr->rx_desc_ring[j]) in bnx2_alloc_rx_mem()
785 return -ENOMEM; in bnx2_alloc_rx_mem()
789 if (bp->rx_pg_ring_size) { in bnx2_alloc_rx_mem()
790 rxr->rx_pg_ring = in bnx2_alloc_rx_mem()
792 bp->rx_max_pg_ring)); in bnx2_alloc_rx_mem()
793 if (!rxr->rx_pg_ring) in bnx2_alloc_rx_mem()
794 return -ENOMEM; in bnx2_alloc_rx_mem()
798 for (j = 0; j < bp->rx_max_pg_ring; j++) { in bnx2_alloc_rx_mem()
799 rxr->rx_pg_desc_ring[j] = in bnx2_alloc_rx_mem()
800 dma_alloc_coherent(&bp->pdev->dev, in bnx2_alloc_rx_mem()
802 &rxr->rx_pg_desc_mapping[j], in bnx2_alloc_rx_mem()
804 if (!rxr->rx_pg_desc_ring[j]) in bnx2_alloc_rx_mem()
805 return -ENOMEM; in bnx2_alloc_rx_mem()
817 if (bp->status_blk) { in bnx2_free_stats_blk()
818 dma_free_coherent(&bp->pdev->dev, bp->status_stats_size, in bnx2_free_stats_blk()
819 bp->status_blk, in bnx2_free_stats_blk()
820 bp->status_blk_mapping); in bnx2_free_stats_blk()
821 bp->status_blk = NULL; in bnx2_free_stats_blk()
822 bp->stats_blk = NULL; in bnx2_free_stats_blk()
835 if (bp->flags & BNX2_FLAG_MSIX_CAP) in bnx2_alloc_stats_blk()
838 bp->status_stats_size = status_blk_size + in bnx2_alloc_stats_blk()
840 status_blk = dma_alloc_coherent(&bp->pdev->dev, bp->status_stats_size, in bnx2_alloc_stats_blk()
841 &bp->status_blk_mapping, GFP_KERNEL); in bnx2_alloc_stats_blk()
843 return -ENOMEM; in bnx2_alloc_stats_blk()
845 bp->status_blk = status_blk; in bnx2_alloc_stats_blk()
846 bp->stats_blk = status_blk + status_blk_size; in bnx2_alloc_stats_blk()
847 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size; in bnx2_alloc_stats_blk()
856 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; in bnx2_free_mem()
861 for (i = 0; i < bp->ctx_pages; i++) { in bnx2_free_mem()
862 if (bp->ctx_blk[i]) { in bnx2_free_mem()
863 dma_free_coherent(&bp->pdev->dev, BNX2_PAGE_SIZE, in bnx2_free_mem()
864 bp->ctx_blk[i], in bnx2_free_mem()
865 bp->ctx_blk_mapping[i]); in bnx2_free_mem()
866 bp->ctx_blk[i] = NULL; in bnx2_free_mem()
870 if (bnapi->status_blk.msi) in bnx2_free_mem()
871 bnapi->status_blk.msi = NULL; in bnx2_free_mem()
880 bnapi = &bp->bnx2_napi[0]; in bnx2_alloc_mem()
881 bnapi->status_blk.msi = bp->status_blk; in bnx2_alloc_mem()
882 bnapi->hw_tx_cons_ptr = in bnx2_alloc_mem()
883 &bnapi->status_blk.msi->status_tx_quick_consumer_index0; in bnx2_alloc_mem()
884 bnapi->hw_rx_cons_ptr = in bnx2_alloc_mem()
885 &bnapi->status_blk.msi->status_rx_quick_consumer_index0; in bnx2_alloc_mem()
886 if (bp->flags & BNX2_FLAG_MSIX_CAP) { in bnx2_alloc_mem()
887 for (i = 1; i < bp->irq_nvecs; i++) { in bnx2_alloc_mem()
890 bnapi = &bp->bnx2_napi[i]; in bnx2_alloc_mem()
892 sblk = (bp->status_blk + BNX2_SBLK_MSIX_ALIGN_SIZE * i); in bnx2_alloc_mem()
893 bnapi->status_blk.msix = sblk; in bnx2_alloc_mem()
894 bnapi->hw_tx_cons_ptr = in bnx2_alloc_mem()
895 &sblk->status_tx_quick_consumer_index; in bnx2_alloc_mem()
896 bnapi->hw_rx_cons_ptr = in bnx2_alloc_mem()
897 &sblk->status_rx_quick_consumer_index; in bnx2_alloc_mem()
898 bnapi->int_num = i << 24; in bnx2_alloc_mem()
903 bp->ctx_pages = 0x2000 / BNX2_PAGE_SIZE; in bnx2_alloc_mem()
904 if (bp->ctx_pages == 0) in bnx2_alloc_mem()
905 bp->ctx_pages = 1; in bnx2_alloc_mem()
906 for (i = 0; i < bp->ctx_pages; i++) { in bnx2_alloc_mem()
907 bp->ctx_blk[i] = dma_alloc_coherent(&bp->pdev->dev, in bnx2_alloc_mem()
909 &bp->ctx_blk_mapping[i], in bnx2_alloc_mem()
911 if (!bp->ctx_blk[i]) in bnx2_alloc_mem()
928 return -ENOMEM; in bnx2_alloc_mem()
936 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) in bnx2_report_fw_link()
939 if (bp->link_up) { in bnx2_report_fw_link()
942 switch (bp->line_speed) { in bnx2_report_fw_link()
944 if (bp->duplex == DUPLEX_HALF) in bnx2_report_fw_link()
950 if (bp->duplex == DUPLEX_HALF) in bnx2_report_fw_link()
956 if (bp->duplex == DUPLEX_HALF) in bnx2_report_fw_link()
962 if (bp->duplex == DUPLEX_HALF) in bnx2_report_fw_link()
971 if (bp->autoneg) { in bnx2_report_fw_link()
974 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); in bnx2_report_fw_link()
975 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); in bnx2_report_fw_link()
978 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) in bnx2_report_fw_link()
993 return (bp->phy_port == PORT_FIBRE) ? "SerDes" : in bnx2_xceiver_str()
994 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" : in bnx2_xceiver_str()
1001 if (bp->link_up) { in bnx2_report_link()
1002 netif_carrier_on(bp->dev); in bnx2_report_link()
1003 netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex", in bnx2_report_link()
1005 bp->line_speed, in bnx2_report_link()
1006 bp->duplex == DUPLEX_FULL ? "full" : "half"); in bnx2_report_link()
1008 if (bp->flow_ctrl) { in bnx2_report_link()
1009 if (bp->flow_ctrl & FLOW_CTRL_RX) { in bnx2_report_link()
1011 if (bp->flow_ctrl & FLOW_CTRL_TX) in bnx2_report_link()
1021 netif_carrier_off(bp->dev); in bnx2_report_link()
1022 netdev_err(bp->dev, "NIC %s Link is Down\n", in bnx2_report_link()
1034 bp->flow_ctrl = 0; in bnx2_resolve_flow_ctrl()
1035 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) != in bnx2_resolve_flow_ctrl()
1038 if (bp->duplex == DUPLEX_FULL) { in bnx2_resolve_flow_ctrl()
1039 bp->flow_ctrl = bp->req_flow_ctrl; in bnx2_resolve_flow_ctrl()
1044 if (bp->duplex != DUPLEX_FULL) { in bnx2_resolve_flow_ctrl()
1048 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && in bnx2_resolve_flow_ctrl()
1054 bp->flow_ctrl |= FLOW_CTRL_TX; in bnx2_resolve_flow_ctrl()
1056 bp->flow_ctrl |= FLOW_CTRL_RX; in bnx2_resolve_flow_ctrl()
1060 bnx2_read_phy(bp, bp->mii_adv, &local_adv); in bnx2_resolve_flow_ctrl()
1061 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); in bnx2_resolve_flow_ctrl()
1063 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { in bnx2_resolve_flow_ctrl()
1080 /* See Table 28B-3 of 802.3ab-1999 spec. */ in bnx2_resolve_flow_ctrl()
1084 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; in bnx2_resolve_flow_ctrl()
1087 bp->flow_ctrl = FLOW_CTRL_RX; in bnx2_resolve_flow_ctrl()
1092 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; in bnx2_resolve_flow_ctrl()
1100 bp->flow_ctrl = FLOW_CTRL_TX; in bnx2_resolve_flow_ctrl()
1110 bp->link_up = 1; in bnx2_5709s_linkup()
1116 if ((bp->autoneg & AUTONEG_SPEED) == 0) { in bnx2_5709s_linkup()
1117 bp->line_speed = bp->req_line_speed; in bnx2_5709s_linkup()
1118 bp->duplex = bp->req_duplex; in bnx2_5709s_linkup()
1124 bp->line_speed = SPEED_10; in bnx2_5709s_linkup()
1127 bp->line_speed = SPEED_100; in bnx2_5709s_linkup()
1131 bp->line_speed = SPEED_1000; in bnx2_5709s_linkup()
1134 bp->line_speed = SPEED_2500; in bnx2_5709s_linkup()
1138 bp->duplex = DUPLEX_FULL; in bnx2_5709s_linkup()
1140 bp->duplex = DUPLEX_HALF; in bnx2_5709s_linkup()
1149 bp->link_up = 1; in bnx2_5708s_linkup()
1153 bp->line_speed = SPEED_10; in bnx2_5708s_linkup()
1156 bp->line_speed = SPEED_100; in bnx2_5708s_linkup()
1159 bp->line_speed = SPEED_1000; in bnx2_5708s_linkup()
1162 bp->line_speed = SPEED_2500; in bnx2_5708s_linkup()
1166 bp->duplex = DUPLEX_FULL; in bnx2_5708s_linkup()
1168 bp->duplex = DUPLEX_HALF; in bnx2_5708s_linkup()
1178 bp->link_up = 1; in bnx2_5706s_linkup()
1179 bp->line_speed = SPEED_1000; in bnx2_5706s_linkup()
1181 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); in bnx2_5706s_linkup()
1183 bp->duplex = DUPLEX_FULL; in bnx2_5706s_linkup()
1186 bp->duplex = DUPLEX_HALF; in bnx2_5706s_linkup()
1193 bnx2_read_phy(bp, bp->mii_adv, &local_adv); in bnx2_5706s_linkup()
1194 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); in bnx2_5706s_linkup()
1200 bp->duplex = DUPLEX_FULL; in bnx2_5706s_linkup()
1203 bp->duplex = DUPLEX_HALF; in bnx2_5706s_linkup()
1215 bp->phy_flags &= ~BNX2_PHY_FLAG_MDIX; in bnx2_copper_linkup()
1217 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); in bnx2_copper_linkup()
1226 bp->line_speed = SPEED_1000; in bnx2_copper_linkup()
1227 bp->duplex = DUPLEX_FULL; in bnx2_copper_linkup()
1230 bp->line_speed = SPEED_1000; in bnx2_copper_linkup()
1231 bp->duplex = DUPLEX_HALF; in bnx2_copper_linkup()
1234 bnx2_read_phy(bp, bp->mii_adv, &local_adv); in bnx2_copper_linkup()
1235 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); in bnx2_copper_linkup()
1239 bp->line_speed = SPEED_100; in bnx2_copper_linkup()
1240 bp->duplex = DUPLEX_FULL; in bnx2_copper_linkup()
1243 bp->line_speed = SPEED_100; in bnx2_copper_linkup()
1244 bp->duplex = DUPLEX_HALF; in bnx2_copper_linkup()
1247 bp->line_speed = SPEED_10; in bnx2_copper_linkup()
1248 bp->duplex = DUPLEX_FULL; in bnx2_copper_linkup()
1251 bp->line_speed = SPEED_10; in bnx2_copper_linkup()
1252 bp->duplex = DUPLEX_HALF; in bnx2_copper_linkup()
1255 bp->line_speed = 0; in bnx2_copper_linkup()
1256 bp->link_up = 0; in bnx2_copper_linkup()
1262 bp->line_speed = SPEED_100; in bnx2_copper_linkup()
1265 bp->line_speed = SPEED_10; in bnx2_copper_linkup()
1268 bp->duplex = DUPLEX_FULL; in bnx2_copper_linkup()
1271 bp->duplex = DUPLEX_HALF; in bnx2_copper_linkup()
1275 if (bp->link_up) { in bnx2_copper_linkup()
1280 bp->phy_flags |= BNX2_PHY_FLAG_MDIX; in bnx2_copper_linkup()
1295 if (bp->flow_ctrl & FLOW_CTRL_TX) in bnx2_init_rx_context()
1307 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) { in bnx2_init_all_rx_contexts()
1320 if (bp->link_up && (bp->line_speed == SPEED_1000) && in bnx2_set_mac_link()
1321 (bp->duplex == DUPLEX_HALF)) { in bnx2_set_mac_link()
1332 if (bp->link_up) { in bnx2_set_mac_link()
1333 switch (bp->line_speed) { in bnx2_set_mac_link()
1356 if (bp->duplex == DUPLEX_HALF) in bnx2_set_mac_link()
1361 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN; in bnx2_set_mac_link()
1363 if (bp->flow_ctrl & FLOW_CTRL_RX) in bnx2_set_mac_link()
1364 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN; in bnx2_set_mac_link()
1365 BNX2_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode); in bnx2_set_mac_link()
1371 if (bp->flow_ctrl & FLOW_CTRL_TX) in bnx2_set_mac_link()
1384 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && in bnx2_enable_bmsr1()
1393 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && in bnx2_disable_bmsr1()
1405 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) in bnx2_test_and_enable_2g5()
1408 if (bp->autoneg & AUTONEG_SPEED) in bnx2_test_and_enable_2g5()
1409 bp->advertising |= ADVERTISED_2500baseX_Full; in bnx2_test_and_enable_2g5()
1414 bnx2_read_phy(bp, bp->mii_up1, &up1); in bnx2_test_and_enable_2g5()
1417 bnx2_write_phy(bp, bp->mii_up1, up1); in bnx2_test_and_enable_2g5()
1434 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) in bnx2_test_and_disable_2g5()
1440 bnx2_read_phy(bp, bp->mii_up1, &up1); in bnx2_test_and_disable_2g5()
1443 bnx2_write_phy(bp, bp->mii_up1, up1); in bnx2_test_and_disable_2g5()
1460 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) in bnx2_enable_forced_2g5()
1477 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); in bnx2_enable_forced_2g5()
1480 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); in bnx2_enable_forced_2g5()
1490 if (bp->autoneg & AUTONEG_SPEED) { in bnx2_enable_forced_2g5()
1492 if (bp->req_duplex == DUPLEX_FULL) in bnx2_enable_forced_2g5()
1495 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); in bnx2_enable_forced_2g5()
1504 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) in bnx2_disable_forced_2g5()
1519 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); in bnx2_disable_forced_2g5()
1522 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); in bnx2_disable_forced_2g5()
1532 if (bp->autoneg & AUTONEG_SPEED) in bnx2_disable_forced_2g5()
1534 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); in bnx2_disable_forced_2g5()
1556 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) { in bnx2_set_link()
1557 bp->link_up = 1; in bnx2_set_link()
1561 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) in bnx2_set_link()
1564 link_up = bp->link_up; in bnx2_set_link()
1567 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); in bnx2_set_link()
1568 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); in bnx2_set_link()
1571 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && in bnx2_set_link()
1575 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) { in bnx2_set_link()
1577 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN; in bnx2_set_link()
1593 bp->link_up = 1; in bnx2_set_link()
1595 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { in bnx2_set_link()
1609 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && in bnx2_set_link()
1610 (bp->autoneg & AUTONEG_SPEED)) in bnx2_set_link()
1613 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) { in bnx2_set_link()
1616 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); in bnx2_set_link()
1618 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); in bnx2_set_link()
1620 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT; in bnx2_set_link()
1622 bp->link_up = 0; in bnx2_set_link()
1625 if (bp->link_up != link_up) { in bnx2_set_link()
1640 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET); in bnx2_reset_phy()
1646 bnx2_read_phy(bp, bp->mii_bmcr, ®); in bnx2_reset_phy()
1653 return -EBUSY; in bnx2_reset_phy()
1661 u32 adv = 0; in bnx2_phy_get_pause_adv() local
1663 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) == in bnx2_phy_get_pause_adv()
1666 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { in bnx2_phy_get_pause_adv()
1667 adv = ADVERTISE_1000XPAUSE; in bnx2_phy_get_pause_adv()
1670 adv = ADVERTISE_PAUSE_CAP; in bnx2_phy_get_pause_adv()
1673 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) { in bnx2_phy_get_pause_adv()
1674 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { in bnx2_phy_get_pause_adv()
1675 adv = ADVERTISE_1000XPSE_ASYM; in bnx2_phy_get_pause_adv()
1678 adv = ADVERTISE_PAUSE_ASYM; in bnx2_phy_get_pause_adv()
1681 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) { in bnx2_phy_get_pause_adv()
1682 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { in bnx2_phy_get_pause_adv()
1683 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; in bnx2_phy_get_pause_adv()
1686 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; in bnx2_phy_get_pause_adv()
1689 return adv; in bnx2_phy_get_pause_adv()
1696 __releases(&bp->phy_lock) in bnx2_setup_remote_phy()
1697 __acquires(&bp->phy_lock) in bnx2_setup_remote_phy()
1703 if (bp->autoneg & AUTONEG_SPEED) { in bnx2_setup_remote_phy()
1705 if (bp->advertising & ADVERTISED_10baseT_Half) in bnx2_setup_remote_phy()
1707 if (bp->advertising & ADVERTISED_10baseT_Full) in bnx2_setup_remote_phy()
1709 if (bp->advertising & ADVERTISED_100baseT_Half) in bnx2_setup_remote_phy()
1711 if (bp->advertising & ADVERTISED_100baseT_Full) in bnx2_setup_remote_phy()
1713 if (bp->advertising & ADVERTISED_1000baseT_Full) in bnx2_setup_remote_phy()
1715 if (bp->advertising & ADVERTISED_2500baseX_Full) in bnx2_setup_remote_phy()
1718 if (bp->req_line_speed == SPEED_2500) in bnx2_setup_remote_phy()
1720 else if (bp->req_line_speed == SPEED_1000) in bnx2_setup_remote_phy()
1722 else if (bp->req_line_speed == SPEED_100) { in bnx2_setup_remote_phy()
1723 if (bp->req_duplex == DUPLEX_FULL) in bnx2_setup_remote_phy()
1727 } else if (bp->req_line_speed == SPEED_10) { in bnx2_setup_remote_phy()
1728 if (bp->req_duplex == DUPLEX_FULL) in bnx2_setup_remote_phy()
1746 spin_unlock_bh(&bp->phy_lock); in bnx2_setup_remote_phy()
1748 spin_lock_bh(&bp->phy_lock); in bnx2_setup_remote_phy()
1755 __releases(&bp->phy_lock) in bnx2_setup_serdes_phy()
1756 __acquires(&bp->phy_lock) in bnx2_setup_serdes_phy()
1758 u32 adv, bmcr; in bnx2_setup_serdes_phy() local
1761 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) in bnx2_setup_serdes_phy()
1764 if (!(bp->autoneg & AUTONEG_SPEED)) { in bnx2_setup_serdes_phy()
1768 if (bp->req_line_speed == SPEED_2500) { in bnx2_setup_serdes_phy()
1771 } else if (bp->req_line_speed == SPEED_1000) { in bnx2_setup_serdes_phy()
1775 bnx2_read_phy(bp, bp->mii_adv, &adv); in bnx2_setup_serdes_phy()
1776 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF); in bnx2_setup_serdes_phy()
1778 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); in bnx2_setup_serdes_phy()
1783 if (bp->req_line_speed == SPEED_2500) in bnx2_setup_serdes_phy()
1785 else if (bp->req_line_speed == SPEED_1000) { in bnx2_setup_serdes_phy()
1791 if (bp->req_line_speed == SPEED_2500) in bnx2_setup_serdes_phy()
1797 if (bp->req_duplex == DUPLEX_FULL) { in bnx2_setup_serdes_phy()
1798 adv |= ADVERTISE_1000XFULL; in bnx2_setup_serdes_phy()
1802 adv |= ADVERTISE_1000XHALF; in bnx2_setup_serdes_phy()
1807 if (bp->link_up) { in bnx2_setup_serdes_phy()
1808 bnx2_write_phy(bp, bp->mii_adv, adv & in bnx2_setup_serdes_phy()
1811 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | in bnx2_setup_serdes_phy()
1814 bp->link_up = 0; in bnx2_setup_serdes_phy()
1815 netif_carrier_off(bp->dev); in bnx2_setup_serdes_phy()
1816 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); in bnx2_setup_serdes_phy()
1819 bnx2_write_phy(bp, bp->mii_adv, adv); in bnx2_setup_serdes_phy()
1820 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); in bnx2_setup_serdes_phy()
1830 if (bp->advertising & ADVERTISED_1000baseT_Full) in bnx2_setup_serdes_phy()
1835 bnx2_read_phy(bp, bp->mii_adv, &adv); in bnx2_setup_serdes_phy()
1836 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); in bnx2_setup_serdes_phy()
1838 bp->serdes_an_pending = 0; in bnx2_setup_serdes_phy()
1839 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) { in bnx2_setup_serdes_phy()
1841 if (bp->link_up) { in bnx2_setup_serdes_phy()
1842 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); in bnx2_setup_serdes_phy()
1843 spin_unlock_bh(&bp->phy_lock); in bnx2_setup_serdes_phy()
1845 spin_lock_bh(&bp->phy_lock); in bnx2_setup_serdes_phy()
1848 bnx2_write_phy(bp, bp->mii_adv, new_adv); in bnx2_setup_serdes_phy()
1849 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | in bnx2_setup_serdes_phy()
1851 /* Speed up link-up time when the link partner in bnx2_setup_serdes_phy()
1859 bp->current_interval = BNX2_SERDES_AN_TIMEOUT; in bnx2_setup_serdes_phy()
1860 bp->serdes_an_pending = 1; in bnx2_setup_serdes_phy()
1861 mod_timer(&bp->timer, jiffies + bp->current_interval); in bnx2_setup_serdes_phy()
1871 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
1890 if (bp->phy_port == PORT_TP) in bnx2_set_default_remote_link()
1896 bp->req_line_speed = 0; in bnx2_set_default_remote_link()
1897 bp->autoneg |= AUTONEG_SPEED; in bnx2_set_default_remote_link()
1898 bp->advertising = ADVERTISED_Autoneg; in bnx2_set_default_remote_link()
1900 bp->advertising |= ADVERTISED_10baseT_Half; in bnx2_set_default_remote_link()
1902 bp->advertising |= ADVERTISED_10baseT_Full; in bnx2_set_default_remote_link()
1904 bp->advertising |= ADVERTISED_100baseT_Half; in bnx2_set_default_remote_link()
1906 bp->advertising |= ADVERTISED_100baseT_Full; in bnx2_set_default_remote_link()
1908 bp->advertising |= ADVERTISED_1000baseT_Full; in bnx2_set_default_remote_link()
1910 bp->advertising |= ADVERTISED_2500baseX_Full; in bnx2_set_default_remote_link()
1912 bp->autoneg = 0; in bnx2_set_default_remote_link()
1913 bp->advertising = 0; in bnx2_set_default_remote_link()
1914 bp->req_duplex = DUPLEX_FULL; in bnx2_set_default_remote_link()
1916 bp->req_line_speed = SPEED_10; in bnx2_set_default_remote_link()
1918 bp->req_duplex = DUPLEX_HALF; in bnx2_set_default_remote_link()
1921 bp->req_line_speed = SPEED_100; in bnx2_set_default_remote_link()
1923 bp->req_duplex = DUPLEX_HALF; in bnx2_set_default_remote_link()
1926 bp->req_line_speed = SPEED_1000; in bnx2_set_default_remote_link()
1928 bp->req_line_speed = SPEED_2500; in bnx2_set_default_remote_link()
1935 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { in bnx2_set_default_link()
1940 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL; in bnx2_set_default_link()
1941 bp->req_line_speed = 0; in bnx2_set_default_link()
1942 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { in bnx2_set_default_link()
1945 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg; in bnx2_set_default_link()
1950 bp->autoneg = 0; in bnx2_set_default_link()
1951 bp->req_line_speed = bp->line_speed = SPEED_1000; in bnx2_set_default_link()
1952 bp->req_duplex = DUPLEX_FULL; in bnx2_set_default_link()
1955 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg; in bnx2_set_default_link()
1964 spin_lock(&bp->indirect_lock); in bnx2_send_heart_beat()
1965 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK); in bnx2_send_heart_beat()
1966 addr = bp->shmem_base + BNX2_DRV_PULSE_MB; in bnx2_send_heart_beat()
1969 spin_unlock(&bp->indirect_lock); in bnx2_send_heart_beat()
1976 u8 link_up = bp->link_up; in bnx2_remote_phy_event()
1987 bp->link_up = 0; in bnx2_remote_phy_event()
1991 bp->link_up = 1; in bnx2_remote_phy_event()
1993 bp->duplex = DUPLEX_FULL; in bnx2_remote_phy_event()
1996 bp->duplex = DUPLEX_HALF; in bnx2_remote_phy_event()
1999 bp->line_speed = SPEED_10; in bnx2_remote_phy_event()
2002 bp->duplex = DUPLEX_HALF; in bnx2_remote_phy_event()
2006 bp->line_speed = SPEED_100; in bnx2_remote_phy_event()
2009 bp->duplex = DUPLEX_HALF; in bnx2_remote_phy_event()
2012 bp->line_speed = SPEED_1000; in bnx2_remote_phy_event()
2015 bp->duplex = DUPLEX_HALF; in bnx2_remote_phy_event()
2018 bp->line_speed = SPEED_2500; in bnx2_remote_phy_event()
2021 bp->line_speed = 0; in bnx2_remote_phy_event()
2025 bp->flow_ctrl = 0; in bnx2_remote_phy_event()
2026 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) != in bnx2_remote_phy_event()
2028 if (bp->duplex == DUPLEX_FULL) in bnx2_remote_phy_event()
2029 bp->flow_ctrl = bp->req_flow_ctrl; in bnx2_remote_phy_event()
2032 bp->flow_ctrl |= FLOW_CTRL_TX; in bnx2_remote_phy_event()
2034 bp->flow_ctrl |= FLOW_CTRL_RX; in bnx2_remote_phy_event()
2037 old_port = bp->phy_port; in bnx2_remote_phy_event()
2039 bp->phy_port = PORT_FIBRE; in bnx2_remote_phy_event()
2041 bp->phy_port = PORT_TP; in bnx2_remote_phy_event()
2043 if (old_port != bp->phy_port) in bnx2_remote_phy_event()
2047 if (bp->link_up != link_up) in bnx2_remote_phy_event()
2073 __releases(&bp->phy_lock) in bnx2_setup_copper_phy()
2074 __acquires(&bp->phy_lock) in bnx2_setup_copper_phy()
2079 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); in bnx2_setup_copper_phy()
2081 bnx2_read_phy(bp, bp->mii_adv, &adv_reg); in bnx2_setup_copper_phy()
2085 new_adv = ADVERTISE_CSMA | ethtool_adv_to_mii_adv_t(bp->advertising); in bnx2_setup_copper_phy()
2087 if (bp->autoneg & AUTONEG_SPEED) { in bnx2_setup_copper_phy()
2096 new_adv1000 |= ethtool_adv_to_mii_ctrl1000_t(bp->advertising); in bnx2_setup_copper_phy()
2101 bnx2_write_phy(bp, bp->mii_adv, new_adv); in bnx2_setup_copper_phy()
2103 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART | in bnx2_setup_copper_phy()
2106 else if (bp->link_up) { in bnx2_setup_copper_phy()
2108 /* or vice-versa. */ in bnx2_setup_copper_phy()
2118 bnx2_write_phy(bp, bp->mii_adv, new_adv); in bnx2_setup_copper_phy()
2121 if (bp->req_line_speed == SPEED_100) { in bnx2_setup_copper_phy()
2124 if (bp->req_duplex == DUPLEX_FULL) { in bnx2_setup_copper_phy()
2130 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); in bnx2_setup_copper_phy()
2131 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); in bnx2_setup_copper_phy()
2135 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); in bnx2_setup_copper_phy()
2136 spin_unlock_bh(&bp->phy_lock); in bnx2_setup_copper_phy()
2138 spin_lock_bh(&bp->phy_lock); in bnx2_setup_copper_phy()
2140 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); in bnx2_setup_copper_phy()
2141 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); in bnx2_setup_copper_phy()
2144 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); in bnx2_setup_copper_phy()
2151 bp->line_speed = bp->req_line_speed; in bnx2_setup_copper_phy()
2152 bp->duplex = bp->req_duplex; in bnx2_setup_copper_phy()
2165 __releases(&bp->phy_lock) in bnx2_setup_phy()
2166 __acquires(&bp->phy_lock) in bnx2_setup_phy()
2168 if (bp->loopback == MAC_LOOPBACK) in bnx2_setup_phy()
2171 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { in bnx2_setup_phy()
2184 bp->mii_bmcr = MII_BMCR + 0x10; in bnx2_init_5709s_phy()
2185 bp->mii_bmsr = MII_BMSR + 0x10; in bnx2_init_5709s_phy()
2186 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1; in bnx2_init_5709s_phy()
2187 bp->mii_adv = MII_ADVERTISE + 0x10; in bnx2_init_5709s_phy()
2188 bp->mii_lpa = MII_LPA + 0x10; in bnx2_init_5709s_phy()
2189 bp->mii_up1 = MII_BNX2_OVER1G_UP1; in bnx2_init_5709s_phy()
2207 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) in bnx2_init_5709s_phy()
2237 bp->mii_up1 = BCM5708S_UP1; in bnx2_init_5708s_phy()
2251 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) { in bnx2_init_5708s_phy()
2293 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT; in bnx2_init_5706s_phy()
2298 if (bp->dev->mtu > ETH_DATA_LEN) { in bnx2_init_5706s_phy()
2333 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) { in bnx2_init_copper_phy()
2344 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) { in bnx2_init_copper_phy()
2352 if (bp->dev->mtu > ETH_DATA_LEN) { in bnx2_init_copper_phy()
2375 /* auto-mdix */ in bnx2_init_copper_phy()
2386 __releases(&bp->phy_lock) in bnx2_init_phy()
2387 __acquires(&bp->phy_lock) in bnx2_init_phy()
2392 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK; in bnx2_init_phy()
2393 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY; in bnx2_init_phy()
2395 bp->mii_bmcr = MII_BMCR; in bnx2_init_phy()
2396 bp->mii_bmsr = MII_BMSR; in bnx2_init_phy()
2397 bp->mii_bmsr1 = MII_BMSR; in bnx2_init_phy()
2398 bp->mii_adv = MII_ADVERTISE; in bnx2_init_phy()
2399 bp->mii_lpa = MII_LPA; in bnx2_init_phy()
2403 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) in bnx2_init_phy()
2407 bp->phy_id = val << 16; in bnx2_init_phy()
2409 bp->phy_id |= val & 0xffff; in bnx2_init_phy()
2411 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { in bnx2_init_phy()
2425 rc = bnx2_setup_phy(bp, bp->phy_port); in bnx2_init_phy()
2439 bp->link_up = 1; in bnx2_set_mac_loopback()
2451 spin_lock_bh(&bp->phy_lock); in bnx2_set_phy_loopback()
2452 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX | in bnx2_set_phy_loopback()
2454 spin_unlock_bh(&bp->phy_lock); in bnx2_set_phy_loopback()
2471 bp->link_up = 1; in bnx2_set_phy_loopback()
2478 struct net_device *dev = bp->dev; in bnx2_dump_mcp_state()
2481 netdev_err(dev, "<--- start MCP states dump --->\n"); in bnx2_dump_mcp_state()
2515 netdev_err(dev, "<--- end MCP states dump --->\n"); in bnx2_dump_mcp_state()
2524 bp->fw_wr_seq++; in bnx2_fw_sync()
2525 msg_data |= bp->fw_wr_seq; in bnx2_fw_sync()
2526 bp->fw_last_msg = msg_data; in bnx2_fw_sync()
2556 return -EBUSY; in bnx2_fw_sync()
2560 return -EIO; in bnx2_fw_sync()
2572 val |= (BNX2_PAGE_BITS - 8) << 16; in bnx2_init_5709_context()
2581 return -EBUSY; in bnx2_init_5709_context()
2583 for (i = 0; i < bp->ctx_pages; i++) { in bnx2_init_5709_context()
2586 if (bp->ctx_blk[i]) in bnx2_init_5709_context()
2587 memset(bp->ctx_blk[i], 0, BNX2_PAGE_SIZE); in bnx2_init_5709_context()
2589 return -ENOMEM; in bnx2_init_5709_context()
2592 (bp->ctx_blk_mapping[i] & 0xffffffff) | in bnx2_init_5709_context()
2595 (u64) bp->ctx_blk_mapping[i] >> 32); in bnx2_init_5709_context()
2606 ret = -EBUSY; in bnx2_init_5709_context()
2623 vcid--; in bnx2_init_context()
2665 return -ENOMEM; in bnx2_alloc_bad_rbuf()
2694 good_mbuf_cnt--; in bnx2_alloc_bad_rbuf()
2724 struct bnx2_sw_pg *rx_pg = &rxr->rx_pg_ring[index]; in bnx2_alloc_rx_page()
2726 &rxr->rx_pg_desc_ring[BNX2_RX_RING(index)][BNX2_RX_IDX(index)]; in bnx2_alloc_rx_page()
2730 return -ENOMEM; in bnx2_alloc_rx_page()
2731 mapping = dma_map_page(&bp->pdev->dev, page, 0, PAGE_SIZE, in bnx2_alloc_rx_page()
2733 if (dma_mapping_error(&bp->pdev->dev, mapping)) { in bnx2_alloc_rx_page()
2735 return -EIO; in bnx2_alloc_rx_page()
2738 rx_pg->page = page; in bnx2_alloc_rx_page()
2740 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32; in bnx2_alloc_rx_page()
2741 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff; in bnx2_alloc_rx_page()
2748 struct bnx2_sw_pg *rx_pg = &rxr->rx_pg_ring[index]; in bnx2_free_rx_page()
2749 struct page *page = rx_pg->page; in bnx2_free_rx_page()
2754 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(rx_pg, mapping), in bnx2_free_rx_page()
2758 rx_pg->page = NULL; in bnx2_free_rx_page()
2765 struct bnx2_sw_bd *rx_buf = &rxr->rx_buf_ring[index]; in bnx2_alloc_rx_data()
2768 &rxr->rx_desc_ring[BNX2_RX_RING(index)][BNX2_RX_IDX(index)]; in bnx2_alloc_rx_data()
2770 data = kmalloc(bp->rx_buf_size, gfp); in bnx2_alloc_rx_data()
2772 return -ENOMEM; in bnx2_alloc_rx_data()
2774 mapping = dma_map_single(&bp->pdev->dev, in bnx2_alloc_rx_data()
2776 bp->rx_buf_use_size, in bnx2_alloc_rx_data()
2778 if (dma_mapping_error(&bp->pdev->dev, mapping)) { in bnx2_alloc_rx_data()
2780 return -EIO; in bnx2_alloc_rx_data()
2783 rx_buf->data = data; in bnx2_alloc_rx_data()
2786 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32; in bnx2_alloc_rx_data()
2787 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff; in bnx2_alloc_rx_data()
2789 rxr->rx_prod_bseq += bp->rx_buf_use_size; in bnx2_alloc_rx_data()
2797 struct status_block *sblk = bnapi->status_blk.msi; in bnx2_phy_event_is_set()
2801 new_link_state = sblk->status_attn_bits & event; in bnx2_phy_event_is_set()
2802 old_link_state = sblk->status_attn_bits_ack & event; in bnx2_phy_event_is_set()
2817 spin_lock(&bp->phy_lock); in bnx2_phy_int()
2824 spin_unlock(&bp->phy_lock); in bnx2_phy_int()
2833 cons = READ_ONCE(*bnapi->hw_tx_cons_ptr); in bnx2_get_hw_tx_cons()
2843 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; in bnx2_tx_int()
2849 index = (bnapi - bp->bnx2_napi); in bnx2_tx_int()
2850 txq = netdev_get_tx_queue(bp->dev, index); in bnx2_tx_int()
2853 sw_cons = txr->tx_cons; in bnx2_tx_int()
2862 tx_buf = &txr->tx_buf_ring[sw_ring_cons]; in bnx2_tx_int()
2863 skb = tx_buf->skb; in bnx2_tx_int()
2866 prefetch(&skb->end); in bnx2_tx_int()
2869 if (tx_buf->is_gso) { in bnx2_tx_int()
2872 last_idx = sw_cons + tx_buf->nr_frags + 1; in bnx2_tx_int()
2873 last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1; in bnx2_tx_int()
2877 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) { in bnx2_tx_int()
2882 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping), in bnx2_tx_int()
2885 tx_buf->skb = NULL; in bnx2_tx_int()
2886 last = tx_buf->nr_frags; in bnx2_tx_int()
2893 tx_buf = &txr->tx_buf_ring[BNX2_TX_RING_IDX(sw_cons)]; in bnx2_tx_int()
2894 dma_unmap_page(&bp->pdev->dev, in bnx2_tx_int()
2896 skb_frag_size(&skb_shinfo(skb)->frags[i]), in bnx2_tx_int()
2902 tx_bytes += skb->len; in bnx2_tx_int()
2913 txr->hw_tx_cons = hw_cons; in bnx2_tx_int()
2914 txr->tx_cons = sw_cons; in bnx2_tx_int()
2924 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) { in bnx2_tx_int()
2927 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) in bnx2_tx_int()
2943 u16 cons = rxr->rx_pg_cons; in bnx2_reuse_rx_skb_pages()
2945 cons_rx_pg = &rxr->rx_pg_ring[cons]; in bnx2_reuse_rx_skb_pages()
2956 shinfo->nr_frags--; in bnx2_reuse_rx_skb_pages()
2957 page = skb_frag_page(&shinfo->frags[shinfo->nr_frags]); in bnx2_reuse_rx_skb_pages()
2959 cons_rx_pg->page = page; in bnx2_reuse_rx_skb_pages()
2963 hw_prod = rxr->rx_pg_prod; in bnx2_reuse_rx_skb_pages()
2968 prod_rx_pg = &rxr->rx_pg_ring[prod]; in bnx2_reuse_rx_skb_pages()
2969 cons_rx_pg = &rxr->rx_pg_ring[cons]; in bnx2_reuse_rx_skb_pages()
2970 cons_bd = &rxr->rx_pg_desc_ring[BNX2_RX_RING(cons)] in bnx2_reuse_rx_skb_pages()
2972 prod_bd = &rxr->rx_pg_desc_ring[BNX2_RX_RING(prod)] in bnx2_reuse_rx_skb_pages()
2976 prod_rx_pg->page = cons_rx_pg->page; in bnx2_reuse_rx_skb_pages()
2977 cons_rx_pg->page = NULL; in bnx2_reuse_rx_skb_pages()
2981 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi; in bnx2_reuse_rx_skb_pages()
2982 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo; in bnx2_reuse_rx_skb_pages()
2988 rxr->rx_pg_prod = hw_prod; in bnx2_reuse_rx_skb_pages()
2989 rxr->rx_pg_cons = cons; in bnx2_reuse_rx_skb_pages()
2999 cons_rx_buf = &rxr->rx_buf_ring[cons]; in bnx2_reuse_rx_data()
3000 prod_rx_buf = &rxr->rx_buf_ring[prod]; in bnx2_reuse_rx_data()
3002 dma_sync_single_for_device(&bp->pdev->dev, in bnx2_reuse_rx_data()
3006 rxr->rx_prod_bseq += bp->rx_buf_use_size; in bnx2_reuse_rx_data()
3008 prod_rx_buf->data = data; in bnx2_reuse_rx_data()
3016 cons_bd = &rxr->rx_desc_ring[BNX2_RX_RING(cons)][BNX2_RX_IDX(cons)]; in bnx2_reuse_rx_data()
3017 prod_bd = &rxr->rx_desc_ring[BNX2_RX_RING(prod)][BNX2_RX_IDX(prod)]; in bnx2_reuse_rx_data()
3018 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi; in bnx2_reuse_rx_data()
3019 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo; in bnx2_reuse_rx_data()
3037 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT; in bnx2_rx_skb()
3044 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size, in bnx2_rx_skb()
3051 skb_reserve(skb, ((u8 *)get_l2_fhdr(data) - data) + BNX2_RX_OFFSET); in bnx2_rx_skb()
3058 u16 pg_cons = rxr->rx_pg_cons; in bnx2_rx_skb()
3059 u16 pg_prod = rxr->rx_pg_prod; in bnx2_rx_skb()
3061 frag_size = len + 4 - hdr_len; in bnx2_rx_skb()
3070 unsigned int tail = 4 - frag_len; in bnx2_rx_skb()
3072 rxr->rx_pg_cons = pg_cons; in bnx2_rx_skb()
3073 rxr->rx_pg_prod = pg_prod; in bnx2_rx_skb()
3075 pages - i); in bnx2_rx_skb()
3076 skb->len -= tail; in bnx2_rx_skb()
3078 skb->tail -= tail; in bnx2_rx_skb()
3081 &skb_shinfo(skb)->frags[i - 1]; in bnx2_rx_skb()
3083 skb->data_len -= tail; in bnx2_rx_skb()
3087 rx_pg = &rxr->rx_pg_ring[pg_cons]; in bnx2_rx_skb()
3093 if (i == pages - 1) in bnx2_rx_skb()
3094 frag_len -= 4; in bnx2_rx_skb()
3096 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len); in bnx2_rx_skb()
3097 rx_pg->page = NULL; in bnx2_rx_skb()
3103 rxr->rx_pg_cons = pg_cons; in bnx2_rx_skb()
3104 rxr->rx_pg_prod = pg_prod; in bnx2_rx_skb()
3106 pages - i); in bnx2_rx_skb()
3110 dma_unmap_page(&bp->pdev->dev, mapping_old, in bnx2_rx_skb()
3113 frag_size -= frag_len; in bnx2_rx_skb()
3114 skb->data_len += frag_len; in bnx2_rx_skb()
3115 skb->truesize += PAGE_SIZE; in bnx2_rx_skb()
3116 skb->len += frag_len; in bnx2_rx_skb()
3121 rxr->rx_pg_prod = pg_prod; in bnx2_rx_skb()
3122 rxr->rx_pg_cons = pg_cons; in bnx2_rx_skb()
3132 cons = READ_ONCE(*bnapi->hw_rx_cons_ptr); in bnx2_get_hw_rx_cons()
3142 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; in bnx2_rx_int()
3151 sw_cons = rxr->rx_cons; in bnx2_rx_int()
3152 sw_prod = rxr->rx_prod; in bnx2_rx_int()
3170 rx_buf = &rxr->rx_buf_ring[sw_ring_cons]; in bnx2_rx_int()
3171 data = rx_buf->data; in bnx2_rx_int()
3172 rx_buf->data = NULL; in bnx2_rx_int()
3179 dma_sync_single_for_cpu(&bp->pdev->dev, dma_addr, in bnx2_rx_int()
3184 next_rx_buf = &rxr->rx_buf_ring[next_ring_idx]; in bnx2_rx_int()
3185 prefetch(get_l2_fhdr(next_rx_buf->data)); in bnx2_rx_int()
3187 len = rx_hdr->l2_fhdr_pkt_len; in bnx2_rx_int()
3188 status = rx_hdr->l2_fhdr_status; in bnx2_rx_int()
3192 hdr_len = rx_hdr->l2_fhdr_ip_xsum; in bnx2_rx_int()
3194 } else if (len > bp->rx_jumbo_thresh) { in bnx2_rx_int()
3195 hdr_len = bp->rx_jumbo_thresh; in bnx2_rx_int()
3210 pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT; in bnx2_rx_int()
3217 len -= 4; in bnx2_rx_int()
3219 if (len <= bp->rx_copy_thresh) { in bnx2_rx_int()
3220 skb = netdev_alloc_skb(bp->dev, len + 6); in bnx2_rx_int()
3228 memcpy(skb->data, in bnx2_rx_int()
3229 (u8 *)rx_hdr + BNX2_RX_OFFSET - 6, in bnx2_rx_int()
3244 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) in bnx2_rx_int()
3245 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), rx_hdr->l2_fhdr_vlan_tag); in bnx2_rx_int()
3247 skb->protocol = eth_type_trans(skb, bp->dev); in bnx2_rx_int()
3249 if (len > (bp->dev->mtu + ETH_HLEN) && in bnx2_rx_int()
3250 skb->protocol != htons(0x8100) && in bnx2_rx_int()
3251 skb->protocol != htons(ETH_P_8021AD)) { in bnx2_rx_int()
3259 if ((bp->dev->features & NETIF_F_RXCSUM) && in bnx2_rx_int()
3265 skb->ip_summed = CHECKSUM_UNNECESSARY; in bnx2_rx_int()
3267 if ((bp->dev->features & NETIF_F_RXHASH) && in bnx2_rx_int()
3270 skb_set_hash(skb, rx_hdr->l2_fhdr_hash, in bnx2_rx_int()
3273 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]); in bnx2_rx_int()
3274 napi_gro_receive(&bnapi->napi, skb); in bnx2_rx_int()
3290 rxr->rx_cons = sw_cons; in bnx2_rx_int()
3291 rxr->rx_prod = sw_prod; in bnx2_rx_int()
3294 BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod); in bnx2_rx_int()
3296 BNX2_WR16(bp, rxr->rx_bidx_addr, sw_prod); in bnx2_rx_int()
3298 BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq); in bnx2_rx_int()
3304 /* MSI ISR - The only difference between this and the INTx ISR
3311 struct bnx2 *bp = bnapi->bp; in bnx2_msi()
3313 prefetch(bnapi->status_blk.msi); in bnx2_msi()
3319 if (unlikely(atomic_read(&bp->intr_sem) != 0)) in bnx2_msi()
3322 napi_schedule(&bnapi->napi); in bnx2_msi()
3331 struct bnx2 *bp = bnapi->bp; in bnx2_msi_1shot()
3333 prefetch(bnapi->status_blk.msi); in bnx2_msi_1shot()
3336 if (unlikely(atomic_read(&bp->intr_sem) != 0)) in bnx2_msi_1shot()
3339 napi_schedule(&bnapi->napi); in bnx2_msi_1shot()
3348 struct bnx2 *bp = bnapi->bp; in bnx2_interrupt()
3349 struct status_block *sblk = bnapi->status_blk.msi; in bnx2_interrupt()
3357 if ((sblk->status_idx == bnapi->last_status_idx) && in bnx2_interrupt()
3372 if (unlikely(atomic_read(&bp->intr_sem) != 0)) in bnx2_interrupt()
3375 if (napi_schedule_prep(&bnapi->napi)) { in bnx2_interrupt()
3376 bnapi->last_status_idx = sblk->status_idx; in bnx2_interrupt()
3377 __napi_schedule(&bnapi->napi); in bnx2_interrupt()
3386 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; in bnx2_has_fast_work()
3387 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; in bnx2_has_fast_work()
3389 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) || in bnx2_has_fast_work()
3390 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)) in bnx2_has_fast_work()
3401 struct status_block *sblk = bnapi->status_blk.msi; in bnx2_has_work()
3407 if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx)) in bnx2_has_work()
3411 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) != in bnx2_has_work()
3412 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS)) in bnx2_has_work()
3421 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; in bnx2_chk_missed_msi()
3429 if (bnapi->last_status_idx == bp->idle_chk_status_idx) { in bnx2_chk_missed_msi()
3433 bnx2_msi(bp->irq_tbl[0].vector, bnapi); in bnx2_chk_missed_msi()
3437 bp->idle_chk_status_idx = bnapi->last_status_idx; in bnx2_chk_missed_msi()
3445 if (!bnapi->cnic_present) in bnx2_poll_cnic()
3449 c_ops = rcu_dereference(bp->cnic_ops); in bnx2_poll_cnic()
3451 bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data, in bnx2_poll_cnic()
3452 bnapi->status_blk.msi); in bnx2_poll_cnic()
3459 struct status_block *sblk = bnapi->status_blk.msi; in bnx2_poll_link()
3460 u32 status_attn_bits = sblk->status_attn_bits; in bnx2_poll_link()
3461 u32 status_attn_bits_ack = sblk->status_attn_bits_ack; in bnx2_poll_link()
3472 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); in bnx2_poll_link()
3480 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; in bnx2_poll_work()
3481 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; in bnx2_poll_work()
3483 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons) in bnx2_poll_work()
3486 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) in bnx2_poll_work()
3487 work_done += bnx2_rx_int(bp, bnapi, budget - work_done); in bnx2_poll_work()
3495 struct bnx2 *bp = bnapi->bp; in bnx2_poll_msix()
3497 struct status_block_msix *sblk = bnapi->status_blk.msix; in bnx2_poll_msix()
3504 bnapi->last_status_idx = sblk->status_idx; in bnx2_poll_msix()
3510 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | in bnx2_poll_msix()
3512 bnapi->last_status_idx); in bnx2_poll_msix()
3522 struct bnx2 *bp = bnapi->bp; in bnx2_poll()
3524 struct status_block *sblk = bnapi->status_blk.msi; in bnx2_poll()
3535 /* bnapi->last_status_idx is used below to tell the hw how in bnx2_poll()
3539 bnapi->last_status_idx = sblk->status_idx; in bnx2_poll()
3547 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) { in bnx2_poll()
3550 bnapi->last_status_idx); in bnx2_poll()
3556 bnapi->last_status_idx); in bnx2_poll()
3560 bnapi->last_status_idx); in bnx2_poll()
3582 spin_lock_bh(&bp->phy_lock); in bnx2_set_rx_mode()
3584 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS | in bnx2_set_rx_mode()
3587 if (!(dev->features & NETIF_F_HW_VLAN_CTAG_RX) && in bnx2_set_rx_mode()
3588 (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)) in bnx2_set_rx_mode()
3590 if (dev->flags & IFF_PROMISC) { in bnx2_set_rx_mode()
3596 else if (dev->flags & IFF_ALLMULTI) { in bnx2_set_rx_mode()
3613 crc = ether_crc_le(ETH_ALEN, ha->addr); in bnx2_set_rx_mode()
3632 } else if (!(dev->flags & IFF_PROMISC)) { in bnx2_set_rx_mode()
3636 bnx2_set_mac_addr(bp, ha->addr, in bnx2_set_rx_mode()
3645 if (rx_mode != bp->rx_mode) { in bnx2_set_rx_mode()
3646 bp->rx_mode = rx_mode; in bnx2_set_rx_mode()
3654 spin_unlock_bh(&bp->phy_lock); in bnx2_set_rx_mode()
3662 u32 offset = be32_to_cpu(section->offset); in check_fw_section()
3663 u32 len = be32_to_cpu(section->len); in check_fw_section()
3665 if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3) in check_fw_section()
3666 return -EINVAL; in check_fw_section()
3667 if ((non_empty && len == 0) || len > fw->size - offset || in check_fw_section()
3668 len & (alignment - 1)) in check_fw_section()
3669 return -EINVAL; in check_fw_section()
3677 if (check_fw_section(fw, &entry->text, 4, true) || in check_mips_fw_entry()
3678 check_fw_section(fw, &entry->data, 4, false) || in check_mips_fw_entry()
3679 check_fw_section(fw, &entry->rodata, 4, false)) in check_mips_fw_entry()
3680 return -EINVAL; in check_mips_fw_entry()
3686 if (bp->rv2p_firmware) { in bnx2_release_firmware()
3687 release_firmware(bp->mips_firmware); in bnx2_release_firmware()
3688 release_firmware(bp->rv2p_firmware); in bnx2_release_firmware()
3689 bp->rv2p_firmware = NULL; in bnx2_release_firmware()
3712 rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev); in bnx2_request_uncached_firmware()
3718 rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev); in bnx2_request_uncached_firmware()
3723 mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data; in bnx2_request_uncached_firmware()
3724 rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data; in bnx2_request_uncached_firmware()
3725 if (bp->mips_firmware->size < sizeof(*mips_fw) || in bnx2_request_uncached_firmware()
3726 check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) || in bnx2_request_uncached_firmware()
3727 check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) || in bnx2_request_uncached_firmware()
3728 check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) || in bnx2_request_uncached_firmware()
3729 check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) || in bnx2_request_uncached_firmware()
3730 check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) { in bnx2_request_uncached_firmware()
3732 rc = -EINVAL; in bnx2_request_uncached_firmware()
3735 if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) || in bnx2_request_uncached_firmware()
3736 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) || in bnx2_request_uncached_firmware()
3737 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) { in bnx2_request_uncached_firmware()
3739 rc = -EINVAL; in bnx2_request_uncached_firmware()
3746 release_firmware(bp->rv2p_firmware); in bnx2_request_uncached_firmware()
3747 bp->rv2p_firmware = NULL; in bnx2_request_uncached_firmware()
3749 release_firmware(bp->mips_firmware); in bnx2_request_uncached_firmware()
3755 return bp->rv2p_firmware ? 0 : bnx2_request_uncached_firmware(bp); in bnx2_request_firmware()
3779 rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len); in load_rv2p_fw()
3780 file_offset = be32_to_cpu(fw_entry->rv2p.offset); in load_rv2p_fw()
3782 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset); in load_rv2p_fw()
3802 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset); in load_rv2p_fw()
3806 loc = be32_to_cpu(fw_entry->fixup[i]); in load_rv2p_fw()
3808 code = be32_to_cpu(*(rv2p_code + loc - 1)); in load_rv2p_fw()
3819 /* Reset the processor, un-stall is done later. */ in load_rv2p_fw()
3840 val = bnx2_reg_rd_ind(bp, cpu_reg->mode); in load_cpu_fw()
3841 val |= cpu_reg->mode_value_halt; in load_cpu_fw()
3842 bnx2_reg_wr_ind(bp, cpu_reg->mode, val); in load_cpu_fw()
3843 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear); in load_cpu_fw()
3846 addr = be32_to_cpu(fw_entry->text.addr); in load_cpu_fw()
3847 len = be32_to_cpu(fw_entry->text.len); in load_cpu_fw()
3848 file_offset = be32_to_cpu(fw_entry->text.offset); in load_cpu_fw()
3849 data = (__be32 *)(bp->mips_firmware->data + file_offset); in load_cpu_fw()
3851 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base); in load_cpu_fw()
3860 addr = be32_to_cpu(fw_entry->data.addr); in load_cpu_fw()
3861 len = be32_to_cpu(fw_entry->data.len); in load_cpu_fw()
3862 file_offset = be32_to_cpu(fw_entry->data.offset); in load_cpu_fw()
3863 data = (__be32 *)(bp->mips_firmware->data + file_offset); in load_cpu_fw()
3865 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base); in load_cpu_fw()
3873 /* Load the Read-Only area. */ in load_cpu_fw()
3874 addr = be32_to_cpu(fw_entry->rodata.addr); in load_cpu_fw()
3875 len = be32_to_cpu(fw_entry->rodata.len); in load_cpu_fw()
3876 file_offset = be32_to_cpu(fw_entry->rodata.offset); in load_cpu_fw()
3877 data = (__be32 *)(bp->mips_firmware->data + file_offset); in load_cpu_fw()
3879 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base); in load_cpu_fw()
3887 /* Clear the pre-fetch instruction. */ in load_cpu_fw()
3888 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0); in load_cpu_fw()
3890 val = be32_to_cpu(fw_entry->start_addr); in load_cpu_fw()
3891 bnx2_reg_wr_ind(bp, cpu_reg->pc, val); in load_cpu_fw()
3894 val = bnx2_reg_rd_ind(bp, cpu_reg->mode); in load_cpu_fw()
3895 val &= ~cpu_reg->mode_value_halt; in load_cpu_fw()
3896 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear); in load_cpu_fw()
3897 bnx2_reg_wr_ind(bp, cpu_reg->mode, val); in load_cpu_fw()
3904 (const struct bnx2_mips_fw_file *) bp->mips_firmware->data; in bnx2_init_cpus()
3906 (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data; in bnx2_init_cpus()
3909 load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1); in bnx2_init_cpus()
3910 load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2); in bnx2_init_cpus()
3913 load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp); in bnx2_init_cpus()
3916 load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp); in bnx2_init_cpus()
3918 /* Initialize the TX Patch-up Processor. */ in bnx2_init_cpus()
3919 load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat); in bnx2_init_cpus()
3922 load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com); in bnx2_init_cpus()
3925 load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp); in bnx2_init_cpus()
3934 if (bp->wol) { in bnx2_setup_wol()
3938 autoneg = bp->autoneg; in bnx2_setup_wol()
3939 advertising = bp->advertising; in bnx2_setup_wol()
3941 if (bp->phy_port == PORT_TP) { in bnx2_setup_wol()
3942 bp->autoneg = AUTONEG_SPEED; in bnx2_setup_wol()
3943 bp->advertising = ADVERTISED_10baseT_Half | in bnx2_setup_wol()
3950 spin_lock_bh(&bp->phy_lock); in bnx2_setup_wol()
3951 bnx2_setup_phy(bp, bp->phy_port); in bnx2_setup_wol()
3952 spin_unlock_bh(&bp->phy_lock); in bnx2_setup_wol()
3954 bp->autoneg = autoneg; in bnx2_setup_wol()
3955 bp->advertising = advertising; in bnx2_setup_wol()
3957 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0); in bnx2_setup_wol()
3966 if (bp->phy_port == PORT_TP) { in bnx2_setup_wol()
3970 if (bp->line_speed == SPEED_2500) in bnx2_setup_wol()
4003 if (!(bp->flags & BNX2_FLAG_NO_WOL)) { in bnx2_setup_wol()
4007 if (bp->fw_last_msg || BNX2_CHIP(bp) != BNX2_CHIP_5709) { in bnx2_setup_wol()
4030 pci_enable_wake(bp->pdev, PCI_D0, false); in bnx2_set_power_state()
4031 pci_set_power_state(bp->pdev, PCI_D0); in bnx2_set_power_state()
4045 pci_wake_from_d3(bp->pdev, bp->wol); in bnx2_set_power_state()
4049 if (bp->wol) in bnx2_set_power_state()
4050 pci_set_power_state(bp->pdev, PCI_D3hot); in bnx2_set_power_state()
4054 if (!bp->fw_last_msg && BNX2_CHIP(bp) == BNX2_CHIP_5709) { in bnx2_set_power_state()
4066 pci_set_power_state(bp->pdev, PCI_D3hot); in bnx2_set_power_state()
4074 return -EINVAL; in bnx2_set_power_state()
4096 return -EBUSY; in bnx2_acquire_nvram_lock()
4119 return -EBUSY; in bnx2_release_nvram_lock()
4133 if (bp->flash_info->flags & BNX2_NV_WREN) { in bnx2_enable_nvram_write()
4149 return -EBUSY; in bnx2_enable_nvram_write()
4193 if (bp->flash_info->flags & BNX2_NV_BUFFERED) in bnx2_nvram_erase_page()
4222 return -EBUSY; in bnx2_nvram_erase_page()
4237 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) { in bnx2_nvram_read_dword()
4238 offset = ((offset / bp->flash_info->page_size) << in bnx2_nvram_read_dword()
4239 bp->flash_info->page_bits) + in bnx2_nvram_read_dword()
4240 (offset % bp->flash_info->page_size); in bnx2_nvram_read_dword()
4266 return -EBUSY; in bnx2_nvram_read_dword()
4283 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) { in bnx2_nvram_write_dword()
4284 offset = ((offset / bp->flash_info->page_size) << in bnx2_nvram_write_dword()
4285 bp->flash_info->page_bits) + in bnx2_nvram_write_dword()
4286 (offset % bp->flash_info->page_size); in bnx2_nvram_write_dword()
4311 return -EBUSY; in bnx2_nvram_write_dword()
4324 bp->flash_info = &flash_5709; in bnx2_init_nvram()
4339 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { in bnx2_init_nvram()
4340 bp->flash_info = flash; in bnx2_init_nvram()
4357 if ((val & mask) == (flash->strapping & mask)) { in bnx2_init_nvram()
4358 bp->flash_info = flash; in bnx2_init_nvram()
4368 BNX2_WR(bp, BNX2_NVM_CFG1, flash->config1); in bnx2_init_nvram()
4369 BNX2_WR(bp, BNX2_NVM_CFG2, flash->config2); in bnx2_init_nvram()
4370 BNX2_WR(bp, BNX2_NVM_CFG3, flash->config3); in bnx2_init_nvram()
4371 BNX2_WR(bp, BNX2_NVM_WRITE1, flash->write1); in bnx2_init_nvram()
4383 bp->flash_info = NULL; in bnx2_init_nvram()
4385 return -ENODEV; in bnx2_init_nvram()
4392 bp->flash_size = val; in bnx2_init_nvram()
4394 bp->flash_size = bp->flash_info->total_size; in bnx2_init_nvram()
4404 u32 cmd_flags, offset32, len32, extra; in bnx2_nvram_read() local
4418 extra = 0; in bnx2_nvram_read()
4427 pre_len = 4 - (offset & 3); in bnx2_nvram_read()
4447 len32 -= pre_len; in bnx2_nvram_read()
4450 extra = 4 - (len32 & 3); in bnx2_nvram_read()
4465 memcpy(ret_buf, buf, 4 - extra); in bnx2_nvram_read()
4481 len32 -= 4; in bnx2_nvram_read()
4489 len32 -= 4; in bnx2_nvram_read()
4498 memcpy(ret_buf, buf, 4 - extra); in bnx2_nvram_read()
4533 align_end = 4 - (len32 & 3); in bnx2_nvram_write()
4535 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4))) in bnx2_nvram_write()
4542 return -ENOMEM; in bnx2_nvram_write()
4547 memcpy(align_buf + len32 - 4, end, 4); in bnx2_nvram_write()
4553 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { in bnx2_nvram_write()
4556 rc = -ENOMEM; in bnx2_nvram_write()
4569 page_start -= (page_start % bp->flash_info->page_size); in bnx2_nvram_write()
4571 page_end = page_start + bp->flash_info->page_size; in bnx2_nvram_write()
4586 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { in bnx2_nvram_write()
4590 * (non-buffer flash only) */ in bnx2_nvram_write()
4591 for (j = 0; j < bp->flash_info->page_size; j += 4) { in bnx2_nvram_write()
4592 if (j == (bp->flash_info->page_size - 4)) { in bnx2_nvram_write()
4607 /* Enable writes to flash interface (unlock write-protect) */ in bnx2_nvram_write()
4614 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { in bnx2_nvram_write()
4619 /* Re-enable the write again for the actual write */ in bnx2_nvram_write()
4637 if ((addr == page_end - 4) || in bnx2_nvram_write()
4638 ((bp->flash_info->flags & BNX2_NV_BUFFERED) && in bnx2_nvram_write()
4639 (addr == data_end - 4))) { in bnx2_nvram_write()
4655 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { in bnx2_nvram_write()
4659 if (addr == page_end-4) { in bnx2_nvram_write()
4672 /* Disable writes to flash interface (lock write-protect) */ in bnx2_nvram_write()
4680 written += data_end - data_start; in bnx2_nvram_write()
4694 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP; in bnx2_init_fw_cap()
4695 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN; in bnx2_init_fw_cap()
4697 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE)) in bnx2_init_fw_cap()
4698 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN; in bnx2_init_fw_cap()
4705 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN; in bnx2_init_fw_cap()
4709 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && in bnx2_init_fw_cap()
4713 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP; in bnx2_init_fw_cap()
4717 bp->phy_port = PORT_FIBRE; in bnx2_init_fw_cap()
4719 bp->phy_port = PORT_TP; in bnx2_init_fw_cap()
4725 if (netif_running(bp->dev) && sig) in bnx2_init_fw_cap()
4836 return -EBUSY; in bnx2_reset_chip()
4844 return -ENODEV; in bnx2_reset_chip()
4852 spin_lock_bh(&bp->phy_lock); in bnx2_reset_chip()
4853 old_port = bp->phy_port; in bnx2_reset_chip()
4855 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) && in bnx2_reset_chip()
4856 old_port != bp->phy_port) in bnx2_reset_chip()
4858 spin_unlock_bh(&bp->phy_lock); in bnx2_reset_chip()
4869 if (bp->flags & BNX2_FLAG_USING_MSIX) { in bnx2_reset_chip()
4899 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133)) in bnx2_init_chip()
4904 !(bp->flags & BNX2_FLAG_PCIX)) in bnx2_init_chip()
4915 if (bp->flags & BNX2_FLAG_PCIX) { in bnx2_init_chip()
4918 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD, in bnx2_init_chip()
4920 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD, in bnx2_init_chip()
4942 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0); in bnx2_init_chip()
4959 val = (BNX2_PAGE_BITS - 8) << 24; in bnx2_init_chip()
4965 val |= (BNX2_PAGE_BITS - 8) << 24 | 0x40; in bnx2_init_chip()
4968 val = bp->mac_addr[0] + in bnx2_init_chip()
4969 (bp->mac_addr[1] << 8) + in bnx2_init_chip()
4970 (bp->mac_addr[2] << 16) + in bnx2_init_chip()
4971 bp->mac_addr[3] + in bnx2_init_chip()
4972 (bp->mac_addr[4] << 8) + in bnx2_init_chip()
4973 (bp->mac_addr[5] << 16); in bnx2_init_chip()
4977 mtu = bp->dev->mtu; in bnx2_init_chip()
4990 memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size); in bnx2_init_chip()
4992 bp->bnx2_napi[i].last_status_idx = 0; in bnx2_init_chip()
4994 bp->idle_chk_status_idx = 0xffff; in bnx2_init_chip()
5000 (u64) bp->status_blk_mapping & 0xffffffff); in bnx2_init_chip()
5001 BNX2_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32); in bnx2_init_chip()
5004 (u64) bp->stats_blk_mapping & 0xffffffff); in bnx2_init_chip()
5006 (u64) bp->stats_blk_mapping >> 32); in bnx2_init_chip()
5009 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip); in bnx2_init_chip()
5012 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip); in bnx2_init_chip()
5015 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip); in bnx2_init_chip()
5017 BNX2_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks); in bnx2_init_chip()
5019 BNX2_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks); in bnx2_init_chip()
5022 (bp->com_ticks_int << 16) | bp->com_ticks); in bnx2_init_chip()
5025 (bp->cmd_ticks_int << 16) | bp->cmd_ticks); in bnx2_init_chip()
5027 if (bp->flags & BNX2_FLAG_BROKEN_STATS) in bnx2_init_chip()
5030 BNX2_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks); in bnx2_init_chip()
5040 if (bp->flags & BNX2_FLAG_USING_MSIX) { in bnx2_init_chip()
5047 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI) in bnx2_init_chip()
5052 if (bp->rx_ticks < 25) in bnx2_init_chip()
5057 for (i = 1; i < bp->irq_nvecs; i++) { in bnx2_init_chip()
5058 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) + in bnx2_init_chip()
5067 (bp->tx_quick_cons_trip_int << 16) | in bnx2_init_chip()
5068 bp->tx_quick_cons_trip); in bnx2_init_chip()
5071 (bp->tx_ticks_int << 16) | bp->tx_ticks); in bnx2_init_chip()
5074 (bp->rx_quick_cons_trip_int << 16) | in bnx2_init_chip()
5075 bp->rx_quick_cons_trip); in bnx2_init_chip()
5078 (bp->rx_ticks_int << 16) | bp->rx_ticks); in bnx2_init_chip()
5087 bnx2_set_rx_mode(bp->dev); in bnx2_init_chip()
5102 bp->hc_cmd = BNX2_RD(bp, BNX2_HC_COMMAND); in bnx2_init_chip()
5116 bnapi = &bp->bnx2_napi[i]; in bnx2_clear_ring_states()
5117 txr = &bnapi->tx_ring; in bnx2_clear_ring_states()
5118 rxr = &bnapi->rx_ring; in bnx2_clear_ring_states()
5120 txr->tx_cons = 0; in bnx2_clear_ring_states()
5121 txr->hw_tx_cons = 0; in bnx2_clear_ring_states()
5122 rxr->rx_prod_bseq = 0; in bnx2_clear_ring_states()
5123 rxr->rx_prod = 0; in bnx2_clear_ring_states()
5124 rxr->rx_cons = 0; in bnx2_clear_ring_states()
5125 rxr->rx_pg_prod = 0; in bnx2_clear_ring_states()
5126 rxr->rx_pg_cons = 0; in bnx2_clear_ring_states()
5153 val = (u64) txr->tx_desc_mapping >> 32; in bnx2_init_tx_context()
5156 val = (u64) txr->tx_desc_mapping & 0xffffffff; in bnx2_init_tx_context()
5168 bnapi = &bp->bnx2_napi[ring_num]; in bnx2_init_tx_ring()
5169 txr = &bnapi->tx_ring; in bnx2_init_tx_ring()
5174 cid = TX_TSS_CID + ring_num - 1; in bnx2_init_tx_ring()
5176 bp->tx_wake_thresh = bp->tx_ring_size / 2; in bnx2_init_tx_ring()
5178 txbd = &txr->tx_desc_ring[BNX2_MAX_TX_DESC_CNT]; in bnx2_init_tx_ring()
5180 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32; in bnx2_init_tx_ring()
5181 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff; in bnx2_init_tx_ring()
5183 txr->tx_prod = 0; in bnx2_init_tx_ring()
5184 txr->tx_prod_bseq = 0; in bnx2_init_tx_ring()
5186 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX; in bnx2_init_tx_ring()
5187 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ; in bnx2_init_tx_ring()
5204 rxbd->rx_bd_len = buf_size; in bnx2_init_rxbd_rings()
5205 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END; in bnx2_init_rxbd_rings()
5207 if (i == (num_rings - 1)) in bnx2_init_rxbd_rings()
5211 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32; in bnx2_init_rxbd_rings()
5212 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff; in bnx2_init_rxbd_rings()
5222 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num]; in bnx2_init_rx_ring()
5223 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; in bnx2_init_rx_ring()
5228 cid = RX_RSS_CID + ring_num - 1; in bnx2_init_rx_ring()
5232 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping, in bnx2_init_rx_ring()
5233 bp->rx_buf_use_size, bp->rx_max_ring); in bnx2_init_rx_ring()
5243 if (bp->rx_pg_ring_size) { in bnx2_init_rx_ring()
5244 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring, in bnx2_init_rx_ring()
5245 rxr->rx_pg_desc_mapping, in bnx2_init_rx_ring()
5246 PAGE_SIZE, bp->rx_max_pg_ring); in bnx2_init_rx_ring()
5247 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE; in bnx2_init_rx_ring()
5250 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num); in bnx2_init_rx_ring()
5252 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32; in bnx2_init_rx_ring()
5255 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff; in bnx2_init_rx_ring()
5262 val = (u64) rxr->rx_desc_mapping[0] >> 32; in bnx2_init_rx_ring()
5265 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff; in bnx2_init_rx_ring()
5268 ring_prod = prod = rxr->rx_pg_prod; in bnx2_init_rx_ring()
5269 for (i = 0; i < bp->rx_pg_ring_size; i++) { in bnx2_init_rx_ring()
5271 netdev_warn(bp->dev, "init'ed rx page ring %d with %d/%d pages only\n", in bnx2_init_rx_ring()
5272 ring_num, i, bp->rx_pg_ring_size); in bnx2_init_rx_ring()
5278 rxr->rx_pg_prod = prod; in bnx2_init_rx_ring()
5280 ring_prod = prod = rxr->rx_prod; in bnx2_init_rx_ring()
5281 for (i = 0; i < bp->rx_ring_size; i++) { in bnx2_init_rx_ring()
5283 netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n", in bnx2_init_rx_ring()
5284 ring_num, i, bp->rx_ring_size); in bnx2_init_rx_ring()
5290 rxr->rx_prod = prod; in bnx2_init_rx_ring()
5292 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX; in bnx2_init_rx_ring()
5293 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ; in bnx2_init_rx_ring()
5294 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX; in bnx2_init_rx_ring()
5296 BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod); in bnx2_init_rx_ring()
5297 BNX2_WR16(bp, rxr->rx_bidx_addr, prod); in bnx2_init_rx_ring()
5299 BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq); in bnx2_init_rx_ring()
5311 for (i = 0; i < bp->num_tx_rings; i++) in bnx2_init_all_rings()
5314 if (bp->num_tx_rings > 1) in bnx2_init_all_rings()
5315 BNX2_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) | in bnx2_init_all_rings()
5321 for (i = 0; i < bp->num_rx_rings; i++) in bnx2_init_all_rings()
5324 if (bp->num_rx_rings > 1) { in bnx2_init_all_rings()
5330 tbl_32 |= (i % (bp->num_rx_rings - 1)) << shift; in bnx2_init_all_rings()
5354 ring_size -= BNX2_MAX_RX_DESC_CNT; in bnx2_find_max_ring()
5374 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8; in bnx2_set_rx_ring_size()
5379 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH; in bnx2_set_rx_ring_size()
5380 bp->rx_pg_ring_size = 0; in bnx2_set_rx_ring_size()
5381 bp->rx_max_pg_ring = 0; in bnx2_set_rx_ring_size()
5382 bp->rx_max_pg_ring_idx = 0; in bnx2_set_rx_ring_size()
5383 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) { in bnx2_set_rx_ring_size()
5384 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT; in bnx2_set_rx_ring_size()
5390 bp->rx_pg_ring_size = jumbo_size; in bnx2_set_rx_ring_size()
5391 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size, in bnx2_set_rx_ring_size()
5393 bp->rx_max_pg_ring_idx = in bnx2_set_rx_ring_size()
5394 (bp->rx_max_pg_ring * BNX2_RX_DESC_CNT) - 1; in bnx2_set_rx_ring_size()
5396 bp->rx_copy_thresh = 0; in bnx2_set_rx_ring_size()
5399 bp->rx_buf_use_size = rx_size; in bnx2_set_rx_ring_size()
5401 bp->rx_buf_size = kmalloc_size_roundup( in bnx2_set_rx_ring_size()
5402 SKB_DATA_ALIGN(bp->rx_buf_use_size + BNX2_RX_ALIGN) + in bnx2_set_rx_ring_size()
5404 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET; in bnx2_set_rx_ring_size()
5405 bp->rx_ring_size = size; in bnx2_set_rx_ring_size()
5406 bp->rx_max_ring = bnx2_find_max_ring(size, BNX2_MAX_RX_RINGS); in bnx2_set_rx_ring_size()
5407 bp->rx_max_ring_idx = (bp->rx_max_ring * BNX2_RX_DESC_CNT) - 1; in bnx2_set_rx_ring_size()
5415 for (i = 0; i < bp->num_tx_rings; i++) { in bnx2_free_tx_skbs()
5416 struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; in bnx2_free_tx_skbs()
5417 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; in bnx2_free_tx_skbs()
5420 if (!txr->tx_buf_ring) in bnx2_free_tx_skbs()
5424 struct bnx2_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j]; in bnx2_free_tx_skbs()
5425 struct sk_buff *skb = tx_buf->skb; in bnx2_free_tx_skbs()
5433 dma_unmap_single(&bp->pdev->dev, in bnx2_free_tx_skbs()
5438 tx_buf->skb = NULL; in bnx2_free_tx_skbs()
5440 last = tx_buf->nr_frags; in bnx2_free_tx_skbs()
5443 tx_buf = &txr->tx_buf_ring[BNX2_TX_RING_IDX(j)]; in bnx2_free_tx_skbs()
5444 dma_unmap_page(&bp->pdev->dev, in bnx2_free_tx_skbs()
5446 skb_frag_size(&skb_shinfo(skb)->frags[k]), in bnx2_free_tx_skbs()
5451 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i)); in bnx2_free_tx_skbs()
5460 for (i = 0; i < bp->num_rx_rings; i++) { in bnx2_free_rx_skbs()
5461 struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; in bnx2_free_rx_skbs()
5462 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; in bnx2_free_rx_skbs()
5465 if (!rxr->rx_buf_ring) in bnx2_free_rx_skbs()
5468 for (j = 0; j < bp->rx_max_ring_idx; j++) { in bnx2_free_rx_skbs()
5469 struct bnx2_sw_bd *rx_buf = &rxr->rx_buf_ring[j]; in bnx2_free_rx_skbs()
5470 u8 *data = rx_buf->data; in bnx2_free_rx_skbs()
5475 dma_unmap_single(&bp->pdev->dev, in bnx2_free_rx_skbs()
5477 bp->rx_buf_use_size, in bnx2_free_rx_skbs()
5480 rx_buf->data = NULL; in bnx2_free_rx_skbs()
5484 for (j = 0; j < bp->rx_max_pg_ring_idx; j++) in bnx2_free_rx_skbs()
5521 spin_lock_bh(&bp->phy_lock); in bnx2_init_nic()
5524 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) in bnx2_init_nic()
5526 spin_unlock_bh(&bp->phy_lock); in bnx2_init_nic()
5535 if (bp->flags & BNX2_FLAG_NO_WOL) in bnx2_shutdown_chip()
5537 else if (bp->wol) in bnx2_shutdown_chip()
5681 save_val = readl(bp->regview + offset); in bnx2_test_registers()
5683 writel(0, bp->regview + offset); in bnx2_test_registers()
5685 val = readl(bp->regview + offset); in bnx2_test_registers()
5694 writel(0xffffffff, bp->regview + offset); in bnx2_test_registers()
5696 val = readl(bp->regview + offset); in bnx2_test_registers()
5705 writel(save_val, bp->regview + offset); in bnx2_test_registers()
5709 writel(save_val, bp->regview + offset); in bnx2_test_registers()
5710 ret = -ENODEV; in bnx2_test_registers()
5732 return -ENODEV; in bnx2_do_mem_test()
5796 int ret = -ENODEV; in bnx2_run_loopback()
5797 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi; in bnx2_run_loopback()
5803 txr = &tx_napi->tx_ring; in bnx2_run_loopback()
5804 rxr = &bnapi->rx_ring; in bnx2_run_loopback()
5806 bp->loopback = MAC_LOOPBACK; in bnx2_run_loopback()
5810 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) in bnx2_run_loopback()
5813 bp->loopback = PHY_LOOPBACK; in bnx2_run_loopback()
5817 return -EINVAL; in bnx2_run_loopback()
5819 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4); in bnx2_run_loopback()
5820 skb = netdev_alloc_skb(bp->dev, pkt_size); in bnx2_run_loopback()
5822 return -ENOMEM; in bnx2_run_loopback()
5824 memcpy(packet, bp->dev->dev_addr, ETH_ALEN); in bnx2_run_loopback()
5829 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size, in bnx2_run_loopback()
5831 if (dma_mapping_error(&bp->pdev->dev, map)) { in bnx2_run_loopback()
5833 return -EIO; in bnx2_run_loopback()
5837 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); in bnx2_run_loopback()
5846 txbd = &txr->tx_desc_ring[BNX2_TX_RING_IDX(txr->tx_prod)]; in bnx2_run_loopback()
5848 txbd->tx_bd_haddr_hi = (u64) map >> 32; in bnx2_run_loopback()
5849 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff; in bnx2_run_loopback()
5850 txbd->tx_bd_mss_nbytes = pkt_size; in bnx2_run_loopback()
5851 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END; in bnx2_run_loopback()
5854 txr->tx_prod = BNX2_NEXT_TX_BD(txr->tx_prod); in bnx2_run_loopback()
5855 txr->tx_prod_bseq += pkt_size; in bnx2_run_loopback()
5857 BNX2_WR16(bp, txr->tx_bidx_addr, txr->tx_prod); in bnx2_run_loopback()
5858 BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq); in bnx2_run_loopback()
5863 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); in bnx2_run_loopback()
5869 dma_unmap_single(&bp->pdev->dev, map, pkt_size, DMA_TO_DEVICE); in bnx2_run_loopback()
5872 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod) in bnx2_run_loopback()
5880 rx_buf = &rxr->rx_buf_ring[rx_start_idx]; in bnx2_run_loopback()
5881 data = rx_buf->data; in bnx2_run_loopback()
5886 dma_sync_single_for_cpu(&bp->pdev->dev, in bnx2_run_loopback()
5888 bp->rx_buf_use_size, DMA_FROM_DEVICE); in bnx2_run_loopback()
5890 if (rx_hdr->l2_fhdr_status & in bnx2_run_loopback()
5900 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) { in bnx2_run_loopback()
5913 bp->loopback = 0; in bnx2_run_loopback()
5927 if (!netif_running(bp->dev)) in bnx2_test_loopback()
5931 spin_lock_bh(&bp->phy_lock); in bnx2_test_loopback()
5933 spin_unlock_bh(&bp->phy_lock); in bnx2_test_loopback()
5957 rc = -ENODEV; in bnx2_test_nvram()
5966 rc = -ENODEV; in bnx2_test_nvram()
5972 rc = -ENODEV; in bnx2_test_nvram()
5984 if (!netif_running(bp->dev)) in bnx2_test_link()
5985 return -ENODEV; in bnx2_test_link()
5987 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { in bnx2_test_link()
5988 if (bp->link_up) in bnx2_test_link()
5990 return -ENODEV; in bnx2_test_link()
5992 spin_lock_bh(&bp->phy_lock); in bnx2_test_link()
5994 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); in bnx2_test_link()
5995 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); in bnx2_test_link()
5997 spin_unlock_bh(&bp->phy_lock); in bnx2_test_link()
6002 return -ENODEV; in bnx2_test_link()
6011 if (!netif_running(bp->dev)) in bnx2_test_intr()
6012 return -ENODEV; in bnx2_test_intr()
6016 /* This register is not touched during run-time. */ in bnx2_test_intr()
6017 BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW); in bnx2_test_intr()
6032 return -ENODEV; in bnx2_test_intr()
6041 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL) in bnx2_5706_serdes_has_link()
6072 spin_lock(&bp->phy_lock); in bnx2_5706_serdes_timer()
6073 if (bp->serdes_an_pending) { in bnx2_5706_serdes_timer()
6074 bp->serdes_an_pending--; in bnx2_5706_serdes_timer()
6076 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) { in bnx2_5706_serdes_timer()
6079 bp->current_interval = BNX2_TIMER_INTERVAL; in bnx2_5706_serdes_timer()
6081 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); in bnx2_5706_serdes_timer()
6087 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); in bnx2_5706_serdes_timer()
6088 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT; in bnx2_5706_serdes_timer()
6092 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) && in bnx2_5706_serdes_timer()
6093 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) { in bnx2_5706_serdes_timer()
6101 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); in bnx2_5706_serdes_timer()
6103 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); in bnx2_5706_serdes_timer()
6105 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT; in bnx2_5706_serdes_timer()
6108 bp->current_interval = BNX2_TIMER_INTERVAL; in bnx2_5706_serdes_timer()
6117 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) { in bnx2_5706_serdes_timer()
6118 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) { in bnx2_5706_serdes_timer()
6120 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN; in bnx2_5706_serdes_timer()
6123 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC)) in bnx2_5706_serdes_timer()
6126 spin_unlock(&bp->phy_lock); in bnx2_5706_serdes_timer()
6132 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) in bnx2_5708_serdes_timer()
6135 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) { in bnx2_5708_serdes_timer()
6136 bp->serdes_an_pending = 0; in bnx2_5708_serdes_timer()
6140 spin_lock(&bp->phy_lock); in bnx2_5708_serdes_timer()
6141 if (bp->serdes_an_pending) in bnx2_5708_serdes_timer()
6142 bp->serdes_an_pending--; in bnx2_5708_serdes_timer()
6143 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) { in bnx2_5708_serdes_timer()
6146 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); in bnx2_5708_serdes_timer()
6149 bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT; in bnx2_5708_serdes_timer()
6152 bp->serdes_an_pending = 2; in bnx2_5708_serdes_timer()
6153 bp->current_interval = BNX2_TIMER_INTERVAL; in bnx2_5708_serdes_timer()
6157 bp->current_interval = BNX2_TIMER_INTERVAL; in bnx2_5708_serdes_timer()
6159 spin_unlock(&bp->phy_lock); in bnx2_5708_serdes_timer()
6167 if (!netif_running(bp->dev)) in bnx2_timer()
6170 if (atomic_read(&bp->intr_sem) != 0) in bnx2_timer()
6173 if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) == in bnx2_timer()
6179 bp->stats_blk->stat_FwRxDrop = in bnx2_timer()
6183 if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks) in bnx2_timer()
6184 BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | in bnx2_timer()
6187 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { in bnx2_timer()
6195 mod_timer(&bp->timer, jiffies + bp->current_interval); in bnx2_timer()
6205 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX) in bnx2_request_irq()
6210 for (i = 0; i < bp->irq_nvecs; i++) { in bnx2_request_irq()
6211 irq = &bp->irq_tbl[i]; in bnx2_request_irq()
6212 rc = request_irq(irq->vector, irq->handler, flags, irq->name, in bnx2_request_irq()
6213 &bp->bnx2_napi[i]); in bnx2_request_irq()
6216 irq->requested = 1; in bnx2_request_irq()
6227 for (i = 0; i < bp->irq_nvecs; i++) { in __bnx2_free_irq()
6228 irq = &bp->irq_tbl[i]; in __bnx2_free_irq()
6229 if (irq->requested) in __bnx2_free_irq()
6230 free_irq(irq->vector, &bp->bnx2_napi[i]); in __bnx2_free_irq()
6231 irq->requested = 0; in __bnx2_free_irq()
6240 if (bp->flags & BNX2_FLAG_USING_MSI) in bnx2_free_irq()
6241 pci_disable_msi(bp->pdev); in bnx2_free_irq()
6242 else if (bp->flags & BNX2_FLAG_USING_MSIX) in bnx2_free_irq()
6243 pci_disable_msix(bp->pdev); in bnx2_free_irq()
6245 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI); in bnx2_free_irq()
6253 struct net_device *dev = bp->dev; in bnx2_enable_msix()
6254 const int len = sizeof(bp->irq_tbl[0].name); in bnx2_enable_msix()
6257 BNX2_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1); in bnx2_enable_msix()
6261 /* Need to flush the previous three writes to ensure MSI-X in bnx2_enable_msix()
6274 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, in bnx2_enable_msix()
6281 msix_vecs--; in bnx2_enable_msix()
6283 bp->irq_nvecs = msix_vecs; in bnx2_enable_msix()
6284 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI; in bnx2_enable_msix()
6286 bp->irq_tbl[i].vector = msix_ent[i].vector; in bnx2_enable_msix()
6287 snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i); in bnx2_enable_msix()
6288 bp->irq_tbl[i].handler = bnx2_msi_1shot; in bnx2_enable_msix()
6298 if (!bp->num_req_rx_rings) in bnx2_setup_int_mode()
6299 msix_vecs = max(cpus + 1, bp->num_req_tx_rings); in bnx2_setup_int_mode()
6300 else if (!bp->num_req_tx_rings) in bnx2_setup_int_mode()
6301 msix_vecs = max(cpus, bp->num_req_rx_rings); in bnx2_setup_int_mode()
6303 msix_vecs = max(bp->num_req_rx_rings, bp->num_req_tx_rings); in bnx2_setup_int_mode()
6307 bp->irq_tbl[0].handler = bnx2_interrupt; in bnx2_setup_int_mode()
6308 strcpy(bp->irq_tbl[0].name, bp->dev->name); in bnx2_setup_int_mode()
6309 bp->irq_nvecs = 1; in bnx2_setup_int_mode()
6310 bp->irq_tbl[0].vector = bp->pdev->irq; in bnx2_setup_int_mode()
6312 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi) in bnx2_setup_int_mode()
6315 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi && in bnx2_setup_int_mode()
6316 !(bp->flags & BNX2_FLAG_USING_MSIX)) { in bnx2_setup_int_mode()
6317 if (pci_enable_msi(bp->pdev) == 0) { in bnx2_setup_int_mode()
6318 bp->flags |= BNX2_FLAG_USING_MSI; in bnx2_setup_int_mode()
6320 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI; in bnx2_setup_int_mode()
6321 bp->irq_tbl[0].handler = bnx2_msi_1shot; in bnx2_setup_int_mode()
6323 bp->irq_tbl[0].handler = bnx2_msi; in bnx2_setup_int_mode()
6325 bp->irq_tbl[0].vector = bp->pdev->irq; in bnx2_setup_int_mode()
6329 if (!bp->num_req_tx_rings) in bnx2_setup_int_mode()
6330 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs); in bnx2_setup_int_mode()
6332 bp->num_tx_rings = min(bp->irq_nvecs, bp->num_req_tx_rings); in bnx2_setup_int_mode()
6334 if (!bp->num_req_rx_rings) in bnx2_setup_int_mode()
6335 bp->num_rx_rings = bp->irq_nvecs; in bnx2_setup_int_mode()
6337 bp->num_rx_rings = min(bp->irq_nvecs, bp->num_req_rx_rings); in bnx2_setup_int_mode()
6339 netif_set_real_num_tx_queues(bp->dev, bp->num_tx_rings); in bnx2_setup_int_mode()
6341 return netif_set_real_num_rx_queues(bp->dev, bp->num_rx_rings); in bnx2_setup_int_mode()
6376 mod_timer(&bp->timer, jiffies + bp->current_interval); in bnx2_open()
6378 atomic_set(&bp->intr_sem, 0); in bnx2_open()
6380 memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block)); in bnx2_open()
6384 if (bp->flags & BNX2_FLAG_USING_MSI) { in bnx2_open()
6389 …netdev_warn(bp->dev, "No interrupt was generated using MSI, switching to INTx mode. Please report … in bnx2_open()
6402 del_timer_sync(&bp->timer); in bnx2_open()
6408 if (bp->flags & BNX2_FLAG_USING_MSI) in bnx2_open()
6410 else if (bp->flags & BNX2_FLAG_USING_MSIX) in bnx2_open()
6435 if (!netif_running(bp->dev)) { in bnx2_reset_task()
6442 pci_read_config_word(bp->pdev, PCI_COMMAND, &pcicmd); in bnx2_reset_task()
6445 pci_restore_state(bp->pdev); in bnx2_reset_task()
6446 pci_save_state(bp->pdev); in bnx2_reset_task()
6450 netdev_err(bp->dev, "failed to reset NIC, closing\n"); in bnx2_reset_task()
6452 dev_close(bp->dev); in bnx2_reset_task()
6457 atomic_set(&bp->intr_sem, 1); in bnx2_reset_task()
6469 struct net_device *dev = bp->dev; in bnx2_dump_ftq()
6490 netdev_err(dev, "<--- start FTQ dump --->\n"); in bnx2_dump_ftq()
6505 netdev_err(dev, "<--- end FTQ dump --->\n"); in bnx2_dump_ftq()
6506 netdev_err(dev, "<--- start TBDC dump --->\n"); in bnx2_dump_ftq()
6528 netdev_err(dev, "<--- end TBDC dump --->\n"); in bnx2_dump_ftq()
6534 struct net_device *dev = bp->dev; in bnx2_dump_state()
6537 pci_read_config_dword(bp->pdev, PCI_COMMAND, &val1); in bnx2_dump_state()
6539 atomic_read(&bp->intr_sem), val1); in bnx2_dump_state()
6540 pci_read_config_dword(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &val1); in bnx2_dump_state()
6541 pci_read_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, &val2); in bnx2_dump_state()
6550 if (bp->flags & BNX2_FLAG_USING_MSIX) in bnx2_dump_state()
6565 schedule_work(&bp->reset_task); in bnx2_tx_timeout()
6588 bnapi = &bp->bnx2_napi[i]; in bnx2_start_xmit()
6589 txr = &bnapi->tx_ring; in bnx2_start_xmit()
6593 (skb_shinfo(skb)->nr_frags + 1))) { in bnx2_start_xmit()
6600 prod = txr->tx_prod; in bnx2_start_xmit()
6604 if (skb->ip_summed == CHECKSUM_PARTIAL) { in bnx2_start_xmit()
6613 if ((mss = skb_shinfo(skb)->gso_size)) { in bnx2_start_xmit()
6621 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) { in bnx2_start_xmit()
6622 u32 tcp_off = skb_transport_offset(skb) - in bnx2_start_xmit()
6623 sizeof(struct ipv6hdr) - ETH_HLEN; in bnx2_start_xmit()
6639 if (tcp_opt_len || (iph->ihl > 5)) { in bnx2_start_xmit()
6640 vlan_tag_flags |= ((iph->ihl - 5) + in bnx2_start_xmit()
6647 mapping = dma_map_single(&bp->pdev->dev, skb->data, len, in bnx2_start_xmit()
6649 if (dma_mapping_error(&bp->pdev->dev, mapping)) { in bnx2_start_xmit()
6654 tx_buf = &txr->tx_buf_ring[ring_prod]; in bnx2_start_xmit()
6655 tx_buf->skb = skb; in bnx2_start_xmit()
6658 txbd = &txr->tx_desc_ring[ring_prod]; in bnx2_start_xmit()
6660 txbd->tx_bd_haddr_hi = (u64) mapping >> 32; in bnx2_start_xmit()
6661 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff; in bnx2_start_xmit()
6662 txbd->tx_bd_mss_nbytes = len | (mss << 16); in bnx2_start_xmit()
6663 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START; in bnx2_start_xmit()
6665 last_frag = skb_shinfo(skb)->nr_frags; in bnx2_start_xmit()
6666 tx_buf->nr_frags = last_frag; in bnx2_start_xmit()
6667 tx_buf->is_gso = skb_is_gso(skb); in bnx2_start_xmit()
6670 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; in bnx2_start_xmit()
6674 txbd = &txr->tx_desc_ring[ring_prod]; in bnx2_start_xmit()
6677 mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 0, len, in bnx2_start_xmit()
6679 if (dma_mapping_error(&bp->pdev->dev, mapping)) in bnx2_start_xmit()
6681 dma_unmap_addr_set(&txr->tx_buf_ring[ring_prod], mapping, in bnx2_start_xmit()
6684 txbd->tx_bd_haddr_hi = (u64) mapping >> 32; in bnx2_start_xmit()
6685 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff; in bnx2_start_xmit()
6686 txbd->tx_bd_mss_nbytes = len | (mss << 16); in bnx2_start_xmit()
6687 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags; in bnx2_start_xmit()
6690 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END; in bnx2_start_xmit()
6695 netdev_tx_sent_queue(txq, skb->len); in bnx2_start_xmit()
6698 txr->tx_prod_bseq += skb->len; in bnx2_start_xmit()
6700 BNX2_WR16(bp, txr->tx_bidx_addr, prod); in bnx2_start_xmit()
6701 BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq); in bnx2_start_xmit()
6703 txr->tx_prod = prod; in bnx2_start_xmit()
6714 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh) in bnx2_start_xmit()
6724 prod = txr->tx_prod; in bnx2_start_xmit()
6726 tx_buf = &txr->tx_buf_ring[ring_prod]; in bnx2_start_xmit()
6727 tx_buf->skb = NULL; in bnx2_start_xmit()
6728 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping), in bnx2_start_xmit()
6735 tx_buf = &txr->tx_buf_ring[ring_prod]; in bnx2_start_xmit()
6736 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping), in bnx2_start_xmit()
6737 skb_frag_size(&skb_shinfo(skb)->frags[i]), in bnx2_start_xmit()
6754 del_timer_sync(&bp->timer); in bnx2_close()
6760 bp->link_up = 0; in bnx2_close()
6761 netif_carrier_off(bp->dev); in bnx2_close()
6768 u32 *hw_stats = (u32 *) bp->stats_blk; in bnx2_save_stats()
6769 u32 *temp_stats = (u32 *) bp->temp_stats_blk; in bnx2_save_stats()
6772 /* The 1st 10 counters are 64-bit counters */ in bnx2_save_stats()
6793 GET_64BIT_NET_STATS64(bp->stats_blk->ctr) + \
6794 GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr)
6797 (unsigned long) (bp->stats_blk->ctr + \
6798 bp->temp_stats_blk->ctr)
6805 if (!bp->stats_blk) in bnx2_get_stats64()
6808 net_stats->rx_packets = in bnx2_get_stats64()
6813 net_stats->tx_packets = in bnx2_get_stats64()
6818 net_stats->rx_bytes = in bnx2_get_stats64()
6821 net_stats->tx_bytes = in bnx2_get_stats64()
6824 net_stats->multicast = in bnx2_get_stats64()
6827 net_stats->collisions = in bnx2_get_stats64()
6830 net_stats->rx_length_errors = in bnx2_get_stats64()
6834 net_stats->rx_over_errors = in bnx2_get_stats64()
6838 net_stats->rx_frame_errors = in bnx2_get_stats64()
6841 net_stats->rx_crc_errors = in bnx2_get_stats64()
6844 net_stats->rx_errors = net_stats->rx_length_errors + in bnx2_get_stats64()
6845 net_stats->rx_over_errors + net_stats->rx_frame_errors + in bnx2_get_stats64()
6846 net_stats->rx_crc_errors; in bnx2_get_stats64()
6848 net_stats->tx_aborted_errors = in bnx2_get_stats64()
6854 net_stats->tx_carrier_errors = 0; in bnx2_get_stats64()
6856 net_stats->tx_carrier_errors = in bnx2_get_stats64()
6860 net_stats->tx_errors = in bnx2_get_stats64()
6862 net_stats->tx_aborted_errors + in bnx2_get_stats64()
6863 net_stats->tx_carrier_errors; in bnx2_get_stats64()
6865 net_stats->rx_missed_errors = in bnx2_get_stats64()
6883 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { in bnx2_get_link_ksettings()
6886 } else if (bp->phy_port == PORT_FIBRE) in bnx2_get_link_ksettings()
6894 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) in bnx2_get_link_ksettings()
6906 spin_lock_bh(&bp->phy_lock); in bnx2_get_link_ksettings()
6907 cmd->base.port = bp->phy_port; in bnx2_get_link_ksettings()
6908 advertising = bp->advertising; in bnx2_get_link_ksettings()
6910 if (bp->autoneg & AUTONEG_SPEED) { in bnx2_get_link_ksettings()
6911 cmd->base.autoneg = AUTONEG_ENABLE; in bnx2_get_link_ksettings()
6913 cmd->base.autoneg = AUTONEG_DISABLE; in bnx2_get_link_ksettings()
6917 cmd->base.speed = bp->line_speed; in bnx2_get_link_ksettings()
6918 cmd->base.duplex = bp->duplex; in bnx2_get_link_ksettings()
6919 if (!(bp->phy_flags & BNX2_PHY_FLAG_SERDES)) { in bnx2_get_link_ksettings()
6920 if (bp->phy_flags & BNX2_PHY_FLAG_MDIX) in bnx2_get_link_ksettings()
6921 cmd->base.eth_tp_mdix = ETH_TP_MDI_X; in bnx2_get_link_ksettings()
6923 cmd->base.eth_tp_mdix = ETH_TP_MDI; in bnx2_get_link_ksettings()
6927 cmd->base.speed = SPEED_UNKNOWN; in bnx2_get_link_ksettings()
6928 cmd->base.duplex = DUPLEX_UNKNOWN; in bnx2_get_link_ksettings()
6930 spin_unlock_bh(&bp->phy_lock); in bnx2_get_link_ksettings()
6932 cmd->base.phy_address = bp->phy_addr; in bnx2_get_link_ksettings()
6934 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, in bnx2_get_link_ksettings()
6936 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, in bnx2_get_link_ksettings()
6947 u8 autoneg = bp->autoneg; in bnx2_set_link_ksettings()
6948 u8 req_duplex = bp->req_duplex; in bnx2_set_link_ksettings()
6949 u16 req_line_speed = bp->req_line_speed; in bnx2_set_link_ksettings()
6950 u32 advertising = bp->advertising; in bnx2_set_link_ksettings()
6951 int err = -EINVAL; in bnx2_set_link_ksettings()
6953 spin_lock_bh(&bp->phy_lock); in bnx2_set_link_ksettings()
6955 if (cmd->base.port != PORT_TP && cmd->base.port != PORT_FIBRE) in bnx2_set_link_ksettings()
6958 if (cmd->base.port != bp->phy_port && in bnx2_set_link_ksettings()
6959 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)) in bnx2_set_link_ksettings()
6965 if (!netif_running(dev) && cmd->base.port != bp->phy_port) in bnx2_set_link_ksettings()
6968 if (cmd->base.autoneg == AUTONEG_ENABLE) { in bnx2_set_link_ksettings()
6972 &advertising, cmd->link_modes.advertising); in bnx2_set_link_ksettings()
6974 if (cmd->base.port == PORT_TP) { in bnx2_set_link_ksettings()
6986 u32 speed = cmd->base.speed; in bnx2_set_link_ksettings()
6988 if (cmd->base.port == PORT_FIBRE) { in bnx2_set_link_ksettings()
6991 (cmd->base.duplex != DUPLEX_FULL)) in bnx2_set_link_ksettings()
6995 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) in bnx2_set_link_ksettings()
7002 req_duplex = cmd->base.duplex; in bnx2_set_link_ksettings()
7006 bp->autoneg = autoneg; in bnx2_set_link_ksettings()
7007 bp->advertising = advertising; in bnx2_set_link_ksettings()
7008 bp->req_line_speed = req_line_speed; in bnx2_set_link_ksettings()
7009 bp->req_duplex = req_duplex; in bnx2_set_link_ksettings()
7016 err = bnx2_setup_phy(bp, cmd->base.port); in bnx2_set_link_ksettings()
7019 spin_unlock_bh(&bp->phy_lock); in bnx2_set_link_ksettings()
7029 strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); in bnx2_get_drvinfo()
7030 strscpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); in bnx2_get_drvinfo()
7031 strscpy(info->fw_version, bp->fw_version, sizeof(info->fw_version)); in bnx2_get_drvinfo()
7073 regs->version = 0; in bnx2_get_regs()
7077 if (!netif_running(bp->dev)) in bnx2_get_regs()
7099 if (bp->flags & BNX2_FLAG_NO_WOL) { in bnx2_get_wol()
7100 wol->supported = 0; in bnx2_get_wol()
7101 wol->wolopts = 0; in bnx2_get_wol()
7104 wol->supported = WAKE_MAGIC; in bnx2_get_wol()
7105 if (bp->wol) in bnx2_get_wol()
7106 wol->wolopts = WAKE_MAGIC; in bnx2_get_wol()
7108 wol->wolopts = 0; in bnx2_get_wol()
7110 memset(&wol->sopass, 0, sizeof(wol->sopass)); in bnx2_get_wol()
7118 if (wol->wolopts & ~WAKE_MAGIC) in bnx2_set_wol()
7119 return -EINVAL; in bnx2_set_wol()
7121 if (wol->wolopts & WAKE_MAGIC) { in bnx2_set_wol()
7122 if (bp->flags & BNX2_FLAG_NO_WOL) in bnx2_set_wol()
7123 return -EINVAL; in bnx2_set_wol()
7125 bp->wol = 1; in bnx2_set_wol()
7128 bp->wol = 0; in bnx2_set_wol()
7131 device_set_wakeup_enable(&bp->pdev->dev, bp->wol); in bnx2_set_wol()
7143 return -EAGAIN; in bnx2_nway_reset()
7145 if (!(bp->autoneg & AUTONEG_SPEED)) { in bnx2_nway_reset()
7146 return -EINVAL; in bnx2_nway_reset()
7149 spin_lock_bh(&bp->phy_lock); in bnx2_nway_reset()
7151 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { in bnx2_nway_reset()
7154 rc = bnx2_setup_remote_phy(bp, bp->phy_port); in bnx2_nway_reset()
7155 spin_unlock_bh(&bp->phy_lock); in bnx2_nway_reset()
7160 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { in bnx2_nway_reset()
7161 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); in bnx2_nway_reset()
7162 spin_unlock_bh(&bp->phy_lock); in bnx2_nway_reset()
7166 spin_lock_bh(&bp->phy_lock); in bnx2_nway_reset()
7168 bp->current_interval = BNX2_SERDES_AN_TIMEOUT; in bnx2_nway_reset()
7169 bp->serdes_an_pending = 1; in bnx2_nway_reset()
7170 mod_timer(&bp->timer, jiffies + bp->current_interval); in bnx2_nway_reset()
7173 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); in bnx2_nway_reset()
7175 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE); in bnx2_nway_reset()
7177 spin_unlock_bh(&bp->phy_lock); in bnx2_nway_reset()
7187 return bp->link_up; in bnx2_get_link()
7195 if (!bp->flash_info) in bnx2_get_eeprom_len()
7198 return (int) bp->flash_size; in bnx2_get_eeprom_len()
7210 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); in bnx2_get_eeprom()
7224 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); in bnx2_set_eeprom()
7238 coal->rx_coalesce_usecs = bp->rx_ticks; in bnx2_get_coalesce()
7239 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip; in bnx2_get_coalesce()
7240 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int; in bnx2_get_coalesce()
7241 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int; in bnx2_get_coalesce()
7243 coal->tx_coalesce_usecs = bp->tx_ticks; in bnx2_get_coalesce()
7244 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip; in bnx2_get_coalesce()
7245 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int; in bnx2_get_coalesce()
7246 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int; in bnx2_get_coalesce()
7248 coal->stats_block_coalesce_usecs = bp->stats_ticks; in bnx2_get_coalesce()
7260 bp->rx_ticks = (u16) coal->rx_coalesce_usecs; in bnx2_set_coalesce()
7261 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff; in bnx2_set_coalesce()
7263 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames; in bnx2_set_coalesce()
7264 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff; in bnx2_set_coalesce()
7266 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq; in bnx2_set_coalesce()
7267 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff; in bnx2_set_coalesce()
7269 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq; in bnx2_set_coalesce()
7270 if (bp->rx_quick_cons_trip_int > 0xff) in bnx2_set_coalesce()
7271 bp->rx_quick_cons_trip_int = 0xff; in bnx2_set_coalesce()
7273 bp->tx_ticks = (u16) coal->tx_coalesce_usecs; in bnx2_set_coalesce()
7274 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff; in bnx2_set_coalesce()
7276 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames; in bnx2_set_coalesce()
7277 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff; in bnx2_set_coalesce()
7279 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq; in bnx2_set_coalesce()
7280 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff; in bnx2_set_coalesce()
7282 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq; in bnx2_set_coalesce()
7283 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int = in bnx2_set_coalesce()
7286 bp->stats_ticks = coal->stats_block_coalesce_usecs; in bnx2_set_coalesce()
7287 if (bp->flags & BNX2_FLAG_BROKEN_STATS) { in bnx2_set_coalesce()
7288 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC) in bnx2_set_coalesce()
7289 bp->stats_ticks = USEC_PER_SEC; in bnx2_set_coalesce()
7291 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS) in bnx2_set_coalesce()
7292 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS; in bnx2_set_coalesce()
7293 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS; in bnx2_set_coalesce()
7295 if (netif_running(bp->dev)) { in bnx2_set_coalesce()
7311 ering->rx_max_pending = BNX2_MAX_TOTAL_RX_DESC_CNT; in bnx2_get_ringparam()
7312 ering->rx_jumbo_max_pending = BNX2_MAX_TOTAL_RX_PG_DESC_CNT; in bnx2_get_ringparam()
7314 ering->rx_pending = bp->rx_ring_size; in bnx2_get_ringparam()
7315 ering->rx_jumbo_pending = bp->rx_pg_ring_size; in bnx2_get_ringparam()
7317 ering->tx_max_pending = BNX2_MAX_TX_DESC_CNT; in bnx2_get_ringparam()
7318 ering->tx_pending = bp->tx_ring_size; in bnx2_get_ringparam()
7324 if (netif_running(bp->dev)) { in bnx2_change_ring_size()
7341 bp->tx_ring_size = tx; in bnx2_change_ring_size()
7343 if (netif_running(bp->dev)) { in bnx2_change_ring_size()
7362 dev_close(bp->dev); in bnx2_change_ring_size()
7366 mutex_lock(&bp->cnic_lock); in bnx2_change_ring_size()
7368 if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD) in bnx2_change_ring_size()
7370 mutex_unlock(&bp->cnic_lock); in bnx2_change_ring_size()
7385 if ((ering->rx_pending > BNX2_MAX_TOTAL_RX_DESC_CNT) || in bnx2_set_ringparam()
7386 (ering->tx_pending > BNX2_MAX_TX_DESC_CNT) || in bnx2_set_ringparam()
7387 (ering->tx_pending <= MAX_SKB_FRAGS)) { in bnx2_set_ringparam()
7389 return -EINVAL; in bnx2_set_ringparam()
7391 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending, in bnx2_set_ringparam()
7401 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0); in bnx2_get_pauseparam()
7402 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0); in bnx2_get_pauseparam()
7403 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0); in bnx2_get_pauseparam()
7411 bp->req_flow_ctrl = 0; in bnx2_set_pauseparam()
7412 if (epause->rx_pause) in bnx2_set_pauseparam()
7413 bp->req_flow_ctrl |= FLOW_CTRL_RX; in bnx2_set_pauseparam()
7414 if (epause->tx_pause) in bnx2_set_pauseparam()
7415 bp->req_flow_ctrl |= FLOW_CTRL_TX; in bnx2_set_pauseparam()
7417 if (epause->autoneg) { in bnx2_set_pauseparam()
7418 bp->autoneg |= AUTONEG_FLOW_CTRL; in bnx2_set_pauseparam()
7421 bp->autoneg &= ~AUTONEG_FLOW_CTRL; in bnx2_set_pauseparam()
7425 spin_lock_bh(&bp->phy_lock); in bnx2_set_pauseparam()
7426 bnx2_setup_phy(bp, bp->phy_port); in bnx2_set_pauseparam()
7427 spin_unlock_bh(&bp->phy_lock); in bnx2_set_pauseparam()
7580 return -EOPNOTSUPP; in bnx2_get_sset_count()
7590 if (etest->flags & ETH_TEST_FL_OFFLINE) { in bnx2_self_test()
7599 etest->flags |= ETH_TEST_FL_FAILED; in bnx2_self_test()
7603 etest->flags |= ETH_TEST_FL_FAILED; in bnx2_self_test()
7606 etest->flags |= ETH_TEST_FL_FAILED; in bnx2_self_test()
7608 if (!netif_running(bp->dev)) in bnx2_self_test()
7617 if (bp->link_up) in bnx2_self_test()
7625 etest->flags |= ETH_TEST_FL_FAILED; in bnx2_self_test()
7629 etest->flags |= ETH_TEST_FL_FAILED; in bnx2_self_test()
7634 etest->flags |= ETH_TEST_FL_FAILED; in bnx2_self_test()
7660 u32 *hw_stats = (u32 *) bp->stats_blk; in bnx2_get_ethtool_stats()
7661 u32 *temp_stats = (u32 *) bp->temp_stats_blk; in bnx2_get_ethtool_stats()
7688 /* 4-byte counter */ in bnx2_get_ethtool_stats()
7693 /* 8-byte counter */ in bnx2_get_ethtool_stats()
7708 bp->leds_save = BNX2_RD(bp, BNX2_MISC_CFG); in bnx2_set_phys_id()
7727 BNX2_WR(bp, BNX2_MISC_CFG, bp->leds_save); in bnx2_set_phys_id()
7741 dev->vlan_features |= (dev->hw_features & NETIF_F_ALL_TSO); in bnx2_set_features()
7743 dev->vlan_features &= ~NETIF_F_ALL_TSO; in bnx2_set_features()
7746 !!(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) && in bnx2_set_features()
7749 dev->features = features; in bnx2_set_features()
7766 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) { in bnx2_get_channels()
7771 channels->max_rx = max_rx_rings; in bnx2_get_channels()
7772 channels->max_tx = max_tx_rings; in bnx2_get_channels()
7773 channels->max_other = 0; in bnx2_get_channels()
7774 channels->max_combined = 0; in bnx2_get_channels()
7775 channels->rx_count = bp->num_rx_rings; in bnx2_get_channels()
7776 channels->tx_count = bp->num_tx_rings; in bnx2_get_channels()
7777 channels->other_count = 0; in bnx2_get_channels()
7778 channels->combined_count = 0; in bnx2_get_channels()
7789 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) { in bnx2_set_channels()
7793 if (channels->rx_count > max_rx_rings || in bnx2_set_channels()
7794 channels->tx_count > max_tx_rings) in bnx2_set_channels()
7795 return -EINVAL; in bnx2_set_channels()
7797 bp->num_req_rx_rings = channels->rx_count; in bnx2_set_channels()
7798 bp->num_req_tx_rings = channels->tx_count; in bnx2_set_channels()
7801 rc = bnx2_change_ring_size(bp, bp->rx_ring_size, in bnx2_set_channels()
7802 bp->tx_ring_size, true); in bnx2_set_channels()
7850 data->phy_id = bp->phy_addr; in bnx2_ioctl()
7856 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) in bnx2_ioctl()
7857 return -EOPNOTSUPP; in bnx2_ioctl()
7860 return -EAGAIN; in bnx2_ioctl()
7862 spin_lock_bh(&bp->phy_lock); in bnx2_ioctl()
7863 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval); in bnx2_ioctl()
7864 spin_unlock_bh(&bp->phy_lock); in bnx2_ioctl()
7866 data->val_out = mii_regval; in bnx2_ioctl()
7872 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) in bnx2_ioctl()
7873 return -EOPNOTSUPP; in bnx2_ioctl()
7876 return -EAGAIN; in bnx2_ioctl()
7878 spin_lock_bh(&bp->phy_lock); in bnx2_ioctl()
7879 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in); in bnx2_ioctl()
7880 spin_unlock_bh(&bp->phy_lock); in bnx2_ioctl()
7888 return -EOPNOTSUPP; in bnx2_ioctl()
7898 if (!is_valid_ether_addr(addr->sa_data)) in bnx2_change_mac_addr()
7899 return -EADDRNOTAVAIL; in bnx2_change_mac_addr()
7901 eth_hw_addr_set(dev, addr->sa_data); in bnx2_change_mac_addr()
7903 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0); in bnx2_change_mac_addr()
7914 dev->mtu = new_mtu; in bnx2_change_mtu()
7915 return bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size, in bnx2_change_mtu()
7926 for (i = 0; i < bp->irq_nvecs; i++) { in poll_bnx2()
7927 struct bnx2_irq *irq = &bp->irq_tbl[i]; in poll_bnx2()
7929 disable_irq(irq->vector); in poll_bnx2()
7930 irq->handler(irq->vector, &bp->bnx2_napi[i]); in poll_bnx2()
7931 enable_irq(irq->vector); in poll_bnx2()
7946 bp->phy_flags |= BNX2_PHY_FLAG_SERDES; in bnx2_get_5709_media()
7955 if (bp->func == 0) { in bnx2_get_5709_media()
7960 bp->phy_flags |= BNX2_PHY_FLAG_SERDES; in bnx2_get_5709_media()
7968 bp->phy_flags |= BNX2_PHY_FLAG_SERDES; in bnx2_get_5709_media()
7983 bp->flags |= BNX2_FLAG_PCIX; in bnx2_get_pci_speed()
7990 bp->bus_speed_mhz = 133; in bnx2_get_pci_speed()
7994 bp->bus_speed_mhz = 100; in bnx2_get_pci_speed()
7999 bp->bus_speed_mhz = 66; in bnx2_get_pci_speed()
8004 bp->bus_speed_mhz = 50; in bnx2_get_pci_speed()
8010 bp->bus_speed_mhz = 33; in bnx2_get_pci_speed()
8016 bp->bus_speed_mhz = 66; in bnx2_get_pci_speed()
8018 bp->bus_speed_mhz = 33; in bnx2_get_pci_speed()
8022 bp->flags |= BNX2_FLAG_PCI_32BIT; in bnx2_get_pci_speed()
8065 memcpy(bp->fw_version, &data[j], len); in bnx2_read_vpd_fw_ver()
8066 bp->fw_version[len] = ' '; in bnx2_read_vpd_fw_ver()
8080 SET_NETDEV_DEV(dev, &pdev->dev); in bnx2_init_board()
8083 bp->flags = 0; in bnx2_init_board()
8084 bp->phy_flags = 0; in bnx2_init_board()
8086 bp->temp_stats_blk = in bnx2_init_board()
8089 if (!bp->temp_stats_blk) { in bnx2_init_board()
8090 rc = -ENOMEM; in bnx2_init_board()
8094 /* enable device (incl. PCI PM wakeup), and bus-mastering */ in bnx2_init_board()
8097 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); in bnx2_init_board()
8102 dev_err(&pdev->dev, in bnx2_init_board()
8104 rc = -ENODEV; in bnx2_init_board()
8110 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); in bnx2_init_board()
8116 bp->pm_cap = pdev->pm_cap; in bnx2_init_board()
8117 if (bp->pm_cap == 0) { in bnx2_init_board()
8118 dev_err(&pdev->dev, in bnx2_init_board()
8120 rc = -EIO; in bnx2_init_board()
8124 bp->dev = dev; in bnx2_init_board()
8125 bp->pdev = pdev; in bnx2_init_board()
8127 spin_lock_init(&bp->phy_lock); in bnx2_init_board()
8128 spin_lock_init(&bp->indirect_lock); in bnx2_init_board()
8130 mutex_init(&bp->cnic_lock); in bnx2_init_board()
8132 INIT_WORK(&bp->reset_task, bnx2_reset_task); in bnx2_init_board()
8134 bp->regview = pci_iomap(pdev, 0, MB_GET_CID_ADDR(TX_TSS_CID + in bnx2_init_board()
8136 if (!bp->regview) { in bnx2_init_board()
8137 dev_err(&pdev->dev, "Cannot map register space, aborting\n"); in bnx2_init_board()
8138 rc = -ENOMEM; in bnx2_init_board()
8150 bp->chip_id = BNX2_RD(bp, BNX2_MISC_ID); in bnx2_init_board()
8154 dev_err(&pdev->dev, "Not PCIE, aborting\n"); in bnx2_init_board()
8155 rc = -EIO; in bnx2_init_board()
8158 bp->flags |= BNX2_FLAG_PCIE; in bnx2_init_board()
8160 bp->flags |= BNX2_FLAG_JUMBO_BROKEN; in bnx2_init_board()
8162 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX); in bnx2_init_board()
8163 if (bp->pcix_cap == 0) { in bnx2_init_board()
8164 dev_err(&pdev->dev, in bnx2_init_board()
8166 rc = -EIO; in bnx2_init_board()
8169 bp->flags |= BNX2_FLAG_BROKEN_STATS; in bnx2_init_board()
8174 if (pdev->msix_cap) in bnx2_init_board()
8175 bp->flags |= BNX2_FLAG_MSIX_CAP; in bnx2_init_board()
8180 if (pdev->msi_cap) in bnx2_init_board()
8181 bp->flags |= BNX2_FLAG_MSI_CAP; in bnx2_init_board()
8184 /* 5708 cannot support DMA addresses > 40-bit. */ in bnx2_init_board()
8191 if (dma_set_mask(&pdev->dev, dma_mask) == 0) { in bnx2_init_board()
8192 dev->features |= NETIF_F_HIGHDMA; in bnx2_init_board()
8193 rc = dma_set_coherent_mask(&pdev->dev, persist_dma_mask); in bnx2_init_board()
8195 dev_err(&pdev->dev, in bnx2_init_board()
8199 } else if ((rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) != 0) { in bnx2_init_board()
8200 dev_err(&pdev->dev, "System does not support DMA, aborting\n"); in bnx2_init_board()
8204 if (!(bp->flags & BNX2_FLAG_PCIE)) in bnx2_init_board()
8213 !(bp->flags & BNX2_FLAG_PCIX)) { in bnx2_init_board()
8214 dev_err(&pdev->dev, in bnx2_init_board()
8216 rc = -EPERM; in bnx2_init_board()
8225 bp->func = 1; in bnx2_init_board()
8229 u32 off = bp->func << 2; in bnx2_init_board()
8231 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off); in bnx2_init_board()
8233 bp->shmem_base = HOST_VIEW_SHMEM_BASE; in bnx2_init_board()
8242 dev_err(&pdev->dev, "Firmware not running, aborting\n"); in bnx2_init_board()
8243 rc = -ENODEV; in bnx2_init_board()
8249 j = strlen(bp->fw_version); in bnx2_init_board()
8255 bp->fw_version[j++] = 'b'; in bnx2_init_board()
8256 bp->fw_version[j++] = 'c'; in bnx2_init_board()
8257 bp->fw_version[j++] = ' '; in bnx2_init_board()
8259 num = (u8) (reg >> (24 - (i * 8))); in bnx2_init_board()
8262 bp->fw_version[j++] = (num / k) + '0'; in bnx2_init_board()
8267 bp->fw_version[j++] = '.'; in bnx2_init_board()
8271 bp->wol = 1; in bnx2_init_board()
8274 bp->flags |= BNX2_FLAG_ASF_ENABLE; in bnx2_init_board()
8290 bp->fw_version[j++] = ' '; in bnx2_init_board()
8294 memcpy(&bp->fw_version[j], ®, 4); in bnx2_init_board()
8300 bp->mac_addr[0] = (u8) (reg >> 8); in bnx2_init_board()
8301 bp->mac_addr[1] = (u8) reg; in bnx2_init_board()
8304 bp->mac_addr[2] = (u8) (reg >> 24); in bnx2_init_board()
8305 bp->mac_addr[3] = (u8) (reg >> 16); in bnx2_init_board()
8306 bp->mac_addr[4] = (u8) (reg >> 8); in bnx2_init_board()
8307 bp->mac_addr[5] = (u8) reg; in bnx2_init_board()
8309 bp->tx_ring_size = BNX2_MAX_TX_DESC_CNT; in bnx2_init_board()
8312 bp->tx_quick_cons_trip_int = 2; in bnx2_init_board()
8313 bp->tx_quick_cons_trip = 20; in bnx2_init_board()
8314 bp->tx_ticks_int = 18; in bnx2_init_board()
8315 bp->tx_ticks = 80; in bnx2_init_board()
8317 bp->rx_quick_cons_trip_int = 2; in bnx2_init_board()
8318 bp->rx_quick_cons_trip = 12; in bnx2_init_board()
8319 bp->rx_ticks_int = 18; in bnx2_init_board()
8320 bp->rx_ticks = 18; in bnx2_init_board()
8322 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS; in bnx2_init_board()
8324 bp->current_interval = BNX2_TIMER_INTERVAL; in bnx2_init_board()
8326 bp->phy_addr = 1; in bnx2_init_board()
8337 bp->phy_flags |= BNX2_PHY_FLAG_SERDES; in bnx2_init_board()
8339 bp->phy_port = PORT_TP; in bnx2_init_board()
8340 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { in bnx2_init_board()
8341 bp->phy_port = PORT_FIBRE; in bnx2_init_board()
8344 bp->flags |= BNX2_FLAG_NO_WOL; in bnx2_init_board()
8345 bp->wol = 0; in bnx2_init_board()
8352 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP && in bnx2_init_board()
8353 pdev->subsystem_device == 0x310c) in bnx2_init_board()
8354 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL; in bnx2_init_board()
8356 bp->phy_addr = 2; in bnx2_init_board()
8358 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE; in bnx2_init_board()
8362 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX; in bnx2_init_board()
8366 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC; in bnx2_init_board()
8374 bp->flags |= BNX2_FLAG_NO_WOL; in bnx2_init_board()
8375 bp->wol = 0; in bnx2_init_board()
8378 if (bp->flags & BNX2_FLAG_NO_WOL) in bnx2_init_board()
8379 device_set_wakeup_capable(&bp->pdev->dev, false); in bnx2_init_board()
8381 device_set_wakeup_enable(&bp->pdev->dev, bp->wol); in bnx2_init_board()
8384 bp->tx_quick_cons_trip_int = in bnx2_init_board()
8385 bp->tx_quick_cons_trip; in bnx2_init_board()
8386 bp->tx_ticks_int = bp->tx_ticks; in bnx2_init_board()
8387 bp->rx_quick_cons_trip_int = in bnx2_init_board()
8388 bp->rx_quick_cons_trip; in bnx2_init_board()
8389 bp->rx_ticks_int = bp->rx_ticks; in bnx2_init_board()
8390 bp->comp_prod_trip_int = bp->comp_prod_trip; in bnx2_init_board()
8391 bp->com_ticks_int = bp->com_ticks; in bnx2_init_board()
8392 bp->cmd_ticks_int = bp->cmd_ticks; in bnx2_init_board()
8397 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes in bnx2_init_board()
8398 * with byte enables disabled on the unused 32-bit word. This is legal in bnx2_init_board()
8412 if (amd_8132->revision >= 0x10 && in bnx2_init_board()
8413 amd_8132->revision <= 0x13) { in bnx2_init_board()
8422 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX; in bnx2_init_board()
8424 timer_setup(&bp->timer, bnx2_timer, 0); in bnx2_init_board()
8425 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL); in bnx2_init_board()
8429 bp->cnic_eth_dev.max_iscsi_conn = in bnx2_init_board()
8432 bp->cnic_probe = bnx2_cnic_probe; in bnx2_init_board()
8439 pci_iounmap(pdev, bp->regview); in bnx2_init_board()
8440 bp->regview = NULL; in bnx2_init_board()
8449 kfree(bp->temp_stats_blk); in bnx2_init_board()
8459 if (bp->flags & BNX2_FLAG_PCIE) { in bnx2_bus_string()
8463 if (bp->flags & BNX2_FLAG_PCIX) in bnx2_bus_string()
8464 s += sprintf(s, "-X"); in bnx2_bus_string()
8465 if (bp->flags & BNX2_FLAG_PCI_32BIT) in bnx2_bus_string()
8466 s += sprintf(s, " 32-bit"); in bnx2_bus_string()
8468 s += sprintf(s, " 64-bit"); in bnx2_bus_string()
8469 s += sprintf(s, " %dMHz", bp->bus_speed_mhz); in bnx2_bus_string()
8479 for (i = 0; i < bp->irq_nvecs; i++) in bnx2_del_napi()
8480 netif_napi_del(&bp->bnx2_napi[i].napi); in bnx2_del_napi()
8488 for (i = 0; i < bp->irq_nvecs; i++) { in bnx2_init_napi()
8489 struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; in bnx2_init_napi()
8497 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll); in bnx2_init_napi()
8498 bnapi->bp = bp; in bnx2_init_napi()
8530 return -ENOMEM; in bnx2_init_one()
8536 dev->netdev_ops = &bnx2_netdev_ops; in bnx2_init_one()
8537 dev->watchdog_timeo = TX_TIMEOUT; in bnx2_init_one()
8538 dev->ethtool_ops = &bnx2_ethtool_ops; in bnx2_init_one()
8545 * In-flight DMA from 1st kernel could continue going in kdump kernel. in bnx2_init_one()
8546 * New io-page table has been created before bnx2 does reset at open stage. in bnx2_init_one()
8547 * We have to wait for the in-flight DMA to complete to avoid it look up in bnx2_init_one()
8548 * into the newly created io-page table. in bnx2_init_one()
8553 eth_hw_addr_set(dev, bp->mac_addr); in bnx2_init_one()
8555 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | in bnx2_init_one()
8560 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6; in bnx2_init_one()
8562 dev->vlan_features = dev->hw_features; in bnx2_init_one()
8563 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; in bnx2_init_one()
8564 dev->features |= dev->hw_features; in bnx2_init_one()
8565 dev->priv_flags |= IFF_UNICAST_FLT; in bnx2_init_one()
8566 dev->min_mtu = MIN_ETHERNET_PACKET_SIZE; in bnx2_init_one()
8567 dev->max_mtu = MAX_ETHERNET_JUMBO_PACKET_SIZE; in bnx2_init_one()
8569 if (!(bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)) in bnx2_init_one()
8570 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; in bnx2_init_one()
8573 dev_err(&pdev->dev, "Cannot register net device\n"); in bnx2_init_one()
8578 "node addr %pM\n", board_info[ent->driver_data].name, in bnx2_init_one()
8582 pdev->irq, dev->dev_addr); in bnx2_init_one()
8587 pci_iounmap(pdev, bp->regview); in bnx2_init_one()
8604 del_timer_sync(&bp->timer); in bnx2_remove_one()
8605 cancel_work_sync(&bp->reset_task); in bnx2_remove_one()
8607 pci_iounmap(bp->pdev, bp->regview); in bnx2_remove_one()
8610 kfree(bp->temp_stats_blk); in bnx2_remove_one()
8628 cancel_work_sync(&bp->reset_task); in bnx2_suspend()
8631 del_timer_sync(&bp->timer); in bnx2_suspend()
8666 * bnx2_io_error_detected - called when PCI error is detected
8689 del_timer_sync(&bp->timer); in bnx2_io_error_detected()
8701 * bnx2_io_slot_reset - called after the pci bus has been reset.
8704 * Restart the card from scratch, as if from a cold-boot.
8715 dev_err(&pdev->dev, in bnx2_io_slot_reset()
8716 "Cannot re-enable PCI device after reset\n"); in bnx2_io_slot_reset()
8739 * bnx2_io_resume - called when traffic can start flowing again.
8772 dev_close(bp->dev); in bnx2_shutdown()