Lines Matching +full:0 +full:x0000ff7f
81 static int disable_msi = 0;
87 BCM5706 = 0,
119 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
121 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
127 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
136 { PCI_VENDOR_ID_BROADCOM, 0x163b,
137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
138 { PCI_VENDOR_ID_BROADCOM, 0x163c,
139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
140 { 0, }
148 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
153 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
155 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
159 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
165 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
170 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
172 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
175 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
180 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
186 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
191 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
196 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
198 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
201 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
203 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
206 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
211 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
213 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
216 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
218 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
221 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
223 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
226 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
255 diff &= 0xffff; in bnx2_tx_avail()
311 for (i = 0; i < 5; i++) { in bnx2_ctx_wr()
313 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0) in bnx2_ctx_wr()
344 return 0; in bnx2_drv_ctl()
350 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; in bnx2_setup_cnic_irq_info()
355 bnapi->cnic_present = 0; in bnx2_setup_cnic_irq_info()
357 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; in bnx2_setup_cnic_irq_info()
362 sb_id = 0; in bnx2_setup_cnic_irq_info()
363 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; in bnx2_setup_cnic_irq_info()
366 cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector; in bnx2_setup_cnic_irq_info()
367 cp->irq_arr[0].status_blk = (void *) in bnx2_setup_cnic_irq_info()
370 cp->irq_arr[0].status_blk_num = sb_id; in bnx2_setup_cnic_irq_info()
392 cp->num_irq = 0; in bnx2_register_cnic()
397 return 0; in bnx2_register_cnic()
403 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; in bnx2_unregister_cnic()
407 cp->drv_state = 0; in bnx2_unregister_cnic()
408 bnapi->cnic_present = 0; in bnx2_unregister_cnic()
412 return 0; in bnx2_unregister_cnic()
461 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; in bnx2_cnic_start()
506 for (i = 0; i < 50; i++) { in bnx2_read_phy()
521 *val = 0x0; in bnx2_read_phy()
526 ret = 0; in bnx2_read_phy()
563 for (i = 0; i < 50; i++) { in bnx2_write_phy()
576 ret = 0; in bnx2_write_phy()
597 for (i = 0; i < bp->irq_nvecs; i++) { in bnx2_disable_int()
611 for (i = 0; i < bp->irq_nvecs; i++) { in bnx2_enable_int()
636 for (i = 0; i < bp->irq_nvecs; i++) in bnx2_disable_int_sync()
645 for (i = 0; i < bp->irq_nvecs; i++) in bnx2_napi_disable()
654 for (i = 0; i < bp->irq_nvecs; i++) in bnx2_napi_enable()
694 for (i = 0; i < bp->num_tx_rings; i++) { in bnx2_free_tx_mem()
714 for (i = 0; i < bp->num_rx_rings; i++) { in bnx2_free_rx_mem()
719 for (j = 0; j < bp->rx_max_ring; j++) { in bnx2_free_rx_mem()
729 for (j = 0; j < bp->rx_max_pg_ring; j++) { in bnx2_free_rx_mem()
746 for (i = 0; i < bp->num_tx_rings; i++) { in bnx2_alloc_tx_mem()
760 return 0; in bnx2_alloc_tx_mem()
768 for (i = 0; i < bp->num_rx_rings; i++) { in bnx2_alloc_rx_mem()
778 for (j = 0; j < bp->rx_max_ring; j++) { in bnx2_alloc_rx_mem()
798 for (j = 0; j < bp->rx_max_pg_ring; j++) { in bnx2_alloc_rx_mem()
809 return 0; in bnx2_alloc_rx_mem()
849 return 0; in bnx2_alloc_stats_blk()
856 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; in bnx2_free_mem()
861 for (i = 0; i < bp->ctx_pages; i++) { in bnx2_free_mem()
880 bnapi = &bp->bnx2_napi[0]; in bnx2_alloc_mem()
903 bp->ctx_pages = 0x2000 / BNX2_PAGE_SIZE; in bnx2_alloc_mem()
904 if (bp->ctx_pages == 0) in bnx2_alloc_mem()
906 for (i = 0; i < bp->ctx_pages; i++) { in bnx2_alloc_mem()
924 return 0; in bnx2_alloc_mem()
934 u32 fw_link_status = 0; in bnx2_report_fw_link()
1034 bp->flow_ctrl = 0; in bnx2_resolve_flow_ctrl()
1064 u32 new_local_adv = 0; in bnx2_resolve_flow_ctrl()
1065 u32 new_remote_adv = 0; in bnx2_resolve_flow_ctrl()
1116 if ((bp->autoneg & AUTONEG_SPEED) == 0) { in bnx2_5709s_linkup()
1119 return 0; in bnx2_5709s_linkup()
1141 return 0; in bnx2_5709s_linkup()
1170 return 0; in bnx2_5708s_linkup()
1190 return 0; in bnx2_5706s_linkup()
1207 return 0; in bnx2_5706s_linkup()
1255 bp->line_speed = 0; in bnx2_copper_linkup()
1256 bp->link_up = 0; in bnx2_copper_linkup()
1283 return 0; in bnx2_copper_linkup()
1293 val |= 0x02 << 8; in bnx2_init_rx_context()
1307 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) { in bnx2_init_all_rx_contexts()
1319 BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620); in bnx2_set_mac_link()
1322 BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff); in bnx2_set_mac_link()
1406 return 0; in bnx2_test_and_enable_2g5()
1418 ret = 0; in bnx2_test_and_enable_2g5()
1432 int ret = 0; in bnx2_test_and_disable_2g5()
1435 return 0; in bnx2_test_and_disable_2g5()
1545 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f); in bnx2_5706s_force_link_dn()
1547 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0); in bnx2_5706s_force_link_dn()
1558 return 0; in bnx2_set_link()
1562 return 0; in bnx2_set_link()
1576 bnx2_5706s_force_link_dn(bp, 0); in bnx2_set_link()
1622 bp->link_up = 0; in bnx2_set_link()
1631 return 0; in bnx2_set_link()
1643 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) { in bnx2_reset_phy()
1655 return 0; in bnx2_reset_phy()
1661 u32 adv = 0; in bnx2_phy_get_pause_adv()
1699 u32 speed_arg = 0, pause_adv; in bnx2_setup_remote_phy()
1747 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0); in bnx2_setup_remote_phy()
1750 return 0; in bnx2_setup_remote_phy()
1759 u32 new_adv = 0; in bnx2_setup_serdes_phy()
1766 int force_link_down = 0; in bnx2_setup_serdes_phy()
1787 new_bmcr &= ~0x2000; in bnx2_setup_serdes_phy()
1814 bp->link_up = 0; in bnx2_setup_serdes_phy()
1825 return 0; in bnx2_setup_serdes_phy()
1838 bp->serdes_an_pending = 0; in bnx2_setup_serdes_phy()
1839 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) { in bnx2_setup_serdes_phy()
1867 return 0; in bnx2_setup_serdes_phy()
1896 bp->req_line_speed = 0; in bnx2_set_default_remote_link()
1912 bp->autoneg = 0; in bnx2_set_default_remote_link()
1913 bp->advertising = 0; in bnx2_set_default_remote_link()
1941 bp->req_line_speed = 0; in bnx2_set_default_link()
1950 bp->autoneg = 0; in bnx2_set_default_link()
1987 bp->link_up = 0; in bnx2_remote_phy_event()
2021 bp->line_speed = 0; in bnx2_remote_phy_event()
2025 bp->flow_ctrl = 0; in bnx2_remote_phy_event()
2068 return 0; in bnx2_set_remote_link()
2076 u32 bmcr, adv_reg, new_adv = 0; in bnx2_setup_copper_phy()
2089 u32 new_adv1000 = 0; in bnx2_setup_copper_phy()
2099 ((bmcr & BMCR_ANENABLE) == 0)) { in bnx2_setup_copper_phy()
2113 return 0; in bnx2_setup_copper_phy()
2120 new_bmcr = 0; in bnx2_setup_copper_phy()
2160 return 0; in bnx2_setup_copper_phy()
2169 return 0; in bnx2_setup_phy()
2184 bp->mii_bmcr = MII_BMCR + 0x10; in bnx2_init_5709s_phy()
2185 bp->mii_bmsr = MII_BMSR + 0x10; in bnx2_init_5709s_phy()
2187 bp->mii_adv = MII_ADVERTISE + 0x10; in bnx2_init_5709s_phy()
2188 bp->mii_lpa = MII_LPA + 0x10; in bnx2_init_5709s_phy()
2226 return 0; in bnx2_init_5709s_phy()
2284 return 0; in bnx2_init_5708s_phy()
2296 BNX2_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300); in bnx2_init_5706s_phy()
2302 bnx2_write_phy(bp, 0x18, 0x7); in bnx2_init_5706s_phy()
2303 bnx2_read_phy(bp, 0x18, &val); in bnx2_init_5706s_phy()
2304 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000); in bnx2_init_5706s_phy()
2306 bnx2_write_phy(bp, 0x1c, 0x6c00); in bnx2_init_5706s_phy()
2307 bnx2_read_phy(bp, 0x1c, &val); in bnx2_init_5706s_phy()
2308 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02); in bnx2_init_5706s_phy()
2313 bnx2_write_phy(bp, 0x18, 0x7); in bnx2_init_5706s_phy()
2314 bnx2_read_phy(bp, 0x18, &val); in bnx2_init_5706s_phy()
2315 bnx2_write_phy(bp, 0x18, val & ~0x4007); in bnx2_init_5706s_phy()
2317 bnx2_write_phy(bp, 0x1c, 0x6c00); in bnx2_init_5706s_phy()
2318 bnx2_read_phy(bp, 0x1c, &val); in bnx2_init_5706s_phy()
2319 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00); in bnx2_init_5706s_phy()
2322 return 0; in bnx2_init_5706s_phy()
2334 bnx2_write_phy(bp, 0x18, 0x0c00); in bnx2_init_copper_phy()
2335 bnx2_write_phy(bp, 0x17, 0x000a); in bnx2_init_copper_phy()
2336 bnx2_write_phy(bp, 0x15, 0x310b); in bnx2_init_copper_phy()
2337 bnx2_write_phy(bp, 0x17, 0x201f); in bnx2_init_copper_phy()
2338 bnx2_write_phy(bp, 0x15, 0x9506); in bnx2_init_copper_phy()
2339 bnx2_write_phy(bp, 0x17, 0x401f); in bnx2_init_copper_phy()
2340 bnx2_write_phy(bp, 0x15, 0x14e2); in bnx2_init_copper_phy()
2341 bnx2_write_phy(bp, 0x18, 0x0400); in bnx2_init_copper_phy()
2346 MII_BNX2_DSP_EXPAND_REG | 0x8); in bnx2_init_copper_phy()
2354 bnx2_write_phy(bp, 0x18, 0x7); in bnx2_init_copper_phy()
2355 bnx2_read_phy(bp, 0x18, &val); in bnx2_init_copper_phy()
2356 bnx2_write_phy(bp, 0x18, val | 0x4000); in bnx2_init_copper_phy()
2358 bnx2_read_phy(bp, 0x10, &val); in bnx2_init_copper_phy()
2359 bnx2_write_phy(bp, 0x10, val | 0x1); in bnx2_init_copper_phy()
2362 bnx2_write_phy(bp, 0x18, 0x7); in bnx2_init_copper_phy()
2363 bnx2_read_phy(bp, 0x18, &val); in bnx2_init_copper_phy()
2364 bnx2_write_phy(bp, 0x18, val & ~0x4007); in bnx2_init_copper_phy()
2366 bnx2_read_phy(bp, 0x10, &val); in bnx2_init_copper_phy()
2367 bnx2_write_phy(bp, 0x10, val & ~0x1); in bnx2_init_copper_phy()
2380 return 0; in bnx2_init_copper_phy()
2390 int rc = 0; in bnx2_init_phy()
2409 bp->phy_id |= val & 0xffff; in bnx2_init_phy()
2440 return 0; in bnx2_set_mac_loopback()
2458 for (i = 0; i < 10; i++) { in bnx2_set_phy_loopback()
2459 if (bnx2_test_link(bp) == 0) in bnx2_set_phy_loopback()
2472 return 0; in bnx2_set_phy_loopback()
2511 DP_SHMEM_LINE(bp, 0x3cc); in bnx2_dump_mcp_state()
2512 DP_SHMEM_LINE(bp, 0x3dc); in bnx2_dump_mcp_state()
2513 DP_SHMEM_LINE(bp, 0x3ec); in bnx2_dump_mcp_state()
2514 netdev_err(dev, "DEBUG: 0x3fc[%08x]\n", bnx2_shmem_rd(bp, 0x3fc)); in bnx2_dump_mcp_state()
2531 return 0; in bnx2_fw_sync()
2534 for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) { in bnx2_fw_sync()
2543 return 0; in bnx2_fw_sync()
2562 return 0; in bnx2_fw_sync()
2568 int i, ret = 0; in bnx2_init_5709_context()
2574 for (i = 0; i < 10; i++) { in bnx2_init_5709_context()
2583 for (i = 0; i < bp->ctx_pages; i++) { in bnx2_init_5709_context()
2587 memset(bp->ctx_blk[i], 0, BNX2_PAGE_SIZE); in bnx2_init_5709_context()
2592 (bp->ctx_blk_mapping[i] & 0xffffffff) | in bnx2_init_5709_context()
2598 for (j = 0; j < 10; j++) { in bnx2_init_5709_context()
2629 if (vcid & 0x8) { in bnx2_init_context()
2630 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7); in bnx2_init_context()
2642 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) { in bnx2_init_context()
2650 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) in bnx2_init_context()
2651 bnx2_ctx_wr(bp, vcid_addr, offset, 0); in bnx2_init_context()
2670 good_mbuf_cnt = 0; in bnx2_alloc_bad_rbuf()
2702 return 0; in bnx2_alloc_bad_rbuf()
2710 val = (mac_addr[0] << 8) | mac_addr[1]; in bnx2_set_mac_addr()
2731 mapping = dma_map_page(&bp->pdev->dev, page, 0, PAGE_SIZE, in bnx2_alloc_rx_page()
2741 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff; in bnx2_alloc_rx_page()
2742 return 0; in bnx2_alloc_rx_page()
2787 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff; in bnx2_alloc_rx_data()
2791 return 0; in bnx2_alloc_rx_data()
2809 is_set = 0; in bnx2_phy_event_is_set()
2845 int tx_pkt = 0, index; in bnx2_tx_int()
2846 unsigned int tx_bytes = 0; in bnx2_tx_int()
2877 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) { in bnx2_tx_int()
2888 for (i = 0; i < last; i++) { in bnx2_tx_int()
2965 for (i = 0; i < count; i++) { in bnx2_reuse_rx_skb_pages()
3028 u16 prod = ring_idx & 0xffff; in bnx2_rx_skb()
3052 if (hdr_len == 0) { in bnx2_rx_skb()
3065 for (i = 0; i < pages; i++) { in bnx2_rx_skb()
3077 if (i == 0) { in bnx2_rx_skb()
3096 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len); in bnx2_rx_skb()
3145 int rx_pkt = 0, pg_ring_used = 0; in bnx2_rx_int()
3147 if (budget <= 0) in bnx2_rx_int()
3190 hdr_len = 0; in bnx2_rx_int()
3250 skb->protocol != htons(0x8100) && in bnx2_rx_int()
3264 L2_FHDR_ERRORS_UDP_XSUM)) == 0)) in bnx2_rx_int()
3273 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]); in bnx2_rx_int()
3319 if (unlikely(atomic_read(&bp->intr_sem) != 0)) in bnx2_msi()
3336 if (unlikely(atomic_read(&bp->intr_sem) != 0)) in bnx2_msi_1shot()
3372 if (unlikely(atomic_read(&bp->intr_sem) != 0)) in bnx2_interrupt()
3392 return 0; in bnx2_has_fast_work()
3415 return 0; in bnx2_has_work()
3421 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; in bnx2_chk_missed_msi()
3433 bnx2_msi(bp->irq_tbl[0].vector, bnapi); in bnx2_chk_missed_msi()
3484 bnx2_tx_int(bp, bnapi, 0); in bnx2_poll_work()
3496 int work_done = 0; in bnx2_poll_msix()
3523 int work_done = 0; in bnx2_poll()
3597 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { in bnx2_set_rx_mode()
3599 0xffffffff); in bnx2_set_rx_mode()
3610 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS); in bnx2_set_rx_mode()
3614 bit = crc & 0xff; in bnx2_set_rx_mode()
3615 regidx = (bit & 0xe0) >> 5; in bnx2_set_rx_mode()
3616 bit &= 0x1f; in bnx2_set_rx_mode()
3620 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { in bnx2_set_rx_mode()
3634 i = 0; in bnx2_set_rx_mode()
3650 BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0); in bnx2_set_rx_mode()
3665 if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3) in check_fw_section()
3667 if ((non_empty && len == 0) || len > fw->size - offset || in check_fw_section()
3670 return 0; in check_fw_section()
3681 return 0; in check_mips_fw_entry()
3755 return bp->rv2p_firmware ? 0 : bnx2_request_uncached_firmware(bp); in bnx2_request_firmware()
3792 for (i = 0; i < rv2p_code_len; i += 8) { in load_rv2p_fw()
3803 for (i = 0; i < 8; i++) { in load_rv2p_fw()
3827 return 0; in load_rv2p_fw()
3855 for (j = 0; j < (len / 4); j++, offset += 4) in load_cpu_fw()
3869 for (j = 0; j < (len / 4); j++, offset += 4) in load_cpu_fw()
3883 for (j = 0; j < (len / 4); j++, offset += 4) in load_cpu_fw()
3888 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0); in load_cpu_fw()
3957 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0); in bnx2_setup_wol()
3977 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { in bnx2_setup_wol()
3979 0xffffffff); in bnx2_setup_wol()
3984 BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0); in bnx2_setup_wol()
4008 bnx2_fw_sync(bp, wol_msg, 1, 0); in bnx2_setup_wol()
4017 bnx2_fw_sync(bp, wol_msg, 1, 0); in bnx2_setup_wol()
4076 return 0; in bnx2_set_power_state()
4087 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { in bnx2_acquire_nvram_lock()
4098 return 0; in bnx2_acquire_nvram_lock()
4110 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { in bnx2_release_nvram_lock()
4121 return 0; in bnx2_release_nvram_lock()
4140 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { in bnx2_enable_nvram_write()
4151 return 0; in bnx2_enable_nvram_write()
4195 return 0; in bnx2_nvram_erase_page()
4211 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { in bnx2_nvram_erase_page()
4224 return 0; in bnx2_nvram_erase_page()
4253 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { in bnx2_nvram_read_dword()
4268 return 0; in bnx2_nvram_read_dword()
4304 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { in bnx2_nvram_write_dword()
4313 return 0; in bnx2_nvram_write_dword()
4320 int j, entry_count, rc = 0; in bnx2_init_nvram()
4333 if (val & 0x40000000) { in bnx2_init_nvram()
4336 for (j = 0, flash = &flash_table[0]; j < entry_count; in bnx2_init_nvram()
4354 for (j = 0, flash = &flash_table[0]; j < entry_count; in bnx2_init_nvram()
4361 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0) in bnx2_init_nvram()
4380 } /* if (val & 0x40000000) */ in bnx2_init_nvram()
4403 int rc = 0; in bnx2_nvram_read()
4406 if (buf_size == 0) in bnx2_nvram_read()
4407 return 0; in bnx2_nvram_read()
4410 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0) in bnx2_nvram_read()
4418 extra = 0; in bnx2_nvram_read()
4420 cmd_flags = 0; in bnx2_nvram_read()
4467 else if (len32 > 0) { in bnx2_nvram_read()
4472 cmd_flags = 0; in bnx2_nvram_read()
4483 while (len32 > 4 && rc == 0) { in bnx2_nvram_read()
4484 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0); in bnx2_nvram_read()
4515 int rc = 0; in bnx2_nvram_write()
4521 align_start = align_end = 0; in bnx2_nvram_write()
4561 written = 0; in bnx2_nvram_write()
4562 while ((written < len32) && (rc == 0)) { in bnx2_nvram_write()
4573 data_start = (written == 0) ? offset32 : page_start; in bnx2_nvram_write()
4579 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0) in bnx2_nvram_write()
4591 for (j = 0; j < bp->flash_info->page_size; j += 4) { in bnx2_nvram_write()
4603 cmd_flags = 0; in bnx2_nvram_write()
4608 if ((rc = bnx2_enable_nvram_write(bp)) != 0) in bnx2_nvram_write()
4613 i = 0; in bnx2_nvram_write()
4616 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0) in bnx2_nvram_write()
4628 if (rc != 0) in bnx2_nvram_write()
4631 cmd_flags = 0; in bnx2_nvram_write()
4646 if (rc != 0) in bnx2_nvram_write()
4649 cmd_flags = 0; in bnx2_nvram_write()
4665 if (rc != 0) in bnx2_nvram_write()
4668 cmd_flags = 0; in bnx2_nvram_write()
4692 u32 val, sig = 0; in bnx2_init_fw_cap()
4763 for (i = 0; i < 100; i++) { in bnx2_wait_dma_complete()
4779 int i, rc = 0; in bnx2_reset_chip()
4825 for (i = 0; i < 10; i++) { in bnx2_reset_chip()
4828 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) in bnx2_reset_chip()
4842 if (val != 0x01020304) { in bnx2_reset_chip()
4848 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0); in bnx2_reset_chip()
4862 * of this register is 0x0000000e. */ in bnx2_reset_chip()
4863 BNX2_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa); in bnx2_reset_chip()
4897 val |= (0x2 << 20) | (1 << 11); in bnx2_init_chip()
4942 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0); in bnx2_init_chip()
4955 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); in bnx2_init_chip()
4965 val |= (BNX2_PAGE_BITS - 8) << 24 | 0x40; in bnx2_init_chip()
4968 val = bp->mac_addr[0] + in bnx2_init_chip()
4990 memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size); in bnx2_init_chip()
4991 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) in bnx2_init_chip()
4992 bp->bnx2_napi[i].last_status_idx = 0; in bnx2_init_chip()
4994 bp->idle_chk_status_idx = 0xffff; in bnx2_init_chip()
5000 (u64) bp->status_blk_mapping & 0xffffffff); in bnx2_init_chip()
5004 (u64) bp->stats_blk_mapping & 0xffffffff); in bnx2_init_chip()
5028 BNX2_WR(bp, BNX2_HC_STATS_TICKS, 0); in bnx2_init_chip()
5031 BNX2_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ in bnx2_init_chip()
5055 bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 0); in bnx2_init_chip()
5095 1, 0); in bnx2_init_chip()
5115 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { in bnx2_clear_ring_states()
5120 txr->tx_cons = 0; in bnx2_clear_ring_states()
5121 txr->hw_tx_cons = 0; in bnx2_clear_ring_states()
5122 rxr->rx_prod_bseq = 0; in bnx2_clear_ring_states()
5123 rxr->rx_prod = 0; in bnx2_clear_ring_states()
5124 rxr->rx_cons = 0; in bnx2_clear_ring_states()
5125 rxr->rx_pg_prod = 0; in bnx2_clear_ring_states()
5126 rxr->rx_pg_cons = 0; in bnx2_clear_ring_states()
5156 val = (u64) txr->tx_desc_mapping & 0xffffffff; in bnx2_init_tx_context()
5171 if (ring_num == 0) in bnx2_init_tx_ring()
5181 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff; in bnx2_init_tx_ring()
5183 txr->tx_prod = 0; in bnx2_init_tx_ring()
5184 txr->tx_prod_bseq = 0; in bnx2_init_tx_ring()
5199 for (i = 0; i < num_rings; i++) { in bnx2_init_rxbd_rings()
5202 rxbd = &rx_ring[i][0]; in bnx2_init_rxbd_rings()
5203 for (j = 0; j < BNX2_MAX_RX_DESC_CNT; j++, rxbd++) { in bnx2_init_rxbd_rings()
5208 j = 0; in bnx2_init_rxbd_rings()
5212 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff; in bnx2_init_rxbd_rings()
5225 if (ring_num == 0) in bnx2_init_rx_ring()
5242 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0); in bnx2_init_rx_ring()
5252 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32; in bnx2_init_rx_ring()
5255 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff; in bnx2_init_rx_ring()
5262 val = (u64) rxr->rx_desc_mapping[0] >> 32; in bnx2_init_rx_ring()
5265 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff; in bnx2_init_rx_ring()
5269 for (i = 0; i < bp->rx_pg_ring_size; i++) { in bnx2_init_rx_ring()
5270 if (bnx2_alloc_rx_page(bp, rxr, ring_prod, GFP_KERNEL) < 0) { in bnx2_init_rx_ring()
5281 for (i = 0; i < bp->rx_ring_size; i++) { in bnx2_init_rx_ring()
5282 if (bnx2_alloc_rx_data(bp, rxr, ring_prod, GFP_KERNEL) < 0) { in bnx2_init_rx_ring()
5310 BNX2_WR(bp, BNX2_TSCH_TSS_CFG, 0); in bnx2_init_all_rings()
5311 for (i = 0; i < bp->num_tx_rings; i++) in bnx2_init_all_rings()
5318 BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, 0); in bnx2_init_all_rings()
5319 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0); in bnx2_init_all_rings()
5321 for (i = 0; i < bp->num_rx_rings; i++) in bnx2_init_all_rings()
5325 u32 tbl_32 = 0; in bnx2_init_all_rings()
5327 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) { in bnx2_init_all_rings()
5337 tbl_32 = 0; in bnx2_init_all_rings()
5359 while ((max & num_rings) == 0) in bnx2_find_max_ring()
5380 bp->rx_pg_ring_size = 0; in bnx2_set_rx_ring_size()
5381 bp->rx_max_pg_ring = 0; in bnx2_set_rx_ring_size()
5382 bp->rx_max_pg_ring_idx = 0; in bnx2_set_rx_ring_size()
5396 bp->rx_copy_thresh = 0; in bnx2_set_rx_ring_size()
5415 for (i = 0; i < bp->num_tx_rings; i++) { in bnx2_free_tx_skbs()
5423 for (j = 0; j < BNX2_TX_DESC_CNT; ) { in bnx2_free_tx_skbs()
5442 for (k = 0; k < last; k++, j = BNX2_NEXT_TX_BD(j)) { in bnx2_free_tx_skbs()
5460 for (i = 0; i < bp->num_rx_rings; i++) { in bnx2_free_rx_skbs()
5468 for (j = 0; j < bp->rx_max_ring_idx; j++) { in bnx2_free_rx_skbs()
5484 for (j = 0; j < bp->rx_max_pg_ring_idx; j++) in bnx2_free_rx_skbs()
5506 if ((rc = bnx2_init_chip(bp)) != 0) in bnx2_reset_nic()
5510 return 0; in bnx2_reset_nic()
5518 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0) in bnx2_init_nic()
5527 return 0; in bnx2_init_nic()
5557 { 0x006c, 0, 0x00000000, 0x0000003f }, in bnx2_test_registers()
5558 { 0x0090, 0, 0xffffffff, 0x00000000 }, in bnx2_test_registers()
5559 { 0x0094, 0, 0x00000000, 0x00000000 }, in bnx2_test_registers()
5561 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 }, in bnx2_test_registers()
5562 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, in bnx2_test_registers()
5563 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, in bnx2_test_registers()
5564 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff }, in bnx2_test_registers()
5565 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 }, in bnx2_test_registers()
5566 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 }, in bnx2_test_registers()
5567 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff }, in bnx2_test_registers()
5568 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, in bnx2_test_registers()
5569 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, in bnx2_test_registers()
5571 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, in bnx2_test_registers()
5572 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, in bnx2_test_registers()
5573 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, in bnx2_test_registers()
5574 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, in bnx2_test_registers()
5575 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, in bnx2_test_registers()
5576 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, in bnx2_test_registers()
5578 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 }, in bnx2_test_registers()
5579 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 }, in bnx2_test_registers()
5580 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 }, in bnx2_test_registers()
5582 { 0x1000, 0, 0x00000000, 0x00000001 }, in bnx2_test_registers()
5583 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 }, in bnx2_test_registers()
5585 { 0x1408, 0, 0x01c00800, 0x00000000 }, in bnx2_test_registers()
5586 { 0x149c, 0, 0x8000ffff, 0x00000000 }, in bnx2_test_registers()
5587 { 0x14a8, 0, 0x00000000, 0x000001ff }, in bnx2_test_registers()
5588 { 0x14ac, 0, 0x0fffffff, 0x10000000 }, in bnx2_test_registers()
5589 { 0x14b0, 0, 0x00000002, 0x00000001 }, in bnx2_test_registers()
5590 { 0x14b8, 0, 0x00000000, 0x00000000 }, in bnx2_test_registers()
5591 { 0x14c0, 0, 0x00000000, 0x00000009 }, in bnx2_test_registers()
5592 { 0x14c4, 0, 0x00003fff, 0x00000000 }, in bnx2_test_registers()
5593 { 0x14cc, 0, 0x00000000, 0x00000001 }, in bnx2_test_registers()
5594 { 0x14d0, 0, 0xffffffff, 0x00000000 }, in bnx2_test_registers()
5596 { 0x1800, 0, 0x00000000, 0x00000001 }, in bnx2_test_registers()
5597 { 0x1804, 0, 0x00000000, 0x00000003 }, in bnx2_test_registers()
5599 { 0x2800, 0, 0x00000000, 0x00000001 }, in bnx2_test_registers()
5600 { 0x2804, 0, 0x00000000, 0x00003f01 }, in bnx2_test_registers()
5601 { 0x2808, 0, 0x0f3f3f03, 0x00000000 }, in bnx2_test_registers()
5602 { 0x2810, 0, 0xffff0000, 0x00000000 }, in bnx2_test_registers()
5603 { 0x2814, 0, 0xffff0000, 0x00000000 }, in bnx2_test_registers()
5604 { 0x2818, 0, 0xffff0000, 0x00000000 }, in bnx2_test_registers()
5605 { 0x281c, 0, 0xffff0000, 0x00000000 }, in bnx2_test_registers()
5606 { 0x2834, 0, 0xffffffff, 0x00000000 }, in bnx2_test_registers()
5607 { 0x2840, 0, 0x00000000, 0xffffffff }, in bnx2_test_registers()
5608 { 0x2844, 0, 0x00000000, 0xffffffff }, in bnx2_test_registers()
5609 { 0x2848, 0, 0xffffffff, 0x00000000 }, in bnx2_test_registers()
5610 { 0x284c, 0, 0xf800f800, 0x07ff07ff }, in bnx2_test_registers()
5612 { 0x2c00, 0, 0x00000000, 0x00000011 }, in bnx2_test_registers()
5613 { 0x2c04, 0, 0x00000000, 0x00030007 }, in bnx2_test_registers()
5615 { 0x3c00, 0, 0x00000000, 0x00000001 }, in bnx2_test_registers()
5616 { 0x3c04, 0, 0x00000000, 0x00070000 }, in bnx2_test_registers()
5617 { 0x3c08, 0, 0x00007f71, 0x07f00000 }, in bnx2_test_registers()
5618 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 }, in bnx2_test_registers()
5619 { 0x3c10, 0, 0xffffffff, 0x00000000 }, in bnx2_test_registers()
5620 { 0x3c14, 0, 0x00000000, 0xffffffff }, in bnx2_test_registers()
5621 { 0x3c18, 0, 0x00000000, 0xffffffff }, in bnx2_test_registers()
5622 { 0x3c1c, 0, 0xfffff000, 0x00000000 }, in bnx2_test_registers()
5623 { 0x3c20, 0, 0xffffff00, 0x00000000 }, in bnx2_test_registers()
5625 { 0x5004, 0, 0x00000000, 0x0000007f }, in bnx2_test_registers()
5626 { 0x5008, 0, 0x0f0007ff, 0x00000000 }, in bnx2_test_registers()
5628 { 0x5c00, 0, 0x00000000, 0x00000001 }, in bnx2_test_registers()
5629 { 0x5c04, 0, 0x00000000, 0x0003000f }, in bnx2_test_registers()
5630 { 0x5c08, 0, 0x00000003, 0x00000000 }, in bnx2_test_registers()
5631 { 0x5c0c, 0, 0x0000fff8, 0x00000000 }, in bnx2_test_registers()
5632 { 0x5c10, 0, 0x00000000, 0xffffffff }, in bnx2_test_registers()
5633 { 0x5c80, 0, 0x00000000, 0x0f7113f1 }, in bnx2_test_registers()
5634 { 0x5c84, 0, 0x00000000, 0x0000f333 }, in bnx2_test_registers()
5635 { 0x5c88, 0, 0x00000000, 0x00077373 }, in bnx2_test_registers()
5636 { 0x5c8c, 0, 0x00000000, 0x0007f737 }, in bnx2_test_registers()
5638 { 0x6808, 0, 0x0000ff7f, 0x00000000 }, in bnx2_test_registers()
5639 { 0x680c, 0, 0xffffffff, 0x00000000 }, in bnx2_test_registers()
5640 { 0x6810, 0, 0xffffffff, 0x00000000 }, in bnx2_test_registers()
5641 { 0x6814, 0, 0xffffffff, 0x00000000 }, in bnx2_test_registers()
5642 { 0x6818, 0, 0xffffffff, 0x00000000 }, in bnx2_test_registers()
5643 { 0x681c, 0, 0xffffffff, 0x00000000 }, in bnx2_test_registers()
5644 { 0x6820, 0, 0x00ff00ff, 0x00000000 }, in bnx2_test_registers()
5645 { 0x6824, 0, 0x00ff00ff, 0x00000000 }, in bnx2_test_registers()
5646 { 0x6828, 0, 0x00ff00ff, 0x00000000 }, in bnx2_test_registers()
5647 { 0x682c, 0, 0x03ff03ff, 0x00000000 }, in bnx2_test_registers()
5648 { 0x6830, 0, 0x03ff03ff, 0x00000000 }, in bnx2_test_registers()
5649 { 0x6834, 0, 0x03ff03ff, 0x00000000 }, in bnx2_test_registers()
5650 { 0x6838, 0, 0x03ff03ff, 0x00000000 }, in bnx2_test_registers()
5651 { 0x683c, 0, 0x0000ffff, 0x00000000 }, in bnx2_test_registers()
5652 { 0x6840, 0, 0x00000ff0, 0x00000000 }, in bnx2_test_registers()
5653 { 0x6844, 0, 0x00ffff00, 0x00000000 }, in bnx2_test_registers()
5654 { 0x684c, 0, 0xffffffff, 0x00000000 }, in bnx2_test_registers()
5655 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 }, in bnx2_test_registers()
5656 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 }, in bnx2_test_registers()
5657 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 }, in bnx2_test_registers()
5658 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 }, in bnx2_test_registers()
5659 { 0x6908, 0, 0x00000000, 0x0001ff0f }, in bnx2_test_registers()
5660 { 0x690c, 0, 0x00000000, 0x0ffe00f0 }, in bnx2_test_registers()
5662 { 0xffff, 0, 0x00000000, 0x00000000 }, in bnx2_test_registers()
5665 ret = 0; in bnx2_test_registers()
5666 is_5709 = 0; in bnx2_test_registers()
5670 for (i = 0; reg_tbl[i].offset != 0xffff; i++) { in bnx2_test_registers()
5683 writel(0, bp->regview + offset); in bnx2_test_registers()
5686 if ((val & rw_mask) != 0) { in bnx2_test_registers()
5694 writel(0xffffffff, bp->regview + offset); in bnx2_test_registers()
5719 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555, in bnx2_do_mem_test()
5720 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa }; in bnx2_do_mem_test()
5723 for (i = 0; i < sizeof(test_pattern) / 4; i++) { in bnx2_do_mem_test()
5726 for (offset = 0; offset < size; offset += 4) { in bnx2_do_mem_test()
5736 return 0; in bnx2_do_mem_test()
5742 int ret = 0; in bnx2_test_memory()
5748 { 0x60000, 0x4000 }, in bnx2_test_memory()
5749 { 0xa0000, 0x3000 }, in bnx2_test_memory()
5750 { 0xe0000, 0x4000 }, in bnx2_test_memory()
5751 { 0x120000, 0x4000 }, in bnx2_test_memory()
5752 { 0x1a0000, 0x4000 }, in bnx2_test_memory()
5753 { 0x160000, 0x4000 }, in bnx2_test_memory()
5754 { 0xffffffff, 0 }, in bnx2_test_memory()
5757 { 0x60000, 0x4000 }, in bnx2_test_memory()
5758 { 0xa0000, 0x3000 }, in bnx2_test_memory()
5759 { 0xe0000, 0x4000 }, in bnx2_test_memory()
5760 { 0x120000, 0x4000 }, in bnx2_test_memory()
5761 { 0x1a0000, 0x4000 }, in bnx2_test_memory()
5762 { 0xffffffff, 0 }, in bnx2_test_memory()
5771 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) { in bnx2_test_memory()
5773 mem_tbl[i].len)) != 0) { in bnx2_test_memory()
5781 #define BNX2_MAC_LOOPBACK 0
5797 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi; in bnx2_run_loopback()
5811 return 0; in bnx2_run_loopback()
5825 memset(packet + ETH_ALEN, 0x0, 8); in bnx2_run_loopback()
5827 packet[i] = (unsigned char) (i & 0xff); in bnx2_run_loopback()
5844 num_pkts = 0; in bnx2_run_loopback()
5849 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff; in bnx2_run_loopback()
5905 if (*(data + i) != (unsigned char) (i & 0xff)) { in bnx2_run_loopback()
5910 ret = 0; in bnx2_run_loopback()
5913 bp->loopback = 0; in bnx2_run_loopback()
5925 int rc = 0; in bnx2_test_loopback()
5941 #define NVRAM_SIZE 0x200
5942 #define CRC32_RESIDUAL 0xdebb20e3
5949 int rc = 0; in bnx2_test_nvram()
5952 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0) in bnx2_test_nvram()
5955 magic = be32_to_cpu(buf[0]); in bnx2_test_nvram()
5956 if (magic != 0x669955aa) { in bnx2_test_nvram()
5961 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0) in bnx2_test_nvram()
5964 csum = ether_crc_le(0x100, data); in bnx2_test_nvram()
5970 csum = ether_crc_le(0x100, data + 0x100); in bnx2_test_nvram()
5989 return 0; in bnx2_test_link()
6000 return 0; in bnx2_test_link()
6014 status_idx = BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff; in bnx2_test_intr()
6020 for (i = 0; i < 10; i++) { in bnx2_test_intr()
6021 if ((BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) != in bnx2_test_intr()
6030 return 0; in bnx2_test_intr()
6042 return 0; in bnx2_5706_serdes_has_link()
6048 return 0; in bnx2_5706_serdes_has_link()
6055 return 0; in bnx2_5706_serdes_has_link()
6062 return 0; in bnx2_5706_serdes_has_link()
6075 check_link = 0; in bnx2_5706_serdes_timer()
6076 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) { in bnx2_5706_serdes_timer()
6096 bnx2_write_phy(bp, 0x17, 0x0f01); in bnx2_5706_serdes_timer()
6097 bnx2_read_phy(bp, 0x15, &phy2); in bnx2_5706_serdes_timer()
6098 if (phy2 & 0x20) { in bnx2_5706_serdes_timer()
6135 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) { in bnx2_5708_serdes_timer()
6136 bp->serdes_an_pending = 0; in bnx2_5708_serdes_timer()
6143 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) { in bnx2_5708_serdes_timer()
6170 if (atomic_read(&bp->intr_sem) != 0) in bnx2_timer()
6203 int rc = 0, i; in bnx2_request_irq()
6206 flags = 0; in bnx2_request_irq()
6210 for (i = 0; i < bp->irq_nvecs; i++) { in bnx2_request_irq()
6227 for (i = 0; i < bp->irq_nvecs; i++) { in __bnx2_free_irq()
6231 irq->requested = 0; in __bnx2_free_irq()
6254 const int len = sizeof(bp->irq_tbl[0].name); in bnx2_enable_msix()
6265 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { in bnx2_enable_msix()
6267 msix_ent[i].vector = 0; in bnx2_enable_msix()
6276 if (total_vecs < 0) in bnx2_enable_msix()
6285 for (i = 0; i < total_vecs; i++) { in bnx2_enable_msix()
6307 bp->irq_tbl[0].handler = bnx2_interrupt; in bnx2_setup_int_mode()
6308 strcpy(bp->irq_tbl[0].name, bp->dev->name); in bnx2_setup_int_mode()
6310 bp->irq_tbl[0].vector = bp->pdev->irq; in bnx2_setup_int_mode()
6317 if (pci_enable_msi(bp->pdev) == 0) { in bnx2_setup_int_mode()
6321 bp->irq_tbl[0].handler = bnx2_msi_1shot; in bnx2_setup_int_mode()
6323 bp->irq_tbl[0].handler = bnx2_msi; in bnx2_setup_int_mode()
6325 bp->irq_tbl[0].vector = bp->pdev->irq; in bnx2_setup_int_mode()
6352 if (rc < 0) in bnx2_open()
6378 atomic_set(&bp->intr_sem, 0); in bnx2_open()
6380 memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block)); in bnx2_open()
6388 if (bnx2_test_intr(bp) != 0) { in bnx2_open()
6396 rc = bnx2_init_nic(bp, 0); in bnx2_open()
6491 for (i = 0; i < ARRAY_SIZE(ftq_arr); i++) in bnx2_dump_ftq()
6496 for (reg = BNX2_TXP_CPU_MODE; reg <= BNX2_CP_CPU_MODE; reg += 0x40000) in bnx2_dump_ftq()
6501 bnx2_reg_rd_ind(bp, reg + 0x1c), in bnx2_dump_ftq()
6502 bnx2_reg_rd_ind(bp, reg + 0x1c), in bnx2_dump_ftq()
6503 bnx2_reg_rd_ind(bp, reg + 0x20)); in bnx2_dump_ftq()
6510 for (i = 0; i < 0x20; i++) { in bnx2_dump_ftq()
6511 int j = 0; in bnx2_dump_ftq()
6526 bdidx >> 24, (valid >> 8) & 0x0ff); in bnx2_dump_ftq()
6603 vlan_tag_flags = 0; in bnx2_start_xmit()
6627 if (likely(tcp_off == 0)) in bnx2_start_xmit()
6631 vlan_tag_flags |= ((tcp_off & 0x3) << in bnx2_start_xmit()
6633 ((tcp_off & 0x10) << in bnx2_start_xmit()
6635 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL; in bnx2_start_xmit()
6645 mss = 0; in bnx2_start_xmit()
6661 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff; in bnx2_start_xmit()
6669 for (i = 0; i < last_frag; i++) { in bnx2_start_xmit()
6677 mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 0, len, in bnx2_start_xmit()
6685 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff; in bnx2_start_xmit()
6732 for (i = 0; i < last_frag; i++) { in bnx2_start_xmit()
6760 bp->link_up = 0; in bnx2_close()
6762 return 0; in bnx2_close()
6773 for (i = 0; i < 20; i += 2) { in bnx2_save_stats()
6779 if (lo > 0xffffffff) in bnx2_save_stats()
6782 temp_stats[i + 1] = lo & 0xffffffff; in bnx2_save_stats()
6854 net_stats->tx_carrier_errors = 0; in bnx2_get_stats64()
6879 int support_serdes = 0, support_copper = 0; in bnx2_get_link_ksettings()
6939 return 0; in bnx2_get_link_ksettings()
7003 advertising = 0; in bnx2_set_link_ksettings()
7011 err = 0; in bnx2_set_link_ksettings()
7049 0x0000, 0x0098, 0x0400, 0x045c, in bnx2_get_regs()
7050 0x0800, 0x0880, 0x0c00, 0x0c10, in bnx2_get_regs()
7051 0x0c30, 0x0d08, 0x1000, 0x101c, in bnx2_get_regs()
7052 0x1040, 0x1048, 0x1080, 0x10a4, in bnx2_get_regs()
7053 0x1400, 0x1490, 0x1498, 0x14f0, in bnx2_get_regs()
7054 0x1500, 0x155c, 0x1580, 0x15dc, in bnx2_get_regs()
7055 0x1600, 0x1658, 0x1680, 0x16d8, in bnx2_get_regs()
7056 0x1800, 0x1820, 0x1840, 0x1854, in bnx2_get_regs()
7057 0x1880, 0x1894, 0x1900, 0x1984, in bnx2_get_regs()
7058 0x1c00, 0x1c0c, 0x1c40, 0x1c54, in bnx2_get_regs()
7059 0x1c80, 0x1c94, 0x1d00, 0x1d84, in bnx2_get_regs()
7060 0x2000, 0x2030, 0x23c0, 0x2400, in bnx2_get_regs()
7061 0x2800, 0x2820, 0x2830, 0x2850, in bnx2_get_regs()
7062 0x2b40, 0x2c10, 0x2fc0, 0x3058, in bnx2_get_regs()
7063 0x3c00, 0x3c94, 0x4000, 0x4010, in bnx2_get_regs()
7064 0x4080, 0x4090, 0x43c0, 0x4458, in bnx2_get_regs()
7065 0x4c00, 0x4c18, 0x4c40, 0x4c54, in bnx2_get_regs()
7066 0x4fc0, 0x5010, 0x53c0, 0x5444, in bnx2_get_regs()
7067 0x5c00, 0x5c18, 0x5c80, 0x5c90, in bnx2_get_regs()
7068 0x5fc0, 0x6000, 0x6400, 0x6428, in bnx2_get_regs()
7069 0x6800, 0x6848, 0x684c, 0x6860, in bnx2_get_regs()
7070 0x6888, 0x6910, 0x8000 in bnx2_get_regs()
7073 regs->version = 0; in bnx2_get_regs()
7075 memset(p, 0, BNX2_REGDUMP_LEN); in bnx2_get_regs()
7080 i = 0; in bnx2_get_regs()
7081 offset = reg_boundaries[0]; in bnx2_get_regs()
7100 wol->supported = 0; in bnx2_get_wol()
7101 wol->wolopts = 0; in bnx2_get_wol()
7108 wol->wolopts = 0; in bnx2_get_wol()
7110 memset(&wol->sopass, 0, sizeof(wol->sopass)); in bnx2_get_wol()
7128 bp->wol = 0; in bnx2_set_wol()
7133 return 0; in bnx2_set_wol()
7179 return 0; in bnx2_nway_reset()
7196 return 0; in bnx2_get_eeprom_len()
7236 memset(coal, 0, sizeof(struct ethtool_coalesce)); in bnx2_get_coalesce()
7250 return 0; in bnx2_get_coalesce()
7261 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff; in bnx2_set_coalesce()
7264 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff; in bnx2_set_coalesce()
7267 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff; in bnx2_set_coalesce()
7270 if (bp->rx_quick_cons_trip_int > 0xff) in bnx2_set_coalesce()
7271 bp->rx_quick_cons_trip_int = 0xff; in bnx2_set_coalesce()
7274 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff; in bnx2_set_coalesce()
7277 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff; in bnx2_set_coalesce()
7280 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff; in bnx2_set_coalesce()
7283 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int = in bnx2_set_coalesce()
7284 0xff; in bnx2_set_coalesce()
7288 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC) in bnx2_set_coalesce()
7297 bnx2_init_nic(bp, 0); in bnx2_set_coalesce()
7301 return 0; in bnx2_set_coalesce()
7344 int rc = 0; in bnx2_change_ring_size()
7358 rc = bnx2_init_nic(bp, 0); in bnx2_change_ring_size()
7374 return 0; in bnx2_change_ring_size()
7401 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0); in bnx2_get_pauseparam()
7402 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0); in bnx2_get_pauseparam()
7403 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0); in bnx2_get_pauseparam()
7411 bp->req_flow_ctrl = 0; in bnx2_set_pauseparam()
7430 return 0; in bnx2_set_pauseparam()
7543 8,0,8,8,8,8,8,8,8,8,
7544 4,0,4,4,4,4,4,4,4,4,
7551 8,0,8,8,8,8,8,8,8,8,
7589 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS); in bnx2_self_test()
7597 if (bnx2_test_registers(bp) != 0) { in bnx2_self_test()
7598 buf[0] = 1; in bnx2_self_test()
7601 if (bnx2_test_memory(bp) != 0) { in bnx2_self_test()
7605 if ((buf[2] = bnx2_test_loopback(bp)) != 0) in bnx2_self_test()
7616 for (i = 0; i < 7; i++) { in bnx2_self_test()
7623 if (bnx2_test_nvram(bp) != 0) { in bnx2_self_test()
7627 if (bnx2_test_intr(bp) != 0) { in bnx2_self_test()
7632 if (bnx2_test_link(bp) != 0) { in bnx2_self_test()
7665 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS); in bnx2_get_ethtool_stats()
7677 for (i = 0; i < BNX2_NUM_STATS; i++) { in bnx2_get_ethtool_stats()
7680 if (stats_len_arr[i] == 0) { in bnx2_get_ethtool_stats()
7682 buf[i] = 0; in bnx2_get_ethtool_stats()
7726 BNX2_WR(bp, BNX2_EMAC_LED, 0); in bnx2_set_phys_id()
7731 return 0; in bnx2_set_phys_id()
7751 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1); in bnx2_set_features()
7756 return 0; in bnx2_set_features()
7773 channels->max_other = 0; in bnx2_get_channels()
7774 channels->max_combined = 0; in bnx2_get_channels()
7777 channels->other_count = 0; in bnx2_get_channels()
7778 channels->combined_count = 0; in bnx2_get_channels()
7787 int rc = 0; in bnx2_set_channels()
7863 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval); in bnx2_ioctl()
7879 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in); in bnx2_ioctl()
7903 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0); in bnx2_change_mac_addr()
7905 return 0; in bnx2_change_mac_addr()
7926 for (i = 0; i < bp->irq_nvecs; i++) { in poll_bnx2()
7955 if (bp->func == 0) { in bnx2_get_5709_media()
7957 case 0x4: in bnx2_get_5709_media()
7958 case 0x5: in bnx2_get_5709_media()
7959 case 0x6: in bnx2_get_5709_media()
7965 case 0x1: in bnx2_get_5709_media()
7966 case 0x2: in bnx2_get_5709_media()
7967 case 0x4: in bnx2_get_5709_media()
8033 #define BNX2_VPD_NVRAM_OFFSET 0x300 in bnx2_read_vpd_fw_ver()
8045 for (i = 0; i < BNX2_VPD_LEN; i += 4) in bnx2_read_vpd_fw_ver()
8050 if (j < 0) in bnx2_read_vpd_fw_ver()
8059 if (j < 0) in bnx2_read_vpd_fw_ver()
8083 bp->flags = 0; in bnx2_init_board()
8084 bp->phy_flags = 0; in bnx2_init_board()
8101 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { in bnx2_init_board()
8117 if (bp->pm_cap == 0) { in bnx2_init_board()
8134 bp->regview = pci_iomap(pdev, 0, MB_GET_CID_ADDR(TX_TSS_CID + in bnx2_init_board()
8163 if (bp->pcix_cap == 0) { in bnx2_init_board()
8191 if (dma_set_mask(&pdev->dev, dma_mask) == 0) { in bnx2_init_board()
8199 } else if ((rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) != 0) { in bnx2_init_board()
8251 for (i = 0; i < 3 && j < 24; i++) { in bnx2_init_board()
8254 if (i == 0) { in bnx2_init_board()
8262 bp->fw_version[j++] = (num / k) + '0'; in bnx2_init_board()
8263 skip0 = 0; in bnx2_init_board()
8276 for (i = 0; i < 30; i++) { in bnx2_init_board()
8291 for (i = 0; i < 3 && j < 28; i++) { in bnx2_init_board()
8300 bp->mac_addr[0] = (u8) (reg >> 8); in bnx2_init_board()
8345 bp->wol = 0; in bnx2_init_board()
8353 pdev->subsystem_device == 0x310c) in bnx2_init_board()
8375 bp->wol = 0; in bnx2_init_board()
8405 if (BNX2_CHIP(bp) == BNX2_CHIP_5706 && disable_msi == 0) { in bnx2_init_board()
8412 if (amd_8132->revision >= 0x10 && in bnx2_init_board()
8413 amd_8132->revision <= 0x13) { in bnx2_init_board()
8424 timer_setup(&bp->timer, bnx2_timer, 0); in bnx2_init_board()
8436 return 0; in bnx2_init_board()
8479 for (i = 0; i < bp->irq_nvecs; i++) in bnx2_del_napi()
8488 for (i = 0; i < bp->irq_nvecs; i++) { in bnx2_init_napi()
8492 if (i == 0) in bnx2_init_napi()
8533 if (rc < 0) in bnx2_init_one()
8579 ((BNX2_CHIP_ID(bp) & 0xf000) >> 12) + 'A', in bnx2_init_one()
8580 ((BNX2_CHIP_ID(bp) & 0x0ff0) >> 4), in bnx2_init_one()
8581 bnx2_bus_string(bp, str), (long)pci_resource_start(pdev, 0), in bnx2_init_one()
8584 return 0; in bnx2_init_one()
8637 return 0; in bnx2_suspend()
8647 return 0; in bnx2_resume()
8654 return 0; in bnx2_resume()
8711 int err = 0; in bnx2_io_slot_reset()