Lines Matching +full:data +full:- +full:addr
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Applied Micro X-Gene SoC Ethernet Driver
18 void __iomem *addr = pdata->eth_csr_addr + offset; in xgene_enet_wr_csr() local
20 iowrite32(val, addr); in xgene_enet_wr_csr()
26 void __iomem *addr = pdata->eth_ring_if_addr + offset; in xgene_enet_wr_ring_if() local
28 iowrite32(val, addr); in xgene_enet_wr_ring_if()
34 void __iomem *addr = pdata->eth_diag_csr_addr + offset; in xgene_enet_wr_diag_csr() local
36 iowrite32(val, addr); in xgene_enet_wr_diag_csr()
39 static bool xgene_enet_wr_indirect(void __iomem *addr, void __iomem *wr, in xgene_enet_wr_indirect() argument
46 iowrite32(wr_addr, addr); in xgene_enet_wr_indirect()
51 while (!(done = ioread32(cmd_done)) && wait--) in xgene_enet_wr_indirect()
65 void __iomem *addr, *wr, *cmd, *cmd_done; in xgene_enet_wr_pcs() local
67 addr = pdata->pcs_addr + PCS_ADDR_REG_OFFSET; in xgene_enet_wr_pcs()
68 wr = pdata->pcs_addr + PCS_WRITE_REG_OFFSET; in xgene_enet_wr_pcs()
69 cmd = pdata->pcs_addr + PCS_COMMAND_REG_OFFSET; in xgene_enet_wr_pcs()
70 cmd_done = pdata->pcs_addr + PCS_COMMAND_DONE_REG_OFFSET; in xgene_enet_wr_pcs()
72 if (!xgene_enet_wr_indirect(addr, wr, cmd, cmd_done, wr_addr, wr_data)) in xgene_enet_wr_pcs()
73 netdev_err(pdata->ndev, "PCS write failed, addr: %04x\n", in xgene_enet_wr_pcs()
80 void __iomem *addr = pdata->mcx_mac_csr_addr + offset; in xgene_enet_wr_axg_csr() local
82 iowrite32(val, addr); in xgene_enet_wr_axg_csr()
88 void __iomem *addr = pdata->eth_csr_addr + offset; in xgene_enet_rd_csr() local
90 *val = ioread32(addr); in xgene_enet_rd_csr()
96 void __iomem *addr = pdata->eth_diag_csr_addr + offset; in xgene_enet_rd_diag_csr() local
98 *val = ioread32(addr); in xgene_enet_rd_diag_csr()
101 static bool xgene_enet_rd_indirect(void __iomem *addr, void __iomem *rd, in xgene_enet_rd_indirect() argument
108 iowrite32(rd_addr, addr); in xgene_enet_rd_indirect()
112 while (!(done = ioread32(cmd_done)) && wait--) in xgene_enet_rd_indirect()
127 void __iomem *addr, *rd, *cmd, *cmd_done; in xgene_enet_rd_pcs() local
130 addr = pdata->pcs_addr + PCS_ADDR_REG_OFFSET; in xgene_enet_rd_pcs()
131 rd = pdata->pcs_addr + PCS_READ_REG_OFFSET; in xgene_enet_rd_pcs()
132 cmd = pdata->pcs_addr + PCS_COMMAND_REG_OFFSET; in xgene_enet_rd_pcs()
133 cmd_done = pdata->pcs_addr + PCS_COMMAND_DONE_REG_OFFSET; in xgene_enet_rd_pcs()
135 success = xgene_enet_rd_indirect(addr, rd, cmd, cmd_done, rd_addr, rd_data); in xgene_enet_rd_pcs()
137 netdev_err(pdata->ndev, "PCS read failed, addr: %04x\n", in xgene_enet_rd_pcs()
146 void __iomem *addr = pdata->mcx_mac_csr_addr + offset; in xgene_enet_rd_axg_csr() local
148 *val = ioread32(addr); in xgene_enet_rd_axg_csr()
153 struct net_device *ndev = pdata->ndev; in xgene_enet_ecc_init()
154 u32 data; in xgene_enet_ecc_init() local
160 xgene_enet_rd_diag_csr(pdata, ENET_BLOCK_MEM_RDY_ADDR, &data); in xgene_enet_ecc_init()
161 } while ((data != 0xffffffff) && wait--); in xgene_enet_ecc_init()
163 if (data != 0xffffffff) { in xgene_enet_ecc_init()
165 return -ENODEV; in xgene_enet_ecc_init()
179 /* Errata: 10GE_4 - ICM_ECM_DROP_COUNT not clear-on-read */ in xgene_xgmac_get_drop_cnt()
199 u32 data; in xgene_pcs_reset() local
201 if (!xgene_enet_rd_pcs(pdata, PCS_CONTROL_1, &data)) in xgene_pcs_reset()
204 xgene_enet_wr_pcs(pdata, PCS_CONTROL_1, data | PCS_CTRL_PCS_RST); in xgene_pcs_reset()
205 xgene_enet_wr_pcs(pdata, PCS_CONTROL_1, data & ~PCS_CTRL_PCS_RST); in xgene_pcs_reset()
210 const u8 *dev_addr = pdata->ndev->dev_addr; in xgene_xgmac_set_mac_addr()
225 u32 data; in xgene_xgmac_set_mss() local
228 xgene_enet_rd_csr(pdata, XG_TSIF_MSS_REG0_ADDR + offset, &data); in xgene_xgmac_set_mss()
231 data = SET_VAL(TSO_MSS1, data >> TSO_MSS1_POS) | in xgene_xgmac_set_mss()
234 data = SET_VAL(TSO_MSS1, mss) | SET_VAL(TSO_MSS0, data); in xgene_xgmac_set_mss()
236 xgene_enet_wr_csr(pdata, XG_TSIF_MSS_REG0_ADDR + offset, data); in xgene_xgmac_set_mss()
247 u32 data; in xgene_enet_link_status() local
249 xgene_enet_rd_csr(pdata, XG_LINK_STATUS_ADDR, &data); in xgene_enet_link_status()
251 return data; in xgene_enet_link_status()
257 u32 data; in xgene_xgmac_enable_tx_pause() local
259 xgene_enet_rd_axg_csr(pdata, XGENET_CSR_ECM_CFG_0_ADDR, &data); in xgene_xgmac_enable_tx_pause()
262 data |= MULTI_DPF_AUTOCTRL | PAUSE_XON_EN; in xgene_xgmac_enable_tx_pause()
264 data &= ~(MULTI_DPF_AUTOCTRL | PAUSE_XON_EN); in xgene_xgmac_enable_tx_pause()
266 xgene_enet_wr_axg_csr(pdata, XGENET_CSR_ECM_CFG_0_ADDR, data); in xgene_xgmac_enable_tx_pause()
271 u32 data; in xgene_xgmac_flowctl_tx() local
273 data = xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1); in xgene_xgmac_flowctl_tx()
276 data |= HSTTCTLEN; in xgene_xgmac_flowctl_tx()
278 data &= ~HSTTCTLEN; in xgene_xgmac_flowctl_tx()
280 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data); in xgene_xgmac_flowctl_tx()
282 pdata->mac_ops->enable_tx_pause(pdata, enable); in xgene_xgmac_flowctl_tx()
287 u32 data; in xgene_xgmac_flowctl_rx() local
289 data = xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1); in xgene_xgmac_flowctl_rx()
292 data |= HSTRCTLEN; in xgene_xgmac_flowctl_rx()
294 data &= ~HSTRCTLEN; in xgene_xgmac_flowctl_rx()
296 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data); in xgene_xgmac_flowctl_rx()
301 u32 data; in xgene_xgmac_init() local
305 data = xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1); in xgene_xgmac_init()
306 data |= HSTPPEN; in xgene_xgmac_init()
307 data &= ~HSTLENCHK; in xgene_xgmac_init()
308 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data); in xgene_xgmac_init()
312 xgene_enet_rd_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, &data); in xgene_xgmac_init()
313 data |= CFG_RSIF_FPBUFF_TIMEOUT_EN; in xgene_xgmac_init()
314 /* Errata 10GE_1 - FIFO threshold default value incorrect */ in xgene_xgmac_init()
315 RSIF_CLE_BUFF_THRESH_SET(&data, XG_RSIF_CLE_BUFF_THRESH); in xgene_xgmac_init()
316 xgene_enet_wr_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, data); in xgene_xgmac_init()
318 /* Errata 10GE_1 - FIFO threshold default value incorrect */ in xgene_xgmac_init()
319 xgene_enet_rd_csr(pdata, XG_RSIF_CONFIG1_REG_ADDR, &data); in xgene_xgmac_init()
320 RSIF_PLC_CLE_BUFF_THRESH_SET(&data, XG_RSIF_PLC_CLE_BUFF_THRESH); in xgene_xgmac_init()
321 xgene_enet_wr_csr(pdata, XG_RSIF_CONFIG1_REG_ADDR, data); in xgene_xgmac_init()
323 xgene_enet_rd_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, &data); in xgene_xgmac_init()
324 data |= BIT(12); in xgene_xgmac_init()
325 xgene_enet_wr_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, data); in xgene_xgmac_init()
331 xgene_enet_rd_axg_csr(pdata, XGENET_CSR_MULTI_DPF0_ADDR, &data); in xgene_xgmac_init()
332 data = (DEF_QUANTA << 16) | (data & 0xFFFF); in xgene_xgmac_init()
333 xgene_enet_wr_axg_csr(pdata, XGENET_CSR_MULTI_DPF0_ADDR, data); in xgene_xgmac_init()
335 if (pdata->enet_id != XGENE_ENET1) { in xgene_xgmac_init()
336 xgene_enet_rd_axg_csr(pdata, XGENET_CSR_MULTI_DPF1_ADDR, &data); in xgene_xgmac_init()
337 data = (NORM_PAUSE_OPCODE << 16) | (data & 0xFFFF); in xgene_xgmac_init()
338 xgene_enet_wr_axg_csr(pdata, XGENET_CSR_MULTI_DPF1_ADDR, data); in xgene_xgmac_init()
341 data = (XG_DEF_PAUSE_OFF_THRES << 16) | XG_DEF_PAUSE_THRES; in xgene_xgmac_init()
342 xgene_enet_wr_csr(pdata, XG_RXBUF_PAUSE_THRESH, data); in xgene_xgmac_init()
344 xgene_xgmac_flowctl_tx(pdata, pdata->tx_pause); in xgene_xgmac_init()
345 xgene_xgmac_flowctl_rx(pdata, pdata->rx_pause); in xgene_xgmac_init()
350 u32 data; in xgene_xgmac_rx_enable() local
352 data = xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1); in xgene_xgmac_rx_enable()
353 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data | HSTRFEN); in xgene_xgmac_rx_enable()
358 u32 data; in xgene_xgmac_tx_enable() local
360 data = xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1); in xgene_xgmac_tx_enable()
361 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data | HSTTFEN); in xgene_xgmac_tx_enable()
366 u32 data; in xgene_xgmac_rx_disable() local
368 data = xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1); in xgene_xgmac_rx_disable()
369 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data & ~HSTRFEN); in xgene_xgmac_rx_disable()
374 u32 data; in xgene_xgmac_tx_disable() local
376 data = xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1); in xgene_xgmac_tx_disable()
377 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data & ~HSTTFEN); in xgene_xgmac_tx_disable()
382 struct device *dev = &pdata->pdev->dev; in xgene_enet_reset()
385 return -ENODEV; in xgene_enet_reset()
387 if (dev->of_node) { in xgene_enet_reset()
388 clk_prepare_enable(pdata->clk); in xgene_enet_reset()
390 clk_disable_unprepare(pdata->clk); in xgene_enet_reset()
392 clk_prepare_enable(pdata->clk); in xgene_enet_reset()
398 status = acpi_evaluate_object(ACPI_HANDLE(&pdata->pdev->dev), in xgene_enet_reset()
401 acpi_evaluate_object(ACPI_HANDLE(&pdata->pdev->dev), in xgene_enet_reset()
436 struct device *dev = &pdata->pdev->dev; in xgene_enet_shutdown()
438 if (dev->of_node) { in xgene_enet_shutdown()
439 if (!IS_ERR(pdata->clk)) in xgene_enet_shutdown()
440 clk_disable_unprepare(pdata->clk); in xgene_enet_shutdown()
447 u32 addr, data; in xgene_enet_clear() local
449 if (xgene_enet_is_bufpool(ring->id)) { in xgene_enet_clear()
450 addr = ENET_CFGSSQMIFPRESET_ADDR; in xgene_enet_clear()
451 data = BIT(xgene_enet_get_fpsel(ring->id)); in xgene_enet_clear()
453 addr = ENET_CFGSSQMIWQRESET_ADDR; in xgene_enet_clear()
454 data = BIT(xgene_enet_ring_bufnum(ring->id)); in xgene_enet_clear()
457 xgene_enet_wr_ring_if(pdata, addr, data); in xgene_enet_clear()
462 struct device *dev = &pdata->pdev->dev; in xgene_enet_gpio_lookup()
464 pdata->sfp_rdy = gpiod_get(dev, "rxlos", GPIOD_IN); in xgene_enet_gpio_lookup()
465 if (IS_ERR(pdata->sfp_rdy)) in xgene_enet_gpio_lookup()
466 pdata->sfp_rdy = gpiod_get(dev, "sfp", GPIOD_IN); in xgene_enet_gpio_lookup()
468 if (IS_ERR(pdata->sfp_rdy)) in xgene_enet_gpio_lookup()
469 return -ENODEV; in xgene_enet_gpio_lookup()
478 struct net_device *ndev = pdata->ndev; in xgene_enet_link_state()
482 if (pdata->sfp_gpio_en && link_status && in xgene_enet_link_state()
483 (!IS_ERR(pdata->sfp_rdy) || !xgene_enet_gpio_lookup(pdata)) && in xgene_enet_link_state()
484 !gpiod_get_value(pdata->sfp_rdy)) in xgene_enet_link_state()
492 netdev_info(ndev, "Link is Up - 10Gbps\n"); in xgene_enet_link_state()
507 schedule_delayed_work(&pdata->link_work, poll_interval); in xgene_enet_link_state()