Lines Matching +full:48 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* Applied Micro X-Gene SoC Ethernet Driver
22 u32 end = start + len - 1; in xgene_set_bits()
41 #define OVERWRITE BIT(31)
42 #define IS_BUFFER_POOL BIT(20)
43 #define PREFETCH_BUF_EN BIT(21)
61 #define CREATE_MASK(pos, len) GENMASK((pos)+(len)-1, (pos))
62 #define CREATE_MASK_ULL(pos, len) GENMASK_ULL((pos)+(len)-1, (pos))
92 #define ACCEPTLERR BIT(19)
93 #define QCOHERENT BIT(4)
94 #define RECOMBBUF BIT(27)
137 #define BUSY_MASK BIT(0)
138 #define READ_CYCLE_MASK BIT(0)
150 #define CFG_RSIF_FPBUFF_TIMEOUT_EN BIT(31)
151 #define RESUME_TX BIT(0)
152 #define CFG_SPEED_1250 BIT(24)
153 #define TX_PORT0 BIT(0)
154 #define CFG_BYPASS_UNISEC_TX BIT(2)
155 #define CFG_BYPASS_UNISEC_RX BIT(1)
156 #define CFG_CLE_BYPASS_EN0 BIT(31)
178 #define PAUSE_XON_EN BIT(30)
179 #define MULTI_DPF_AUTOCTRL BIT(28)
188 #define TX_DV_GATE_EN0 BIT(2)
189 #define RX_DV_GATE_EN0 BIT(1)
190 #define RESUME_RX0 BIT(0)
209 #define SOFT_RESET1 BIT(31)
210 #define TX_EN BIT(0)
211 #define RX_EN BIT(2)
212 #define TX_FLOW_EN BIT(4)
213 #define RX_FLOW_EN BIT(5)
214 #define ENET_LHD_MODE BIT(25)
215 #define ENET_GHD_MODE BIT(26)
216 #define FULL_DUPLEX2 BIT(0)
217 #define PAD_CRC BIT(2)
218 #define LENGTH_CHK BIT(4)
283 #define BUFDATALEN_POS 48
288 #define HENQNUM_POS 48
309 #define LL_BYTES_LSB_POS 48
311 #define LL_LEN_POS 48
409 return xgene_enet_ring_bufnum(id) - RING_BUFNUM_BUFPOOL; in xgene_enet_get_fpsel()