Lines Matching +full:burst +full:- +full:wrap

1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
3 * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
15 head_masked = io_cq->head & (io_cq->q_depth - 1); in ena_com_get_next_rx_cdesc()
16 expected_phase = io_cq->phase; in ena_com_get_next_rx_cdesc()
18 cdesc = (struct ena_eth_io_rx_cdesc_base *)(io_cq->cdesc_addr.virt_addr in ena_com_get_next_rx_cdesc()
19 + (head_masked * io_cq->cdesc_entry_size_in_bytes)); in ena_com_get_next_rx_cdesc()
21 desc_phase = (READ_ONCE(cdesc->status) & in ena_com_get_next_rx_cdesc()
41 tail_masked = io_sq->tail & (io_sq->q_depth - 1); in get_sq_desc_regular_queue()
43 offset = tail_masked * io_sq->desc_entry_size; in get_sq_desc_regular_queue()
45 return (void *)((uintptr_t)io_sq->desc_addr.virt_addr + offset); in get_sq_desc_regular_queue()
51 struct ena_com_llq_info *llq_info = &io_sq->llq_info; in ena_com_write_bounce_buffer_to_dev()
56 dst_tail_mask = io_sq->tail & (io_sq->q_depth - 1); in ena_com_write_bounce_buffer_to_dev()
57 dst_offset = dst_tail_mask * llq_info->desc_list_entry_size; in ena_com_write_bounce_buffer_to_dev()
60 if (unlikely(!io_sq->entries_in_tx_burst_left)) { in ena_com_write_bounce_buffer_to_dev()
61 netdev_err(ena_com_io_sq_to_ena_dev(io_sq)->net_device, in ena_com_write_bounce_buffer_to_dev()
62 "Error: trying to send more packets than tx burst allows\n"); in ena_com_write_bounce_buffer_to_dev()
63 return -ENOSPC; in ena_com_write_bounce_buffer_to_dev()
66 io_sq->entries_in_tx_burst_left--; in ena_com_write_bounce_buffer_to_dev()
67 netdev_dbg(ena_com_io_sq_to_ena_dev(io_sq)->net_device, in ena_com_write_bounce_buffer_to_dev()
69 io_sq->qid, io_sq->entries_in_tx_burst_left); in ena_com_write_bounce_buffer_to_dev()
78 __iowrite64_copy(io_sq->desc_addr.pbuf_dev_addr + dst_offset, in ena_com_write_bounce_buffer_to_dev()
79 bounce_buffer, (llq_info->desc_list_entry_size) / 8); in ena_com_write_bounce_buffer_to_dev()
81 io_sq->tail++; in ena_com_write_bounce_buffer_to_dev()
83 /* Switch phase bit in case of wrap around */ in ena_com_write_bounce_buffer_to_dev()
84 if (unlikely((io_sq->tail & (io_sq->q_depth - 1)) == 0)) in ena_com_write_bounce_buffer_to_dev()
85 io_sq->phase ^= 1; in ena_com_write_bounce_buffer_to_dev()
94 struct ena_com_llq_pkt_ctrl *pkt_ctrl = &io_sq->llq_buf_ctrl; in ena_com_write_header_to_bounce()
95 struct ena_com_llq_info *llq_info = &io_sq->llq_info; in ena_com_write_header_to_bounce()
96 u8 *bounce_buffer = pkt_ctrl->curr_bounce_buf; in ena_com_write_header_to_bounce()
99 if (unlikely(io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)) in ena_com_write_header_to_bounce()
103 llq_info->descs_num_before_header * io_sq->desc_entry_size; in ena_com_write_header_to_bounce()
106 llq_info->desc_list_entry_size)) { in ena_com_write_header_to_bounce()
107 netdev_err(ena_com_io_sq_to_ena_dev(io_sq)->net_device, in ena_com_write_header_to_bounce()
109 return -EFAULT; in ena_com_write_header_to_bounce()
113 netdev_err(ena_com_io_sq_to_ena_dev(io_sq)->net_device, in ena_com_write_header_to_bounce()
115 return -EFAULT; in ena_com_write_header_to_bounce()
125 struct ena_com_llq_pkt_ctrl *pkt_ctrl = &io_sq->llq_buf_ctrl; in get_sq_desc_llq()
129 bounce_buffer = pkt_ctrl->curr_bounce_buf; in get_sq_desc_llq()
132 netdev_err(ena_com_io_sq_to_ena_dev(io_sq)->net_device, in get_sq_desc_llq()
137 sq_desc = bounce_buffer + pkt_ctrl->idx * io_sq->desc_entry_size; in get_sq_desc_llq()
138 pkt_ctrl->idx++; in get_sq_desc_llq()
139 pkt_ctrl->descs_left_in_line--; in get_sq_desc_llq()
146 struct ena_com_llq_pkt_ctrl *pkt_ctrl = &io_sq->llq_buf_ctrl; in ena_com_close_bounce_buffer()
147 struct ena_com_llq_info *llq_info = &io_sq->llq_info; in ena_com_close_bounce_buffer()
150 if (unlikely(io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)) in ena_com_close_bounce_buffer()
154 if (likely(pkt_ctrl->idx)) { in ena_com_close_bounce_buffer()
156 pkt_ctrl->curr_bounce_buf); in ena_com_close_bounce_buffer()
158 netdev_err(ena_com_io_sq_to_ena_dev(io_sq)->net_device, in ena_com_close_bounce_buffer()
163 pkt_ctrl->curr_bounce_buf = in ena_com_close_bounce_buffer()
164 ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl); in ena_com_close_bounce_buffer()
165 memset(io_sq->llq_buf_ctrl.curr_bounce_buf, in ena_com_close_bounce_buffer()
166 0x0, llq_info->desc_list_entry_size); in ena_com_close_bounce_buffer()
169 pkt_ctrl->idx = 0; in ena_com_close_bounce_buffer()
170 pkt_ctrl->descs_left_in_line = llq_info->descs_num_before_header; in ena_com_close_bounce_buffer()
176 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) in get_sq_desc()
184 struct ena_com_llq_pkt_ctrl *pkt_ctrl = &io_sq->llq_buf_ctrl; in ena_com_sq_update_llq_tail()
185 struct ena_com_llq_info *llq_info = &io_sq->llq_info; in ena_com_sq_update_llq_tail()
188 if (!pkt_ctrl->descs_left_in_line) { in ena_com_sq_update_llq_tail()
190 pkt_ctrl->curr_bounce_buf); in ena_com_sq_update_llq_tail()
192 netdev_err(ena_com_io_sq_to_ena_dev(io_sq)->net_device, in ena_com_sq_update_llq_tail()
197 pkt_ctrl->curr_bounce_buf = in ena_com_sq_update_llq_tail()
198 ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl); in ena_com_sq_update_llq_tail()
199 memset(io_sq->llq_buf_ctrl.curr_bounce_buf, in ena_com_sq_update_llq_tail()
200 0x0, llq_info->desc_list_entry_size); in ena_com_sq_update_llq_tail()
202 pkt_ctrl->idx = 0; in ena_com_sq_update_llq_tail()
203 if (unlikely(llq_info->desc_stride_ctrl == ENA_ADMIN_SINGLE_DESC_PER_ENTRY)) in ena_com_sq_update_llq_tail()
204 pkt_ctrl->descs_left_in_line = 1; in ena_com_sq_update_llq_tail()
206 pkt_ctrl->descs_left_in_line = in ena_com_sq_update_llq_tail()
207 llq_info->desc_list_entry_size / io_sq->desc_entry_size; in ena_com_sq_update_llq_tail()
215 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) in ena_com_sq_update_tail()
218 io_sq->tail++; in ena_com_sq_update_tail()
220 /* Switch phase bit in case of wrap around */ in ena_com_sq_update_tail()
221 if (unlikely((io_sq->tail & (io_sq->q_depth - 1)) == 0)) in ena_com_sq_update_tail()
222 io_sq->phase ^= 1; in ena_com_sq_update_tail()
230 idx &= (io_cq->q_depth - 1); in ena_com_rx_cdesc_idx_to_ptr()
232 ((uintptr_t)io_cq->cdesc_addr.virt_addr + in ena_com_rx_cdesc_idx_to_ptr()
233 idx * io_cq->cdesc_entry_size_in_bytes); in ena_com_rx_cdesc_idx_to_ptr()
250 last = (READ_ONCE(cdesc->status) & in ena_com_cdesc_rx_pkt_get()
256 *first_cdesc_idx = io_cq->cur_rx_pkt_cdesc_start_idx; in ena_com_cdesc_rx_pkt_get()
257 count += io_cq->cur_rx_pkt_cdesc_count; in ena_com_cdesc_rx_pkt_get()
259 head_masked = io_cq->head & (io_cq->q_depth - 1); in ena_com_cdesc_rx_pkt_get()
261 io_cq->cur_rx_pkt_cdesc_count = 0; in ena_com_cdesc_rx_pkt_get()
262 io_cq->cur_rx_pkt_cdesc_start_idx = head_masked; in ena_com_cdesc_rx_pkt_get()
264 netdev_dbg(ena_com_io_cq_to_ena_dev(io_cq)->net_device, in ena_com_cdesc_rx_pkt_get()
266 io_cq->qid, *first_cdesc_idx, count); in ena_com_cdesc_rx_pkt_get()
268 io_cq->cur_rx_pkt_cdesc_count += count; in ena_com_cdesc_rx_pkt_get()
282 return -EFAULT; in ena_com_create_meta()
286 meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_META_DESC_MASK; in ena_com_create_meta()
288 meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK; in ena_com_create_meta()
290 /* bits 0-9 of the mss */ in ena_com_create_meta()
291 meta_desc->word2 |= ((u32)ena_meta->mss << in ena_com_create_meta()
294 /* bits 10-13 of the mss */ in ena_com_create_meta()
295 meta_desc->len_ctrl |= ((ena_meta->mss >> 10) << in ena_com_create_meta()
300 meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK; in ena_com_create_meta()
301 meta_desc->len_ctrl |= ((u32)io_sq->phase << in ena_com_create_meta()
305 meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_FIRST_MASK; in ena_com_create_meta()
306 meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_META_STORE_MASK; in ena_com_create_meta()
308 meta_desc->word2 |= ena_meta->l3_hdr_len & in ena_com_create_meta()
310 meta_desc->word2 |= (ena_meta->l3_hdr_offset << in ena_com_create_meta()
314 meta_desc->word2 |= ((u32)ena_meta->l4_hdr_len << in ena_com_create_meta()
325 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta; in ena_com_create_and_store_tx_meta_desc()
330 if (io_sq->disable_meta_caching) { in ena_com_create_and_store_tx_meta_desc()
338 memcpy(&io_sq->cached_tx_meta, ena_meta, in ena_com_create_and_store_tx_meta_desc()
351 ena_rx_ctx->l3_proto = cdesc->status & in ena_com_rx_set_flags()
353 ena_rx_ctx->l4_proto = in ena_com_rx_set_flags()
354 (cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK) >> in ena_com_rx_set_flags()
356 ena_rx_ctx->l3_csum_err = in ena_com_rx_set_flags()
357 !!((cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK) >> in ena_com_rx_set_flags()
359 ena_rx_ctx->l4_csum_err = in ena_com_rx_set_flags()
360 !!((cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK) >> in ena_com_rx_set_flags()
362 ena_rx_ctx->l4_csum_checked = in ena_com_rx_set_flags()
363 !!((cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK) >> in ena_com_rx_set_flags()
365 ena_rx_ctx->hash = cdesc->hash; in ena_com_rx_set_flags()
366 ena_rx_ctx->frag = in ena_com_rx_set_flags()
367 (cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK) >> in ena_com_rx_set_flags()
370 netdev_dbg(ena_com_io_cq_to_ena_dev(io_cq)->net_device, in ena_com_rx_set_flags()
372 ena_rx_ctx->l3_proto, ena_rx_ctx->l4_proto, in ena_com_rx_set_flags()
373 ena_rx_ctx->l3_csum_err, ena_rx_ctx->l4_csum_err, in ena_com_rx_set_flags()
374 ena_rx_ctx->hash, ena_rx_ctx->frag, cdesc->status); in ena_com_rx_set_flags()
386 struct ena_com_buf *ena_bufs = ena_tx_ctx->ena_bufs; in ena_com_prepare_tx()
387 void *buffer_to_push = ena_tx_ctx->push_header; in ena_com_prepare_tx()
388 u16 header_len = ena_tx_ctx->header_len; in ena_com_prepare_tx()
389 u16 num_bufs = ena_tx_ctx->num_bufs; in ena_com_prepare_tx()
390 u16 start_tail = io_sq->tail; in ena_com_prepare_tx()
395 WARN(io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_TX, "wrong Q type"); in ena_com_prepare_tx()
399 netdev_dbg(ena_com_io_sq_to_ena_dev(io_sq)->net_device, in ena_com_prepare_tx()
401 return -ENOMEM; in ena_com_prepare_tx()
404 if (unlikely(header_len > io_sq->tx_max_header_size)) { in ena_com_prepare_tx()
405 netdev_err(ena_com_io_sq_to_ena_dev(io_sq)->net_device, in ena_com_prepare_tx()
407 header_len, io_sq->tx_max_header_size); in ena_com_prepare_tx()
408 return -EINVAL; in ena_com_prepare_tx()
411 if (unlikely(io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV && in ena_com_prepare_tx()
413 netdev_err(ena_com_io_sq_to_ena_dev(io_sq)->net_device, in ena_com_prepare_tx()
415 return -EINVAL; in ena_com_prepare_tx()
424 netdev_err(ena_com_io_sq_to_ena_dev(io_sq)->net_device, in ena_com_prepare_tx()
433 netdev_err(ena_com_io_sq_to_ena_dev(io_sq)->net_device, in ena_com_prepare_tx()
435 *nb_hw_desc = io_sq->tail - start_tail; in ena_com_prepare_tx()
441 return -EFAULT; in ena_com_prepare_tx()
446 desc->len_ctrl |= ENA_ETH_IO_TX_DESC_FIRST_MASK; in ena_com_prepare_tx()
448 desc->buff_addr_hi_hdr_sz |= ((u32)header_len << in ena_com_prepare_tx()
451 desc->len_ctrl |= ((u32)io_sq->phase << ENA_ETH_IO_TX_DESC_PHASE_SHIFT) & in ena_com_prepare_tx()
454 desc->len_ctrl |= ENA_ETH_IO_TX_DESC_COMP_REQ_MASK; in ena_com_prepare_tx()
456 /* Bits 0-9 */ in ena_com_prepare_tx()
457 desc->meta_ctrl |= ((u32)ena_tx_ctx->req_id << in ena_com_prepare_tx()
461 desc->meta_ctrl |= (ena_tx_ctx->df << in ena_com_prepare_tx()
465 /* Bits 10-15 */ in ena_com_prepare_tx()
466 desc->len_ctrl |= ((ena_tx_ctx->req_id >> 10) << in ena_com_prepare_tx()
470 if (ena_tx_ctx->meta_valid) { in ena_com_prepare_tx()
471 desc->meta_ctrl |= (ena_tx_ctx->tso_enable << in ena_com_prepare_tx()
474 desc->meta_ctrl |= ena_tx_ctx->l3_proto & in ena_com_prepare_tx()
476 desc->meta_ctrl |= (ena_tx_ctx->l4_proto << in ena_com_prepare_tx()
479 desc->meta_ctrl |= (ena_tx_ctx->l3_csum_enable << in ena_com_prepare_tx()
482 desc->meta_ctrl |= (ena_tx_ctx->l4_csum_enable << in ena_com_prepare_tx()
485 desc->meta_ctrl |= (ena_tx_ctx->l4_csum_partial << in ena_com_prepare_tx()
495 netdev_err(ena_com_io_sq_to_ena_dev(io_sq)->net_device, in ena_com_prepare_tx()
502 return -EFAULT; in ena_com_prepare_tx()
506 desc->len_ctrl |= ((u32)io_sq->phase << in ena_com_prepare_tx()
511 desc->len_ctrl |= ena_bufs->len & in ena_com_prepare_tx()
514 addr_hi = ((ena_bufs->paddr & in ena_com_prepare_tx()
515 GENMASK_ULL(io_sq->dma_addr_bits - 1, 32)) >> 32); in ena_com_prepare_tx()
517 desc->buff_addr_lo = (u32)ena_bufs->paddr; in ena_com_prepare_tx()
518 desc->buff_addr_hi_hdr_sz |= addr_hi & in ena_com_prepare_tx()
524 desc->len_ctrl |= ENA_ETH_IO_TX_DESC_LAST_MASK; in ena_com_prepare_tx()
528 netdev_err(ena_com_io_sq_to_ena_dev(io_sq)->net_device, in ena_com_prepare_tx()
535 *nb_hw_desc = io_sq->tail - start_tail; in ena_com_prepare_tx()
543 struct ena_com_rx_buf_info *ena_buf = &ena_rx_ctx->ena_bufs[0]; in ena_com_rx_pkt()
545 u16 q_depth = io_cq->q_depth; in ena_com_rx_pkt()
550 WARN(io_cq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX, "wrong Q type"); in ena_com_rx_pkt()
554 ena_rx_ctx->descs = nb_hw_desc; in ena_com_rx_pkt()
558 netdev_dbg(ena_com_io_cq_to_ena_dev(io_cq)->net_device, in ena_com_rx_pkt()
559 "Fetch rx packet: queue %d completed desc: %d\n", io_cq->qid, in ena_com_rx_pkt()
562 if (unlikely(nb_hw_desc > ena_rx_ctx->max_bufs)) { in ena_com_rx_pkt()
563 netdev_err(ena_com_io_cq_to_ena_dev(io_cq)->net_device, in ena_com_rx_pkt()
565 ena_rx_ctx->max_bufs); in ena_com_rx_pkt()
566 return -ENOSPC; in ena_com_rx_pkt()
570 ena_rx_ctx->pkt_offset = cdesc->offset; in ena_com_rx_pkt()
573 ena_buf[i].len = cdesc->length; in ena_com_rx_pkt()
574 ena_buf[i].req_id = cdesc->req_id; in ena_com_rx_pkt()
576 return -EIO; in ena_com_rx_pkt()
586 io_sq->next_to_comp += nb_hw_desc; in ena_com_rx_pkt()
588 netdev_dbg(ena_com_io_cq_to_ena_dev(io_cq)->net_device, in ena_com_rx_pkt()
590 io_sq->qid, io_sq->next_to_comp); in ena_com_rx_pkt()
595 ena_rx_ctx->descs = nb_hw_desc; in ena_com_rx_pkt()
606 WARN(io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX, "wrong Q type"); in ena_com_add_single_rx_desc()
609 return -ENOSPC; in ena_com_add_single_rx_desc()
613 return -EFAULT; in ena_com_add_single_rx_desc()
617 desc->length = ena_buf->len; in ena_com_add_single_rx_desc()
619 desc->ctrl = ENA_ETH_IO_RX_DESC_FIRST_MASK | in ena_com_add_single_rx_desc()
622 (io_sq->phase & ENA_ETH_IO_RX_DESC_PHASE_MASK); in ena_com_add_single_rx_desc()
624 desc->req_id = req_id; in ena_com_add_single_rx_desc()
626 netdev_dbg(ena_com_io_sq_to_ena_dev(io_sq)->net_device, in ena_com_add_single_rx_desc()
628 __func__, io_sq->qid, req_id); in ena_com_add_single_rx_desc()
630 desc->buff_addr_lo = (u32)ena_buf->paddr; in ena_com_add_single_rx_desc()
631 desc->buff_addr_hi = in ena_com_add_single_rx_desc()
632 ((ena_buf->paddr & GENMASK_ULL(io_sq->dma_addr_bits - 1, 32)) >> 32); in ena_com_add_single_rx_desc()