amazon/ena/ena_admin_defs.h

1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
3  * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
26 	/* Additional status is provided in ACQ entry extended_status */
59 	/* descriptors and headers are in device memory (a.k.a Low Latency
79 	/* completion queue entry for each sq descriptor */
81 	/* completion queue entry upon request in sq descriptor */
119 	 * 1 : ctrl_data - control buffer address valid
120 	 * 2 : ctrl_data_indirect - control buffer address
142 	 * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx
177 	/* indicates to the driver which AQ entry has been consumed by the
193 	 * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx
199 	/* 3:0 : placement_policy - Describing where the SQ
201 	 *    0x1 - descriptors and headers are in OS memory,
202 	 *    0x3 - descriptors and headers in device memory
203 	 *    (a.k.a Low Latency Queue)
204 	 * 6:4 : completion_policy - Describing what policy
205 	 *    to use for generation completion entry (cqe) in
206 	 *    the CQ associated with this SQ: 0x0 - cqe for each
207 	 *    sq descriptor, 0x1 - cqe upon request in sq
208 	 *    descriptor, 0x2 - current queue head pointer is
210 	 *    0x3 - current queue head pointer is updated in OS
216 	/* 0 : is_physically_contiguous - Described if the
232 	 * used for Low Latency queues. Has to be page aligned.
262 	/* low latency queue ring base address as an offset to PCIe MMIO
267 	/* low latency queue headers' memory as an offset to PCIe MMIO
287 	 * 5 : interrupt_mode_enabled - if set, cq operates
288 	 *    in interrupt mode, otherwise - polling
293 	/* 4:0 : cq_entry_size_words - size of CQ entry in
294 	 *    32-bit words, valid values: 4, 8.
339  * buffer pointed by AQ entry
435 	/* 1:0 : select - 0x1 - current value; 0x3 - default
485 	/* header in a separate ring, implies 16B descriptor list entry */
503 /* packet descriptor list entry always starts with one or more descriptors,
505  * beginning of the subsequent entry. Stride refers to how the rest of the
557 	/* if inline header is specified - this is the size of descriptor list
558 	 * entry. If header in a separate ring is specified - this is the size
559 	 * of header ring entry. bitfield of enum ena_admin_llq_ring_entry_size.
560 	 * specify the entry sizes the device supports
564 	/* the entry size the driver selected to use. */
567 	/* valid only if inline header is specified. First entry associated with
570 	 * descriptors precedding the header in the first entry. The field is
590 	/* accelerated low latency queues requirement. driver needs to
683 	 * 1 : duplex - Full Duplex
699 	 * 1 : TX_L4_ipv4_csum_part - The checksum field
702 	 * 3 : TX_L4_ipv6_csum_part - The checksum field
712 	 * 0 : RX_L3_csum_ipv4 - IPv4 checksum
713 	 * 1 : RX_L4_ipv4_csum - TCP/UDP/IPv4 checksum
714 	 * 2 : RX_L4_ipv6_csum - TCP/UDP/IPv6 checksum
715 	 * 3 : RX_hash - Hash calculation
736 	/* 7:0 : funcs - bitmask of ena_admin_hash_functions */
739 	/* 7:0 : selected_func - bitmask of
800 	 * 1 : L3_sort - support swap L3 addresses if DA is
802 	 * 2 : L4_sort - support swap L4 ports if DP smaller
808 	 * 1 : enable_L3_sort - enable swap L3 addresses if
810 	 * 2 : enable_L4_sort - enable swap L4 ports if DP
897 	/* index of the inline entry. 0xFFFFFFFF means invalid */
900 	/* used for updating single entry, ignored when setting the entire
1033 	 * 7:1 : reserved - MBZ