Lines Matching +full:port +full:- +full:mapping +full:- +full:mode
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Marvell 88E6xxx Switch Port Registers support
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
16 /* Offset 0x00: Port Status Register */
150 /* Offset 0x04: Port Control Register */
185 /* Offset 0x05: Port Control 1 */
193 /* Offset 0x06: Port Based VLAN Map */
197 /* Offset 0x07: Default Port VLAN ID & Priority */
201 /* Offset 0x08: Port Control 2 Register */
230 /* Offset 0x0B: Port Association Vector */
238 /* Offset 0x0C: Port ATU Control */
272 /* Offset 0x0F: Port Special Ether Type */
279 /* Offset 0x10: Extended Port Control Command */
285 /* Offset 0x11: Extended Port Control Data */
297 /* Offset 0x18: IEEE Priority Mapping Table */
311 /* Offset 0x18: Port IEEE Priority Remapping Registers (0-3) */
314 /* Offset 0x19: Port IEEE Priority Remapping Registers (4-7) */
329 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
331 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
333 int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg,
336 int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port,
338 int mv88e6320_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
339 phy_interface_t mode);
340 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
341 phy_interface_t mode);
342 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
343 phy_interface_t mode);
345 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link);
347 int mv88e6xxx_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup);
348 int mv88e6185_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup);
350 int mv88e6185_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
352 int mv88e6250_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
354 int mv88e6341_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
356 int mv88e6352_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
358 int mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
360 int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
362 int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
366 int port);
368 int port);
370 int port);
372 int port);
374 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state);
376 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map);
378 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid);
379 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid);
381 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid);
382 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid);
384 int mv88e6xxx_port_set_lock(struct mv88e6xxx_chip *chip, int port,
387 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
388 u16 mode);
389 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port);
390 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port);
391 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
392 enum mv88e6xxx_egress_mode mode);
393 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
394 enum mv88e6xxx_frame_mode mode);
395 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
396 enum mv88e6xxx_frame_mode mode);
398 int port, bool unicast);
400 int port, bool multicast);
401 int mv88e6352_port_set_ucast_flood(struct mv88e6xxx_chip *chip, int port,
403 int mv88e6352_port_set_mcast_flood(struct mv88e6xxx_chip *chip, int port,
405 int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port,
406 enum mv88e6xxx_policy_mapping mapping,
408 int mv88e6393x_port_set_policy(struct mv88e6xxx_chip *chip, int port,
409 enum mv88e6xxx_policy_mapping mapping,
411 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
415 int port);
416 int mv88e6393x_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
419 int mv88e6393x_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
421 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
423 int mv88e6xxx_port_set_trunk(struct mv88e6xxx_chip *chip, int port,
425 int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
427 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port);
428 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port);
429 int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port,
431 int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
433 int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
435 int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
436 phy_interface_t mode);
437 int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
438 phy_interface_t mode);
439 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
440 phy_interface_t mode);
441 int mv88e6393x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
442 phy_interface_t mode);
443 int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
444 int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
445 int mv88e6xxx_port_drop_untagged(struct mv88e6xxx_chip *chip, int port,
447 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port, bool map);
448 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
450 int mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip *chip, int port,
454 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port);
455 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port);
458 int port, int reg, u16 val);
460 int mv88e6xxx_port_hidden_read(struct mv88e6xxx_chip *chip, int block, int port,