1 // SPDX-License-Identifier: GPL-2.0-or-later
7  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
18 	int addr = chip->info->global1_addr;  in mv88e6xxx_g1_read()
25 	int addr = chip->info->global1_addr;  in mv88e6xxx_g1_write()
33 	return mv88e6xxx_wait_bit(chip, chip->info->global1_addr, reg,  in mv88e6xxx_g1_wait_bit()
40 	return mv88e6xxx_wait_mask(chip, chip->info->global1_addr, reg,  in mv88e6xxx_g1_wait_mask()
113 	 * the PPU, including re-doing PHY detection and initialization  in mv88e6185_g1_reset()
218 /* Offset 0x10: IP-PRI Mapping Register 0
219  * Offset 0x11: IP-PRI Mapping Register 1
220  * Offset 0x12: IP-PRI Mapping Register 2
221  * Offset 0x13: IP-PRI Mapping Register 3
222  * Offset 0x14: IP-PRI Mapping Register 4
223  * Offset 0x15: IP-PRI Mapping Register 5
224  * Offset 0x16: IP-PRI Mapping Register 6
225  * Offset 0x17: IP-PRI Mapping Register 7
268 /* Offset 0x18: IEEE-PRI Register */
287 				 int port)  in mv88e6095_g1_set_egress_port()  argument
299 		reg |= port <<  in mv88e6095_g1_set_egress_port()
304 		reg |= port <<  in mv88e6095_g1_set_egress_port()
308 		return -EINVAL;  in mv88e6095_g1_set_egress_port()
318 int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)  in mv88e6095_g1_set_cpu_port()  argument
328 	reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK);  in mv88e6095_g1_set_cpu_port()
345 				 int port)  in mv88e6390_g1_set_egress_port()  argument
357 		return -EINVAL;  in mv88e6390_g1_set_egress_port()
360 	return mv88e6390_g1_monitor_write(chip, ptr, port);  in mv88e6390_g1_set_egress_port()
363 int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)  in mv88e6390_g1_set_cpu_port()  argument
370 	port |= MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI;  in mv88e6390_g1_set_cpu_port()
372 	return mv88e6390_g1_monitor_write(chip, ptr, port);  in mv88e6390_g1_set_cpu_port()
375 int mv88e6390_g1_set_ptp_cpu_port(struct mv88e6xxx_chip *chip, int port)  in mv88e6390_g1_set_ptp_cpu_port()  argument
382 	port |= MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI;  in mv88e6390_g1_set_ptp_cpu_port()
384 	return mv88e6390_g1_monitor_write(chip, ptr, port);  in mv88e6390_g1_set_ptp_cpu_port()
392 	/* 01:80:c2:00:00:00-01:80:c2:00:00:07 are Management */  in mv88e6390_g1_mgmt_rsvd2cpu()
398 	/* 01:80:c2:00:00:08-01:80:c2:00:00:0f are Management */  in mv88e6390_g1_mgmt_rsvd2cpu()
404 	/* 01:80:c2:00:00:20-01:80:c2:00:00:27 are Management */  in mv88e6390_g1_mgmt_rsvd2cpu()
410 	/* 01:80:c2:00:00:28-01:80:c2:00:00:2f are Management */  in mv88e6390_g1_mgmt_rsvd2cpu()
437 int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port)  in mv88e6185_g1_set_cascade_port()  argument
441 	return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask));  in mv88e6185_g1_set_cascade_port()
500 int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)  in mv88e6xxx_g1_stats_snapshot()  argument
504 	/* Snapshot the hardware statistics counters for this port. */  in mv88e6xxx_g1_stats_snapshot()
508 				 MV88E6XXX_G1_STATS_OP_HIST_RX | port);  in mv88e6xxx_g1_stats_snapshot()
516 int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)  in mv88e6320_g1_stats_snapshot()  argument
518 	port = (port + 1) << 5;  in mv88e6320_g1_stats_snapshot()
520 	return mv88e6xxx_g1_stats_snapshot(chip, port);  in mv88e6320_g1_stats_snapshot()
523 int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)  in mv88e6390_g1_stats_snapshot()  argument
527 	port = (port + 1) << 5;  in mv88e6390_g1_stats_snapshot()
529 	/* Snapshot the hardware statistics counters for this port. */  in mv88e6390_g1_stats_snapshot()
532 				 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | port);  in mv88e6390_g1_stats_snapshot()
580 	/* Keep the histogram mode bits */  in mv88e6xxx_g1_stats_clear()