Lines Matching +full:chip +full:- +full:to +full:- +full:chip
1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
13 #include "chip.h"
16 int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) in mv88e6xxx_g1_read() argument
18 int addr = chip->info->global1_addr; in mv88e6xxx_g1_read()
20 return mv88e6xxx_read(chip, addr, reg, val); in mv88e6xxx_g1_read()
23 int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val) in mv88e6xxx_g1_write() argument
25 int addr = chip->info->global1_addr; in mv88e6xxx_g1_write()
27 return mv88e6xxx_write(chip, addr, reg, val); in mv88e6xxx_g1_write()
30 int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int in mv88e6xxx_g1_wait_bit() argument
33 return mv88e6xxx_wait_bit(chip, chip->info->global1_addr, reg, in mv88e6xxx_g1_wait_bit()
37 int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg, in mv88e6xxx_g1_wait_mask() argument
40 return mv88e6xxx_wait_mask(chip, chip->info->global1_addr, reg, in mv88e6xxx_g1_wait_mask()
46 static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip) in mv88e6185_g1_wait_ppu_disabled() argument
48 return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS, in mv88e6185_g1_wait_ppu_disabled()
53 static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) in mv88e6185_g1_wait_ppu_polling() argument
55 return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS, in mv88e6185_g1_wait_ppu_polling()
60 static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) in mv88e6352_g1_wait_ppu_polling() argument
64 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1); in mv88e6352_g1_wait_ppu_polling()
67 static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip) in mv88e6xxx_g1_wait_init_ready() argument
71 /* Wait up to 1 second for the switch to be ready. The InitReady bit 11 in mv88e6xxx_g1_wait_init_ready()
72 * is set to a one when all units inside the device (ATU, VTU, etc.) in mv88e6xxx_g1_wait_init_ready()
73 * have finished their initialization and are ready to accept frames. in mv88e6xxx_g1_wait_init_ready()
75 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1); in mv88e6xxx_g1_wait_init_ready()
82 int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) in mv88e6xxx_g1_set_switch_mac() argument
88 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg); in mv88e6xxx_g1_set_switch_mac()
93 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg); in mv88e6xxx_g1_set_switch_mac()
98 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg); in mv88e6xxx_g1_set_switch_mac()
107 int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip) in mv88e6185_g1_reset() argument
112 /* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart in mv88e6185_g1_reset()
113 * the PPU, including re-doing PHY detection and initialization in mv88e6185_g1_reset()
115 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); in mv88e6185_g1_reset()
122 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); in mv88e6185_g1_reset()
126 err = mv88e6xxx_g1_wait_init_ready(chip); in mv88e6185_g1_reset()
130 return mv88e6185_g1_wait_ppu_polling(chip); in mv88e6185_g1_reset()
133 int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip) in mv88e6250_g1_reset() argument
139 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); in mv88e6250_g1_reset()
145 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); in mv88e6250_g1_reset()
149 return mv88e6xxx_g1_wait_init_ready(chip); in mv88e6250_g1_reset()
152 int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip) in mv88e6352_g1_reset() argument
156 err = mv88e6250_g1_reset(chip); in mv88e6352_g1_reset()
160 return mv88e6352_g1_wait_ppu_polling(chip); in mv88e6352_g1_reset()
163 int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip) in mv88e6185_g1_ppu_enable() argument
168 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); in mv88e6185_g1_ppu_enable()
174 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); in mv88e6185_g1_ppu_enable()
178 return mv88e6185_g1_wait_ppu_polling(chip); in mv88e6185_g1_ppu_enable()
181 int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip) in mv88e6185_g1_ppu_disable() argument
186 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); in mv88e6185_g1_ppu_disable()
192 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); in mv88e6185_g1_ppu_disable()
196 return mv88e6185_g1_wait_ppu_disabled(chip); in mv88e6185_g1_ppu_disable()
199 int mv88e6185_g1_set_max_frame_size(struct mv88e6xxx_chip *chip, int mtu) in mv88e6185_g1_set_max_frame_size() argument
206 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); in mv88e6185_g1_set_max_frame_size()
215 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); in mv88e6185_g1_set_max_frame_size()
218 /* Offset 0x10: IP-PRI Mapping Register 0
219 * Offset 0x11: IP-PRI Mapping Register 1
220 * Offset 0x12: IP-PRI Mapping Register 2
221 * Offset 0x13: IP-PRI Mapping Register 3
222 * Offset 0x14: IP-PRI Mapping Register 4
223 * Offset 0x15: IP-PRI Mapping Register 5
224 * Offset 0x16: IP-PRI Mapping Register 6
225 * Offset 0x17: IP-PRI Mapping Register 7
228 int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip) in mv88e6085_g1_ip_pri_map() argument
232 /* Reset the IP TOS/DiffServ/Traffic priorities to defaults */ in mv88e6085_g1_ip_pri_map()
233 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000); in mv88e6085_g1_ip_pri_map()
237 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000); in mv88e6085_g1_ip_pri_map()
241 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555); in mv88e6085_g1_ip_pri_map()
245 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555); in mv88e6085_g1_ip_pri_map()
249 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa); in mv88e6085_g1_ip_pri_map()
253 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa); in mv88e6085_g1_ip_pri_map()
257 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff); in mv88e6085_g1_ip_pri_map()
261 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff); in mv88e6085_g1_ip_pri_map()
268 /* Offset 0x18: IEEE-PRI Register */
270 int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) in mv88e6085_g1_ieee_pri_map() argument
272 /* Reset the IEEE Tag priorities to defaults */ in mv88e6085_g1_ieee_pri_map()
273 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41); in mv88e6085_g1_ieee_pri_map()
276 int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) in mv88e6250_g1_ieee_pri_map() argument
278 /* Reset the IEEE Tag priorities to defaults */ in mv88e6250_g1_ieee_pri_map()
279 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa50); in mv88e6250_g1_ieee_pri_map()
285 int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, in mv88e6095_g1_set_egress_port() argument
292 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); in mv88e6095_g1_set_egress_port()
308 return -EINVAL; in mv88e6095_g1_set_egress_port()
311 return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); in mv88e6095_g1_set_egress_port()
318 int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) in mv88e6095_g1_set_cpu_port() argument
323 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); in mv88e6095_g1_set_cpu_port()
330 return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); in mv88e6095_g1_set_cpu_port()
333 static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip, in mv88e6390_g1_monitor_write() argument
340 return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg); in mv88e6390_g1_monitor_write()
343 int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, in mv88e6390_g1_set_egress_port() argument
357 return -EINVAL; in mv88e6390_g1_set_egress_port()
360 return mv88e6390_g1_monitor_write(chip, ptr, port); in mv88e6390_g1_set_egress_port()
363 int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) in mv88e6390_g1_set_cpu_port() argument
367 /* Use the default high priority for management frames sent to in mv88e6390_g1_set_cpu_port()
372 return mv88e6390_g1_monitor_write(chip, ptr, port); in mv88e6390_g1_set_cpu_port()
375 int mv88e6390_g1_set_ptp_cpu_port(struct mv88e6xxx_chip *chip, int port) in mv88e6390_g1_set_ptp_cpu_port() argument
379 /* Use the default high priority for PTP frames sent to in mv88e6390_g1_set_ptp_cpu_port()
384 return mv88e6390_g1_monitor_write(chip, ptr, port); in mv88e6390_g1_set_ptp_cpu_port()
387 int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) in mv88e6390_g1_mgmt_rsvd2cpu() argument
392 /* 01:80:c2:00:00:00-01:80:c2:00:00:07 are Management */ in mv88e6390_g1_mgmt_rsvd2cpu()
394 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); in mv88e6390_g1_mgmt_rsvd2cpu()
398 /* 01:80:c2:00:00:08-01:80:c2:00:00:0f are Management */ in mv88e6390_g1_mgmt_rsvd2cpu()
400 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); in mv88e6390_g1_mgmt_rsvd2cpu()
404 /* 01:80:c2:00:00:20-01:80:c2:00:00:27 are Management */ in mv88e6390_g1_mgmt_rsvd2cpu()
406 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); in mv88e6390_g1_mgmt_rsvd2cpu()
410 /* 01:80:c2:00:00:28-01:80:c2:00:00:2f are Management */ in mv88e6390_g1_mgmt_rsvd2cpu()
412 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); in mv88e6390_g1_mgmt_rsvd2cpu()
421 static int mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip *chip, u16 mask, in mv88e6xxx_g1_ctl2_mask() argument
427 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, ®); in mv88e6xxx_g1_ctl2_mask()
434 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, reg); in mv88e6xxx_g1_ctl2_mask()
437 int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port) in mv88e6185_g1_set_cascade_port() argument
441 return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask)); in mv88e6185_g1_set_cascade_port()
444 int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip) in mv88e6085_g1_rmu_disable() argument
446 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM | in mv88e6085_g1_rmu_disable()
450 int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip) in mv88e6352_g1_rmu_disable() argument
452 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK, in mv88e6352_g1_rmu_disable()
456 int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip) in mv88e6390_g1_rmu_disable() argument
458 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK, in mv88e6390_g1_rmu_disable()
462 int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) in mv88e6390_g1_stats_set_histogram() argument
464 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_HIST_MODE_MASK, in mv88e6390_g1_stats_set_histogram()
468 int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index) in mv88e6xxx_g1_set_device_number() argument
470 return mv88e6xxx_g1_ctl2_mask(chip, in mv88e6xxx_g1_set_device_number()
477 static int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip) in mv88e6xxx_g1_stats_wait() argument
481 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STATS_OP, bit, 0); in mv88e6xxx_g1_stats_wait()
484 int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) in mv88e6095_g1_stats_set_histogram() argument
489 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); in mv88e6095_g1_stats_set_histogram()
495 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); in mv88e6095_g1_stats_set_histogram()
500 int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) in mv88e6xxx_g1_stats_snapshot() argument
505 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, in mv88e6xxx_g1_stats_snapshot()
512 /* Wait for the snapshotting to complete. */ in mv88e6xxx_g1_stats_snapshot()
513 return mv88e6xxx_g1_stats_wait(chip); in mv88e6xxx_g1_stats_snapshot()
516 int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) in mv88e6320_g1_stats_snapshot() argument
520 return mv88e6xxx_g1_stats_snapshot(chip, port); in mv88e6320_g1_stats_snapshot()
523 int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) in mv88e6390_g1_stats_snapshot() argument
530 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, in mv88e6390_g1_stats_snapshot()
536 /* Wait for the snapshotting to complete. */ in mv88e6390_g1_stats_snapshot()
537 return mv88e6xxx_g1_stats_wait(chip); in mv88e6390_g1_stats_snapshot()
540 void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val) in mv88e6xxx_g1_stats_read() argument
548 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, in mv88e6xxx_g1_stats_read()
554 err = mv88e6xxx_g1_stats_wait(chip); in mv88e6xxx_g1_stats_read()
558 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, ®); in mv88e6xxx_g1_stats_read()
564 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, ®); in mv88e6xxx_g1_stats_read()
571 int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip) in mv88e6xxx_g1_stats_clear() argument
576 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); in mv88e6xxx_g1_stats_clear()
584 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); in mv88e6xxx_g1_stats_clear()
588 /* Wait for the flush to complete. */ in mv88e6xxx_g1_stats_clear()
589 return mv88e6xxx_g1_stats_wait(chip); in mv88e6xxx_g1_stats_clear()