Lines Matching +full:sgmii +full:- +full:enable +full:- +full:pll
1 // SPDX-License-Identifier: GPL-2.0-only
85 struct mii_bus *bus = priv->bus; in core_read_mmd_indirect()
89 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); in core_read_mmd_indirect()
94 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); in core_read_mmd_indirect()
99 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); in core_read_mmd_indirect()
104 value = bus->read(bus, 0, MII_MMD_DATA); in core_read_mmd_indirect()
108 dev_err(&bus->dev, "failed to read mmd register\n"); in core_read_mmd_indirect()
117 struct mii_bus *bus = priv->bus; in core_write_mmd_indirect()
121 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); in core_write_mmd_indirect()
126 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); in core_write_mmd_indirect()
131 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); in core_write_mmd_indirect()
136 ret = bus->write(bus, 0, MII_MMD_DATA, data); in core_write_mmd_indirect()
139 dev_err(&bus->dev, in core_write_mmd_indirect()
147 if (priv->bus) in mt7530_mutex_lock()
148 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7530_mutex_lock()
154 if (priv->bus) in mt7530_mutex_unlock()
155 mutex_unlock(&priv->bus->mdio_lock); in mt7530_mutex_unlock()
200 ret = regmap_write(priv->regmap, reg, val); in mt7530_mii_write()
203 dev_err(priv->dev, in mt7530_mii_write()
215 ret = regmap_read(priv->regmap, reg, &val); in mt7530_mii_read()
218 dev_err(priv->dev, in mt7530_mii_read()
239 return mt7530_mii_read(p->priv, p->reg); in _mt7530_unlocked_read()
247 mt7530_mutex_lock(p->priv); in _mt7530_read()
249 val = mt7530_mii_read(p->priv, p->reg); in _mt7530_read()
251 mt7530_mutex_unlock(p->priv); in _mt7530_read()
271 regmap_update_bits(priv->regmap, reg, mask, set); in mt7530_rmw()
303 dev_err(priv->dev, "reset timeout\n"); in mt7530_fdb_cmd()
312 return -EINVAL; in mt7530_fdb_cmd()
330 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", in mt7530_fdb_read()
334 fdb->vid = (reg[1] >> CVID) & CVID_MASK; in mt7530_fdb_read()
335 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; in mt7530_fdb_read()
336 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; in mt7530_fdb_read()
337 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; in mt7530_fdb_read()
338 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; in mt7530_fdb_read()
339 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; in mt7530_fdb_read()
340 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; in mt7530_fdb_read()
341 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; in mt7530_fdb_read()
342 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; in mt7530_fdb_read()
343 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; in mt7530_fdb_read()
382 /* Disable PLL */ in mt7530_pll_setup()
390 /* Enable PLL */ in mt7530_pll_setup()
398 /* Enable core clock */ in mt7530_pll_setup()
420 struct mt7530_priv *priv = ds->priv; in mt7530_pad_clk_setup()
426 dev_err(priv->dev, in mt7530_pad_clk_setup()
429 return -EINVAL; in mt7530_pad_clk_setup()
442 if (priv->id == ID_MT7621) { in mt7530_pad_clk_setup()
443 /* PLL frequency: 125MHz: 1.0GBit */ in mt7530_pad_clk_setup()
448 } else { /* PLL frequency: 250MHz: 2.0Gbit */ in mt7530_pad_clk_setup()
456 dev_err(priv->dev, "xMII interface %d not supported\n", in mt7530_pad_clk_setup()
458 return -EINVAL; in mt7530_pad_clk_setup()
483 /* Enable the MT7530 TRGMII clocks */ in mt7530_pad_clk_setup()
539 /* Step 3: disable PLLGP and enable program PLLGP */ in mt7531_pll_setup()
578 /* Enable 325M clock for SGMII */ in mt7531_pll_setup()
581 /* Enable 250SSC clock for RGMII */ in mt7531_pll_setup()
584 /* Step 6: Enable MT7531 PLL */ in mt7531_pll_setup()
598 struct mt7530_priv *priv = ds->priv; in mt7530_mib_reset()
606 return mdiobus_read_nested(priv->bus, port, regnum); in mt7530_phy_read_c22()
612 return mdiobus_write_nested(priv->bus, port, regnum, val); in mt7530_phy_write_c22()
618 return mdiobus_c45_read_nested(priv->bus, port, devad, regnum); in mt7530_phy_read_c45()
624 return mdiobus_c45_write_nested(priv->bus, port, devad, regnum, val); in mt7530_phy_write_c45()
642 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_read()
653 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_read()
664 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_read()
690 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_write()
701 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_write()
712 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_write()
736 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_read()
748 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_read()
774 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_write()
786 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_write()
799 struct mt7530_priv *priv = bus->priv; in mt753x_phy_read_c22()
801 return priv->info->phy_read_c22(priv, port, regnum); in mt753x_phy_read_c22()
807 struct mt7530_priv *priv = bus->priv; in mt753x_phy_read_c45()
809 return priv->info->phy_read_c45(priv, port, devad, regnum); in mt753x_phy_read_c45()
815 struct mt7530_priv *priv = bus->priv; in mt753x_phy_write_c22()
817 return priv->info->phy_write_c22(priv, port, regnum, val); in mt753x_phy_write_c22()
824 struct mt7530_priv *priv = bus->priv; in mt753x_phy_write_c45()
826 return priv->info->phy_write_c45(priv, port, devad, regnum, val); in mt753x_phy_write_c45()
846 struct mt7530_priv *priv = ds->priv; in mt7530_get_ethtool_stats()
853 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; in mt7530_get_ethtool_stats()
856 if (mib->size == 2) { in mt7530_get_ethtool_stats()
875 struct mt7530_priv *priv = ds->priv; in mt7530_set_ageing_time()
878 unsigned int error = -1; in mt7530_set_ageing_time()
884 return -ERANGE; in mt7530_set_ageing_time()
888 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; in mt7530_set_ageing_time()
891 unsigned int tmp_error = secs - in mt7530_set_ageing_time()
932 struct mt7530_priv *priv = ds->priv; in mt7530_setup_port5()
936 mutex_lock(&priv->reg_mutex); in mt7530_setup_port5()
943 switch (priv->p5_intf_sel) { in mt7530_setup_port5()
945 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ in mt7530_setup_port5()
949 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ in mt7530_setup_port5()
956 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ in mt7530_setup_port5()
963 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", in mt7530_setup_port5()
964 priv->p5_intf_sel); in mt7530_setup_port5()
976 if (!dsa_is_dsa_port(priv->ds, 5) && in mt7530_setup_port5()
992 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", in mt7530_setup_port5()
993 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); in mt7530_setup_port5()
995 priv->p5_interface = interface; in mt7530_setup_port5()
998 mutex_unlock(&priv->reg_mutex); in mt7530_setup_port5()
1020 struct mt7530_priv *priv = ds->priv; in mt753x_cpu_port_enable()
1024 if (priv->info->cpu_port_config) { in mt753x_cpu_port_enable()
1025 ret = priv->info->cpu_port_config(ds, port); in mt753x_cpu_port_enable()
1030 /* Enable Mediatek header mode on the cpu port */ in mt753x_cpu_port_enable()
1034 /* Enable flooding on the CPU port */ in mt753x_cpu_port_enable()
1039 if (priv->id == ID_MT7530 || priv->id == ID_MT7621) in mt753x_cpu_port_enable()
1046 if (priv->id == ID_MT7531 || priv->id == ID_MT7988) in mt753x_cpu_port_enable()
1053 PCR_MATRIX(dsa_user_ports(priv->ds))); in mt753x_cpu_port_enable()
1067 struct mt7530_priv *priv = ds->priv; in mt7530_port_enable()
1069 mutex_lock(&priv->reg_mutex); in mt7530_port_enable()
1076 struct dsa_port *cpu_dp = dp->cpu_dp; in mt7530_port_enable()
1078 priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index)); in mt7530_port_enable()
1080 priv->ports[port].enable = true; in mt7530_port_enable()
1082 priv->ports[port].pm); in mt7530_port_enable()
1085 mutex_unlock(&priv->reg_mutex); in mt7530_port_enable()
1093 struct mt7530_priv *priv = ds->priv; in mt7530_port_disable()
1095 mutex_lock(&priv->reg_mutex); in mt7530_port_disable()
1100 priv->ports[port].enable = false; in mt7530_port_disable()
1105 mutex_unlock(&priv->reg_mutex); in mt7530_port_disable()
1111 struct mt7530_priv *priv = ds->priv; in mt7530_port_change_mtu()
1157 struct mt7530_priv *priv = ds->priv; in mt7530_stp_state_set()
1190 return -EINVAL; in mt7530_port_pre_bridge_flags()
1200 struct mt7530_priv *priv = ds->priv; in mt7530_port_bridge_flags()
1227 struct dsa_port *cpu_dp = dp->cpu_dp; in mt7530_port_bridge_join()
1228 u32 port_bitmap = BIT(cpu_dp->index); in mt7530_port_bridge_join()
1229 struct mt7530_priv *priv = ds->priv; in mt7530_port_bridge_join()
1231 mutex_lock(&priv->reg_mutex); in mt7530_port_bridge_join()
1234 int other_port = other_dp->index; in mt7530_port_bridge_join()
1246 if (priv->ports[other_port].enable) in mt7530_port_bridge_join()
1249 priv->ports[other_port].pm |= PCR_MATRIX(BIT(port)); in mt7530_port_bridge_join()
1255 if (priv->ports[port].enable) in mt7530_port_bridge_join()
1258 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); in mt7530_port_bridge_join()
1264 mutex_unlock(&priv->reg_mutex); in mt7530_port_bridge_join()
1272 struct mt7530_priv *priv = ds->priv; in mt7530_port_set_vlan_unaware()
1276 /* This is called after .port_bridge_leave when leaving a VLAN-aware in mt7530_port_set_vlan_unaware()
1306 struct dsa_port *cpu_dp = dp->cpu_dp; in mt7530_port_set_vlan_unaware()
1308 mt7530_write(priv, MT7530_PCR_P(cpu_dp->index), in mt7530_port_set_vlan_unaware()
1309 PCR_MATRIX(dsa_user_ports(priv->ds))); in mt7530_port_set_vlan_unaware()
1310 mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG in mt7530_port_set_vlan_unaware()
1318 struct mt7530_priv *priv = ds->priv; in mt7530_port_set_vlan_aware()
1327 G0_PORT_VID(priv->ports[port].pvid)); in mt7530_port_set_vlan_aware()
1330 if (!priv->ports[port].pvid) in mt7530_port_set_vlan_aware()
1360 struct dsa_port *cpu_dp = dp->cpu_dp; in mt7530_port_bridge_leave()
1361 struct mt7530_priv *priv = ds->priv; in mt7530_port_bridge_leave()
1363 mutex_lock(&priv->reg_mutex); in mt7530_port_bridge_leave()
1366 int other_port = other_dp->index; in mt7530_port_bridge_leave()
1378 if (priv->ports[other_port].enable) in mt7530_port_bridge_leave()
1381 priv->ports[other_port].pm &= ~PCR_MATRIX(BIT(port)); in mt7530_port_bridge_leave()
1387 if (priv->ports[port].enable) in mt7530_port_bridge_leave()
1389 PCR_MATRIX(BIT(cpu_dp->index))); in mt7530_port_bridge_leave()
1390 priv->ports[port].pm = PCR_MATRIX(BIT(cpu_dp->index)); in mt7530_port_bridge_leave()
1393 * back to the default as is at initial boot which is a VLAN-unaware in mt7530_port_bridge_leave()
1399 mutex_unlock(&priv->reg_mutex); in mt7530_port_bridge_leave()
1407 struct mt7530_priv *priv = ds->priv; in mt7530_port_fdb_add()
1411 mutex_lock(&priv->reg_mutex); in mt7530_port_fdb_add()
1412 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); in mt7530_port_fdb_add()
1414 mutex_unlock(&priv->reg_mutex); in mt7530_port_fdb_add()
1424 struct mt7530_priv *priv = ds->priv; in mt7530_port_fdb_del()
1428 mutex_lock(&priv->reg_mutex); in mt7530_port_fdb_del()
1429 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); in mt7530_port_fdb_del()
1431 mutex_unlock(&priv->reg_mutex); in mt7530_port_fdb_del()
1440 struct mt7530_priv *priv = ds->priv; in mt7530_port_fdb_dump()
1446 mutex_lock(&priv->reg_mutex); in mt7530_port_fdb_dump()
1462 } while (--cnt && in mt7530_port_fdb_dump()
1466 mutex_unlock(&priv->reg_mutex); in mt7530_port_fdb_dump()
1476 struct mt7530_priv *priv = ds->priv; in mt7530_port_mdb_add()
1477 const u8 *addr = mdb->addr; in mt7530_port_mdb_add()
1478 u16 vid = mdb->vid; in mt7530_port_mdb_add()
1482 mutex_lock(&priv->reg_mutex); in mt7530_port_mdb_add()
1490 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); in mt7530_port_mdb_add()
1493 mutex_unlock(&priv->reg_mutex); in mt7530_port_mdb_add()
1503 struct mt7530_priv *priv = ds->priv; in mt7530_port_mdb_del()
1504 const u8 *addr = mdb->addr; in mt7530_port_mdb_del()
1505 u16 vid = mdb->vid; in mt7530_port_mdb_del()
1509 mutex_lock(&priv->reg_mutex); in mt7530_port_mdb_del()
1517 mt7530_fdb_write(priv, vid, port_mask, addr, -1, in mt7530_port_mdb_del()
1521 mutex_unlock(&priv->reg_mutex); in mt7530_port_mdb_del()
1540 dev_err(priv->dev, "poll timeout\n"); in mt7530_vlan_cmd()
1546 dev_err(priv->dev, "read VTCR invalid\n"); in mt7530_vlan_cmd()
1547 return -EINVAL; in mt7530_vlan_cmd()
1558 struct dsa_port *cpu_dp = dp->cpu_dp; in mt7530_port_vlan_filtering()
1561 /* The port is being kept as VLAN-unaware port when bridge is in mt7530_port_vlan_filtering()
1564 * for becoming a VLAN-aware port. in mt7530_port_vlan_filtering()
1567 mt7530_port_set_vlan_aware(ds, cpu_dp->index); in mt7530_port_vlan_filtering()
1579 struct dsa_port *dp = dsa_to_port(priv->ds, entry->port); in mt7530_hw_vlan_add()
1583 new_members = entry->old_members | BIT(entry->port); in mt7530_hw_vlan_add()
1601 else if (entry->untagged) in mt7530_hw_vlan_add()
1606 ETAG_CTRL_P_MASK(entry->port), in mt7530_hw_vlan_add()
1607 ETAG_CTRL_P(entry->port, val)); in mt7530_hw_vlan_add()
1617 new_members = entry->old_members & ~BIT(entry->port); in mt7530_hw_vlan_del()
1621 dev_err(priv->dev, in mt7530_hw_vlan_del()
1648 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; in mt7530_hw_vlan_update()
1677 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; in mt7530_port_vlan_add()
1678 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; in mt7530_port_vlan_add()
1680 struct mt7530_priv *priv = ds->priv; in mt7530_port_vlan_add()
1682 mutex_lock(&priv->reg_mutex); in mt7530_port_vlan_add()
1685 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); in mt7530_port_vlan_add()
1688 priv->ports[port].pvid = vlan->vid; in mt7530_port_vlan_add()
1698 G0_PORT_VID(vlan->vid)); in mt7530_port_vlan_add()
1699 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) { in mt7530_port_vlan_add()
1701 priv->ports[port].pvid = G0_PORT_VID_DEF; in mt7530_port_vlan_add()
1703 /* Only accept tagged frames if the port is VLAN-aware */ in mt7530_port_vlan_add()
1712 mutex_unlock(&priv->reg_mutex); in mt7530_port_vlan_add()
1722 struct mt7530_priv *priv = ds->priv; in mt7530_port_vlan_del()
1724 mutex_lock(&priv->reg_mutex); in mt7530_port_vlan_del()
1727 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, in mt7530_port_vlan_del()
1733 if (priv->ports[port].pvid == vlan->vid) { in mt7530_port_vlan_del()
1734 priv->ports[port].pvid = G0_PORT_VID_DEF; in mt7530_port_vlan_del()
1736 /* Only accept tagged frames if the port is VLAN-aware */ in mt7530_port_vlan_del()
1746 mutex_unlock(&priv->reg_mutex); in mt7530_port_vlan_del()
1767 struct mt7530_priv *priv = ds->priv; in mt753x_port_mirror_add()
1772 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) in mt753x_port_mirror_add()
1773 return -EEXIST; in mt753x_port_mirror_add()
1775 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); in mt753x_port_mirror_add()
1778 monitor_port = mt753x_mirror_port_get(priv->id, val); in mt753x_port_mirror_add()
1779 if (val & MT753X_MIRROR_EN(priv->id) && in mt753x_port_mirror_add()
1780 monitor_port != mirror->to_local_port) in mt753x_port_mirror_add()
1781 return -EEXIST; in mt753x_port_mirror_add()
1783 val |= MT753X_MIRROR_EN(priv->id); in mt753x_port_mirror_add()
1784 val &= ~MT753X_MIRROR_MASK(priv->id); in mt753x_port_mirror_add()
1785 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); in mt753x_port_mirror_add()
1786 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); in mt753x_port_mirror_add()
1791 priv->mirror_rx |= BIT(port); in mt753x_port_mirror_add()
1794 priv->mirror_tx |= BIT(port); in mt753x_port_mirror_add()
1804 struct mt7530_priv *priv = ds->priv; in mt753x_port_mirror_del()
1808 if (mirror->ingress) { in mt753x_port_mirror_del()
1810 priv->mirror_rx &= ~BIT(port); in mt753x_port_mirror_del()
1813 priv->mirror_tx &= ~BIT(port); in mt753x_port_mirror_del()
1817 if (!priv->mirror_rx && !priv->mirror_tx) { in mt753x_port_mirror_del()
1818 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); in mt753x_port_mirror_del()
1819 val &= ~MT753X_MIRROR_EN(priv->id); in mt753x_port_mirror_del()
1820 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); in mt753x_port_mirror_del()
1909 struct device *dev = priv->dev; in mt7530_setup_gpio()
1914 return -ENOMEM; in mt7530_setup_gpio()
1920 gc->label = "mt7530"; in mt7530_setup_gpio()
1921 gc->parent = dev; in mt7530_setup_gpio()
1922 gc->owner = THIS_MODULE; in mt7530_setup_gpio()
1923 gc->get_direction = mt7530_gpio_get_direction; in mt7530_setup_gpio()
1924 gc->direction_input = mt7530_gpio_direction_input; in mt7530_setup_gpio()
1925 gc->direction_output = mt7530_gpio_direction_output; in mt7530_setup_gpio()
1926 gc->get = mt7530_gpio_get; in mt7530_setup_gpio()
1927 gc->set = mt7530_gpio_set; in mt7530_setup_gpio()
1928 gc->base = -1; in mt7530_setup_gpio()
1929 gc->ngpio = 15; in mt7530_setup_gpio()
1930 gc->can_sleep = true; in mt7530_setup_gpio()
1953 irq = irq_find_mapping(priv->irq_domain, p); in mt7530_irq_thread_fn()
1967 priv->irq_enable &= ~BIT(d->hwirq); in mt7530_irq_mask()
1975 priv->irq_enable |= BIT(d->hwirq); in mt7530_irq_unmask()
1991 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); in mt7530_irq_bus_sync_unlock()
2007 irq_set_chip_data(irq, domain->host_data); in mt7530_irq_map()
2025 priv->irq_enable &= ~BIT(d->hwirq); in mt7988_irq_mask()
2026 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); in mt7988_irq_mask()
2034 priv->irq_enable |= BIT(d->hwirq); in mt7988_irq_unmask()
2035 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); in mt7988_irq_unmask()
2048 irq_set_chip_data(irq, domain->host_data); in mt7988_irq_map()
2064 struct dsa_switch *ds = priv->ds; in mt7530_setup_mdio_irq()
2068 if (BIT(p) & ds->phys_mii_mask) { in mt7530_setup_mdio_irq()
2071 irq = irq_create_mapping(priv->irq_domain, p); in mt7530_setup_mdio_irq()
2072 ds->user_mii_bus->irq[p] = irq; in mt7530_setup_mdio_irq()
2080 struct device *dev = priv->dev; in mt7530_setup_irq()
2081 struct device_node *np = dev->of_node; in mt7530_setup_irq()
2084 if (!of_property_read_bool(np, "interrupt-controller")) { in mt7530_setup_irq()
2089 priv->irq = of_irq_get(np, 0); in mt7530_setup_irq()
2090 if (priv->irq <= 0) { in mt7530_setup_irq()
2091 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq); in mt7530_setup_irq()
2092 return priv->irq ? : -EINVAL; in mt7530_setup_irq()
2095 if (priv->id == ID_MT7988) in mt7530_setup_irq()
2096 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, in mt7530_setup_irq()
2100 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, in mt7530_setup_irq()
2104 if (!priv->irq_domain) { in mt7530_setup_irq()
2106 return -ENOMEM; in mt7530_setup_irq()
2110 if (priv->id != ID_MT7531) in mt7530_setup_irq()
2113 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn, in mt7530_setup_irq()
2116 irq_domain_remove(priv->irq_domain); in mt7530_setup_irq()
2130 if (BIT(p) & priv->ds->phys_mii_mask) { in mt7530_free_mdio_irq()
2133 irq = irq_find_mapping(priv->irq_domain, p); in mt7530_free_mdio_irq()
2142 free_irq(priv->irq, priv); in mt7530_free_irq_common()
2143 irq_domain_remove(priv->irq_domain); in mt7530_free_irq_common()
2156 struct dsa_switch *ds = priv->ds; in mt7530_setup_mdio()
2157 struct device *dev = priv->dev; in mt7530_setup_mdio()
2164 return -ENOMEM; in mt7530_setup_mdio()
2166 ds->user_mii_bus = bus; in mt7530_setup_mdio()
2167 bus->priv = priv; in mt7530_setup_mdio()
2168 bus->name = KBUILD_MODNAME "-mii"; in mt7530_setup_mdio()
2169 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); in mt7530_setup_mdio()
2170 bus->read = mt753x_phy_read_c22; in mt7530_setup_mdio()
2171 bus->write = mt753x_phy_write_c22; in mt7530_setup_mdio()
2172 bus->read_c45 = mt753x_phy_read_c45; in mt7530_setup_mdio()
2173 bus->write_c45 = mt753x_phy_write_c45; in mt7530_setup_mdio()
2174 bus->parent = dev; in mt7530_setup_mdio()
2175 bus->phy_mask = ~ds->phys_mii_mask; in mt7530_setup_mdio()
2177 if (priv->irq) in mt7530_setup_mdio()
2183 if (priv->irq) in mt7530_setup_mdio()
2193 struct mt7530_priv *priv = ds->priv; in mt7530_setup()
2208 dn = cpu_dp->conduit->dev.of_node->parent; in mt7530_setup()
2216 dev_err(ds->dev, "parent OF node of DSA conduit not found"); in mt7530_setup()
2217 return -EINVAL; in mt7530_setup()
2220 ds->assisted_learning_on_cpu_port = true; in mt7530_setup()
2221 ds->mtu_enforcement_ingress = true; in mt7530_setup()
2223 if (priv->id == ID_MT7530) { in mt7530_setup()
2224 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); in mt7530_setup()
2225 ret = regulator_enable(priv->core_pwr); in mt7530_setup()
2227 dev_err(priv->dev, in mt7530_setup()
2228 "Failed to enable core power: %d\n", ret); in mt7530_setup()
2232 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); in mt7530_setup()
2233 ret = regulator_enable(priv->io_pwr); in mt7530_setup()
2235 dev_err(priv->dev, "Failed to enable io pwr: %d\n", in mt7530_setup()
2241 /* Reset whole chip through gpio pin or memory-mapped registers for in mt7530_setup()
2244 if (priv->mcm) { in mt7530_setup()
2245 reset_control_assert(priv->rstc); in mt7530_setup()
2247 reset_control_deassert(priv->rstc); in mt7530_setup()
2249 gpiod_set_value_cansleep(priv->reset, 0); in mt7530_setup()
2251 gpiod_set_value_cansleep(priv->reset, 1); in mt7530_setup()
2259 dev_err(priv->dev, "reset timeout\n"); in mt7530_setup()
2266 dev_err(priv->dev, "chip %x can't be supported\n", id); in mt7530_setup()
2267 return -ENODEV; in mt7530_setup()
2286 /* Enable port 6 */ in mt7530_setup()
2292 priv->p6_interface = PHY_INTERFACE_MODE_NA; in mt7530_setup()
2296 /* Enable and reset MIB counters */ in mt7530_setup()
2318 /* Enable consistent egress tag */ in mt7530_setup()
2323 /* Setup VLAN ID 0 for VLAN-unaware bridges */ in mt7530_setup()
2329 priv->p5_intf_sel = P5_DISABLED; in mt7530_setup()
2333 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; in mt7530_setup()
2334 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); in mt7530_setup()
2335 if (ret && ret != -ENODEV) in mt7530_setup()
2341 "mediatek,eth-mac")) in mt7530_setup()
2348 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); in mt7530_setup()
2352 if (phy_node->parent == priv->dev->of_node->parent) { in mt7530_setup()
2354 if (ret && ret != -ENODEV) { in mt7530_setup()
2359 id = of_mdio_parse_addr(ds->dev, phy_node); in mt7530_setup()
2361 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; in mt7530_setup()
2363 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; in mt7530_setup()
2372 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { in mt7530_setup()
2392 struct mt7530_priv *priv = ds->priv; in mt7531_setup_common()
2397 /* Enable and reset MIB counters */ in mt7531_setup_common()
2426 /* Enable consistent egress tag */ in mt7531_setup_common()
2442 struct mt7530_priv *priv = ds->priv; in mt7531_setup()
2447 /* Reset whole chip through gpio pin or memory-mapped registers for in mt7531_setup()
2450 if (priv->mcm) { in mt7531_setup()
2451 reset_control_assert(priv->rstc); in mt7531_setup()
2453 reset_control_deassert(priv->rstc); in mt7531_setup()
2455 gpiod_set_value_cansleep(priv->reset, 0); in mt7531_setup()
2457 gpiod_set_value_cansleep(priv->reset, 1); in mt7531_setup()
2465 dev_err(priv->dev, "reset timeout\n"); in mt7531_setup()
2473 dev_err(priv->dev, "chip %x can't be supported\n", id); in mt7531_setup()
2474 return -ENODEV; in mt7531_setup()
2477 /* all MACs must be forced link-down before sw reset */ in mt7531_setup()
2489 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII; in mt7531_setup()
2491 /* Let ds->user_mii_bus be able to access external phy. */ in mt7531_setup()
2497 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; in mt7531_setup()
2499 dev_dbg(ds->dev, "P5 support %s interface\n", in mt7531_setup()
2500 p5_intf_modes(priv->p5_intf_sel)); in mt7531_setup()
2506 priv->p5_interface = PHY_INTERFACE_MODE_NA; in mt7531_setup()
2507 priv->p6_interface = PHY_INTERFACE_MODE_NA; in mt7531_setup()
2509 /* Enable PHY core PLL, since phy_device has not yet been created in mt7531_setup()
2523 /* Setup VLAN ID 0 for VLAN-unaware bridges */ in mt7531_setup()
2528 ds->assisted_learning_on_cpu_port = true; in mt7531_setup()
2529 ds->mtu_enforcement_ingress = true; in mt7531_setup()
2540 config->supported_interfaces); in mt7530_mac_port_get_caps()
2544 phy_interface_set_rgmii(config->supported_interfaces); in mt7530_mac_port_get_caps()
2546 config->supported_interfaces); in mt7530_mac_port_get_caps()
2548 config->supported_interfaces); in mt7530_mac_port_get_caps()
2553 config->supported_interfaces); in mt7530_mac_port_get_caps()
2555 config->supported_interfaces); in mt7530_mac_port_get_caps()
2562 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); in mt7531_is_rgmii_port()
2568 struct mt7530_priv *priv = ds->priv; in mt7531_mac_port_get_caps()
2573 config->supported_interfaces); in mt7531_mac_port_get_caps()
2576 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ in mt7531_mac_port_get_caps()
2578 phy_interface_set_rgmii(config->supported_interfaces); in mt7531_mac_port_get_caps()
2583 case 6: /* 1st cpu port supports sgmii/8023z only */ in mt7531_mac_port_get_caps()
2585 config->supported_interfaces); in mt7531_mac_port_get_caps()
2587 config->supported_interfaces); in mt7531_mac_port_get_caps()
2589 config->supported_interfaces); in mt7531_mac_port_get_caps()
2591 config->mac_capabilities |= MAC_2500FD; in mt7531_mac_port_get_caps()
2599 phy_interface_zero(config->supported_interfaces); in mt7988_mac_port_get_caps()
2604 config->supported_interfaces); in mt7988_mac_port_get_caps()
2609 config->supported_interfaces); in mt7988_mac_port_get_caps()
2610 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | in mt7988_mac_port_get_caps()
2618 struct mt7530_priv *priv = ds->priv; in mt753x_pad_setup()
2620 return priv->info->pad_setup(ds, state->interface); in mt753x_pad_setup()
2627 struct mt7530_priv *priv = ds->priv; in mt7530_mac_config()
2633 mt7530_setup_port5(priv->ds, interface); in mt7530_mac_config()
2645 dev_err(priv->dev, "RGMII mode is not available for port %d\n", in mt7531_rgmii_setup()
2647 return -EINVAL; in mt7531_rgmii_setup()
2677 return -EINVAL; in mt7531_rgmii_setup()
2698 return -EINVAL; in mt7988_mac_config()
2705 struct mt7530_priv *priv = ds->priv; in mt7531_mac_config()
2710 dev_err(priv->dev, "port %d is not a MAC port\n", port); in mt7531_mac_config()
2711 return -EINVAL; in mt7531_mac_config()
2720 phydev = dp->user->phydev; in mt7531_mac_config()
2726 /* handled in SGMII PCS driver */ in mt7531_mac_config()
2729 return -EINVAL; in mt7531_mac_config()
2732 return -EINVAL; in mt7531_mac_config()
2739 struct mt7530_priv *priv = ds->priv; in mt753x_mac_config()
2741 return priv->info->mac_port_config(ds, port, mode, state->interface); in mt753x_mac_config()
2748 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_mac_select_pcs()
2752 return &priv->pcs[port].pcs; in mt753x_phylink_mac_select_pcs()
2756 return priv->ports[port].sgmii_pcs; in mt753x_phylink_mac_select_pcs()
2766 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_mac_config()
2771 if (state->interface != PHY_INTERFACE_MODE_GMII && in mt753x_phylink_mac_config()
2772 state->interface != PHY_INTERFACE_MODE_INTERNAL) in mt753x_phylink_mac_config()
2776 if (priv->p5_interface == state->interface) in mt753x_phylink_mac_config()
2782 if (priv->p5_intf_sel != P5_DISABLED) in mt753x_phylink_mac_config()
2783 priv->p5_interface = state->interface; in mt753x_phylink_mac_config()
2786 if (priv->p6_interface == state->interface) in mt753x_phylink_mac_config()
2794 priv->p6_interface = state->interface; in mt753x_phylink_mac_config()
2798 dev_err(ds->dev, "%s: unsupported %s port: %i\n", in mt753x_phylink_mac_config()
2799 __func__, phy_modes(state->interface), port); in mt753x_phylink_mac_config()
2807 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id); in mt753x_phylink_mac_config()
2821 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_mac_link_down()
2833 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_mac_link_up()
2838 /* MT753x MAC works in 1G full duplex mode for all up-clocked in mt753x_phylink_mac_link_up()
2880 struct mt7530_priv *priv = ds->priv; in mt7531_cpu_port_config()
2892 priv->p5_interface = interface; in mt7531_cpu_port_config()
2897 priv->p6_interface = interface; in mt7531_cpu_port_config()
2900 return -EINVAL; in mt7531_cpu_port_config()
2912 PMCR_CPU_PORT_SETTING(priv->id)); in mt7531_cpu_port_config()
2922 struct mt7530_priv *priv = ds->priv; in mt7988_cpu_port_config()
2925 PMCR_CPU_PORT_SETTING(priv->id)); in mt7988_cpu_port_config()
2937 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_get_caps()
2939 /* This switch only supports full-duplex at 1Gbps */ in mt753x_phylink_get_caps()
2940 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | in mt753x_phylink_get_caps()
2943 priv->info->mac_port_get_caps(ds, port, config); in mt753x_phylink_get_caps()
2951 if (state->interface == PHY_INTERFACE_MODE_TRGMII || in mt753x_pcs_validate()
2952 phy_interface_mode_is_8023z(state->interface)) in mt753x_pcs_validate()
2961 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; in mt7530_pcs_get_state()
2962 int port = pcs_to_mt753x_pcs(pcs)->port; in mt7530_pcs_get_state()
2967 state->link = (pmsr & PMSR_LINK); in mt7530_pcs_get_state()
2968 state->an_complete = state->link; in mt7530_pcs_get_state()
2969 state->duplex = !!(pmsr & PMSR_DPX); in mt7530_pcs_get_state()
2973 state->speed = SPEED_10; in mt7530_pcs_get_state()
2976 state->speed = SPEED_100; in mt7530_pcs_get_state()
2979 state->speed = SPEED_1000; in mt7530_pcs_get_state()
2982 state->speed = SPEED_UNKNOWN; in mt7530_pcs_get_state()
2986 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); in mt7530_pcs_get_state()
2988 state->pause |= MLO_PAUSE_RX; in mt7530_pcs_get_state()
2990 state->pause |= MLO_PAUSE_TX; in mt7530_pcs_get_state()
3015 struct mt7530_priv *priv = ds->priv; in mt753x_setup()
3019 for (i = 0; i < priv->ds->num_ports; i++) { in mt753x_setup()
3020 priv->pcs[i].pcs.ops = priv->info->pcs_ops; in mt753x_setup()
3021 priv->pcs[i].pcs.neg_mode = true; in mt753x_setup()
3022 priv->pcs[i].priv = priv; in mt753x_setup()
3023 priv->pcs[i].port = i; in mt753x_setup()
3026 ret = priv->info->sw_setup(ds); in mt753x_setup()
3035 if (ret && priv->irq) in mt753x_setup()
3038 if (priv->create_sgmii) { in mt753x_setup()
3039 ret = priv->create_sgmii(priv, mt7531_dual_sgmii_supported(priv)); in mt753x_setup()
3040 if (ret && priv->irq) in mt753x_setup()
3050 struct mt7530_priv *priv = ds->priv; in mt753x_get_mac_eee()
3053 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN); in mt753x_get_mac_eee()
3054 e->tx_lpi_timer = GET_LPI_THRESH(eeecr); in mt753x_get_mac_eee()
3062 struct mt7530_priv *priv = ds->priv; in mt753x_set_mac_eee()
3065 if (e->tx_lpi_timer > 0xFFF) in mt753x_set_mac_eee()
3066 return -EINVAL; in mt753x_set_mac_eee()
3068 set = SET_LPI_THRESH(e->tx_lpi_timer); in mt753x_set_mac_eee()
3069 if (!e->tx_lpi_enabled) in mt753x_set_mac_eee()
3084 struct mt7530_priv *priv = ds->priv; in mt7988_setup()
3087 reset_control_assert(priv->rstc); in mt7988_setup()
3089 reset_control_deassert(priv->rstc); in mt7988_setup()
3192 struct device *dev = priv->dev; in mt7530_probe_common()
3194 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); in mt7530_probe_common()
3195 if (!priv->ds) in mt7530_probe_common()
3196 return -ENOMEM; in mt7530_probe_common()
3198 priv->ds->dev = dev; in mt7530_probe_common()
3199 priv->ds->num_ports = MT7530_NUM_PORTS; in mt7530_probe_common()
3204 priv->info = of_device_get_match_data(dev); in mt7530_probe_common()
3205 if (!priv->info) in mt7530_probe_common()
3206 return -EINVAL; in mt7530_probe_common()
3211 if (!priv->info->sw_setup || !priv->info->pad_setup || in mt7530_probe_common()
3212 !priv->info->phy_read_c22 || !priv->info->phy_write_c22 || in mt7530_probe_common()
3213 !priv->info->mac_port_get_caps || in mt7530_probe_common()
3214 !priv->info->mac_port_config) in mt7530_probe_common()
3215 return -EINVAL; in mt7530_probe_common()
3217 priv->id = priv->info->id; in mt7530_probe_common()
3218 priv->dev = dev; in mt7530_probe_common()
3219 priv->ds->priv = priv; in mt7530_probe_common()
3220 priv->ds->ops = &mt7530_switch_ops; in mt7530_probe_common()
3221 mutex_init(&priv->reg_mutex); in mt7530_probe_common()
3231 if (priv->irq) in mt7530_remove_common()
3234 dsa_unregister_switch(priv->ds); in mt7530_remove_common()
3236 mutex_destroy(&priv->reg_mutex); in mt7530_remove_common()