Lines Matching full:7
13 #define SW_PHY_REG_BLOCK BIT(7)
43 #define SW_DOUBLE_TAG BIT(7)
49 #define SW_VLAN_ENABLE BIT(7)
57 #define UNICAST_LEARN_DISABLE BIT(7)
66 #define SW_AGE_PERIOD_7_0_M GENMASK(7, 0)
72 #define SW_NEW_BACKOFF BIT(7)
77 #define SW_SHORT_IFG BIT(7)
86 #define SW_MIB_COUNTER_FLUSH BIT(7)
97 /* 7 - VPhy */
117 #define VPHY_SW_COLLISION_TEST BIT(7)
141 #define PORT_MAC_LOOPBACK BIT(7)
152 #define PORT_SGMII_SEL BIT(7)
161 #define PORT_TUNE_ADJ GENMASK(13, 7)
178 #define PORT_HIGHEST_PRIO BIT(7)