Lines Matching +full:1 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
18 #define SW_REVISION_S 1
22 #define KSZ8863_GLOBAL_SOFTWARE_RESET BIT(4)
23 #define KSZ8863_PCS_RESET BIT(0)
26 #define KSZ88X3_PORT3_RMII_CLK_INTERNAL BIT(3)
30 #define SW_NEW_BACKOFF BIT(7)
31 #define SW_GLOBAL_RESET BIT(6)
32 #define SW_FLUSH_DYN_MAC_TABLE BIT(5)
33 #define SW_FLUSH_STA_MAC_TABLE BIT(4)
34 #define SW_LINK_AUTO_AGING BIT(0)
38 #define SW_HUGE_PACKET BIT(6)
39 #define SW_TX_FLOW_CTRL_DISABLE BIT(5)
40 #define SW_RX_FLOW_CTRL_DISABLE BIT(4)
41 #define SW_CHECK_LENGTH BIT(3)
42 #define SW_AGING_ENABLE BIT(2)
43 #define SW_FAST_AGING BIT(1)
44 #define SW_AGGR_BACKOFF BIT(0)
48 #define UNICAST_VLAN_BOUNDARY BIT(7)
49 #define SW_BACK_PRESSURE BIT(5)
50 #define FAIR_FLOW_CTRL BIT(4)
51 #define NO_EXC_COLLISION_DROP BIT(3)
52 #define SW_LEGAL_PACKET_DISABLE BIT(1)
54 #define KSZ8863_HUGE_PACKET_ENABLE BIT(2)
55 #define KSZ8863_LEGAL_PACKET_ENABLE BIT(1)
58 #define WEIGHTED_FAIR_QUEUE_ENABLE BIT(3)
60 #define SW_VLAN_ENABLE BIT(7)
61 #define SW_IGMP_SNOOP BIT(6)
62 #define SW_MIRROR_RX_TX BIT(0)
66 #define SW_HALF_DUPLEX_FLOW_CTRL BIT(7)
67 #define SW_HALF_DUPLEX BIT(6)
68 #define SW_FLOW_CTRL BIT(5)
69 #define SW_10_MBIT BIT(4)
70 #define SW_REPLACE_VID BIT(3)
76 #define SW_MIB_COUNTER_FLUSH BIT(7)
77 #define SW_MIB_COUNTER_FREEZE BIT(6)
89 #define SW_LED_LINK_ACT 1
95 #define SW_PASS_PAUSE BIT(0)
101 #define SW_PLL_POWER_DOWN BIT(5)
105 #define SW_ENERGY_DETECTION 1
116 #define PORT_BROADCAST_STORM BIT(7)
117 #define PORT_DIFFSERV_ENABLE BIT(6)
118 #define PORT_802_1P_ENABLE BIT(5)
122 #define PORT_BASED_PRIO_1 1
125 #define PORT_INSERT_TAG BIT(2)
126 #define PORT_REMOVE_TAG BIT(1)
127 #define PORT_QUEUE_SPLIT_L BIT(0)
135 #define PORT_MIRROR_SNIFFER BIT(7)
136 #define PORT_MIRROR_RX BIT(6)
137 #define PORT_MIRROR_TX BIT(5)
146 #define PORT_INGRESS_FILTER BIT(6)
147 #define PORT_DISCARD_NON_VID BIT(5)
148 #define PORT_FORCE_FLOW_CTRL BIT(4)
149 #define PORT_BACK_PRESSURE BIT(3)
170 #define PORT_ACL_ENABLE BIT(2)
173 #define PORT_AUTHEN_BLOCK 1
178 #define PORT_MII_INTERNAL_CLOCK BIT(7)
179 #define PORT_GMII_MAC_MODE BIT(2)
186 #define PORT_AUTO_NEG_ASYM_PAUSE BIT(5)
187 #define PORT_AUTO_NEG_SYM_PAUSE BIT(4)
188 #define PORT_AUTO_NEG_100BTX_FD BIT(3)
189 #define PORT_AUTO_NEG_100BTX BIT(2)
190 #define PORT_AUTO_NEG_10BT_FD BIT(1)
191 #define PORT_AUTO_NEG_10BT BIT(0)
199 #define PORT_REMOTE_ASYM_PAUSE BIT(5)
200 #define PORT_REMOTE_SYM_PAUSE BIT(4)
201 #define PORT_REMOTE_100BTX_FD BIT(3)
202 #define PORT_REMOTE_100BTX BIT(2)
203 #define PORT_REMOTE_10BT_FD BIT(1)
204 #define PORT_REMOTE_10BT BIT(0)
211 #define PORT_HP_MDIX BIT(7)
212 #define PORT_REVERSED_POLARITY BIT(5)
213 #define PORT_TX_FLOW_CTRL BIT(4)
214 #define PORT_RX_FLOW_CTRL BIT(3)
215 #define PORT_STAT_SPEED_100MBIT BIT(2)
216 #define PORT_STAT_FULL_DUPLEX BIT(1)
218 #define PORT_REMOTE_FAULT BIT(0)
225 #define PORT_CABLE_10M_SHORT BIT(7)
229 #define PORT_CABLE_STAT_OPEN 1
232 #define PORT_START_CABLE_DIAG BIT(4)
233 #define PORT_FORCE_LINK BIT(3)
234 #define PORT_POWER_SAVING BIT(2)
235 #define PORT_PHY_REMOTE_LOOPBACK BIT(1)
251 #define PORT_AUTO_NEG_ENABLE BIT(7)
252 #define PORT_AUTO_NEG_DISABLE BIT(7)
253 #define PORT_FORCE_100_MBIT BIT(6)
254 #define PORT_FORCE_FULL_DUPLEX BIT(5)
261 #define PORT_LED_OFF BIT(7)
262 #define PORT_TX_DISABLE BIT(6)
263 #define PORT_AUTO_NEG_RESTART BIT(5)
264 #define PORT_POWER_DOWN BIT(3)
265 #define PORT_AUTO_MDIX_DISABLE BIT(2)
266 #define PORT_FORCE_MDIX BIT(1)
267 #define PORT_MAC_LOOPBACK BIT(0)
274 #define PORT_MDIX_STATUS BIT(7)
275 #define PORT_AUTO_NEG_COMPLETE BIT(6)
276 #define PORT_STAT_LINK_GOOD BIT(5)
283 #define PORT_PHY_LOOPBACK BIT(7)
284 #define PORT_PHY_ISOLATE BIT(5)
285 #define PORT_PHY_SOFT_RESET BIT(4)
286 #define PORT_PHY_FORCE_LINK BIT(3)
288 #define PHY_MODE_IN_AUTO_NEG 1
327 (REG_PORT_2_CTRL_0 - REG_PORT_1_CTRL_0))
330 #define TABLE_EEE_V 1
338 #define TABLE_READ BIT(4)
341 #define TABLE_VLAN_V 1
364 #define INT_PME BIT(4)
369 #define INT_PORT_5 BIT(4)
370 #define INT_PORT_4 BIT(3)
371 #define INT_PORT_3 BIT(2)
372 #define INT_PORT_2 BIT(1)
373 #define INT_PORT_1 BIT(0)
401 #define SW_SELF_ADDR_FILTER_ENABLE BIT(6)
408 #define SW_UNK_FWD_ENABLE BIT(5)
416 #define SW_IN_RATE_LIMIT_64_MS 1
418 #define SW_OUT_RATE_LIMIT_QUEUE_BASED BIT(3)
419 #define SW_INS_TAG_ENABLE BIT(2)
443 #define SW_IPV6_MLD_OPTION BIT(3)
444 #define SW_IPV6_MLD_SNOOP BIT(2)
452 #define PORT_PASS_ALL BIT(6)
454 #define PORT_INS_TAG_FOR_PORT_5 BIT(3)
455 #define PORT_INS_TAG_FOR_PORT_4 BIT(2)
456 #define PORT_INS_TAG_FOR_PORT_3 BIT(1)
457 #define PORT_INS_TAG_FOR_PORT_2 BIT(0)
465 #define PORT_QUEUE_SPLIT_H BIT(1)
467 #define PORT_QUEUE_SPLIT_2 1
469 #define PORT_DROP_TAG BIT(0)
513 #define RATE_CTRL_ENABLE BIT(7)
514 #define RATE_RATIO_M (BIT(7) - 1)
516 #define PORT_OUT_RATE_ENABLE BIT(7)
529 #define PORT_COUNT_IFG_S 1
531 #define PORT_IN_PORT_BASED BIT(PORT_IN_PORT_BASED_S)
532 #define PORT_RATE_PACKET_BASED BIT(PORT_RATE_PACKET_BASED_S)
533 #define PORT_IN_FLOW_CTRL BIT(PORT_IN_FLOW_CTRL_S)
535 #define PORT_IN_UNICAST 1
538 #define PORT_COUNT_IFG BIT(PORT_COUNT_IFG_S)
539 #define PORT_COUNT_PREAMBLE BIT(PORT_COUNT_PREAMBLE_S)
562 #define PORT_IN_RATE_ENABLE BIT(7)
563 #define PORT_RATE_LIMIT_M (BIT(7) - 1)
592 #define SW_PME_OUTPUT_ENABLE BIT(1)
593 #define SW_PME_ACTIVE_HIGH BIT(0)
595 #define PORT_MAGIC_PACKET_DETECT BIT(2)
596 #define PORT_LINK_UP_DETECT BIT(1)
597 #define PORT_ENERGY_DETECT BIT(0)
606 #define ACL_MODE_LAYER_2 1
612 #define ACL_ENABLE_2_TYPE 1
615 #define ACL_ENABLE_3_IP 1
618 #define ACL_ENABLE_4_TCP_PORT_COMP 1
621 #define ACL_SRC BIT(1)
622 #define ACL_EQUAL BIT(0)
632 #define ACL_PORT_MODE_S 1
634 #define ACL_PORT_MODE_EITHER 1
638 #define ACL_TCP_FLAG_ENABLE BIT(0)
649 #define ACL_PRIO_MODE_HIGHER 1
654 #define ACL_VLAN_PRIO_REPLACE BIT(2)
663 #define ACL_MAP_MODE_OR 1
668 #define ACL_CNT_M (BIT(11) - 1)
670 #define ACL_MSEC_UNIT BIT(4)
671 #define ACL_INTR_MODE BIT(3)
694 #define PORT_ACL_WRITE_DONE BIT(6)
695 #define PORT_ACL_READ_DONE BIT(5)
696 #define PORT_ACL_WRITE BIT(4)
701 #define PORT_ACL_FORCE_DLR_MISS BIT(0)
711 #define PHY_START_CABLE_DIAG BIT(15)
718 #define PHY_CABLE_10M_SHORT BIT(12)
725 #define PHY_STAT_REVERSED_POLARITY BIT(5)
726 #define PHY_STAT_MDIX BIT(4)
727 #define PHY_FORCE_LINK BIT(3)
728 #define PHY_POWER_SAVING_ENABLE BIT(2)
729 #define PHY_REMOTE_LOOPBACK BIT(1)
771 * MIB_COUNTER_VALUE 00-00000000-3FFFFFFF
772 * MIB_TOTAL_BYTES 00-0000000F-FFFFFFFF
773 * MIB_PACKET_DROPPED 00-00000000-0000FFFF
774 * MIB_COUNTER_VALID 00-00000020-00000000
775 * MIB_COUNTER_OVERFLOW 00-00000040-00000000
792 #define TAIL_TAG_OVERRIDE BIT(6)
793 #define TAIL_TAG_LOOKUP BIT(7)