Lines Matching +full:port +full:- +full:mapping +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (C) 2017 - 2019 Hauke Mehrtens <hauke@hauke-m.de>
16 * The hardware does not support VLAN filter on the port, but on the
20 * rule and the CPU port is also added to all bridges. This makes it possible
23 * each switch port which is used when the port is used without an
46 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
64 #define GSWIP_MDIO_PHYp(p) (0x15 - (p))
135 #define GSWIP_BM_RAM_VAL(x) (0x043 - (x))
143 /* buffer management Port Configuration Register */
147 /* buffer management Port Control Register */
153 #define GSWIP_PCE_TBL_KEY(x) (0x447 - (x))
155 #define GSWIP_PCE_TBL_VAL(x) (0x44D - (x))
169 #define GSWIP_PCE_PMAP1 0x453 /* Monitoring port map */
170 #define GSWIP_PCE_PMAP2 0x454 /* Default Multicast port map */
171 #define GSWIP_PCE_PMAP3 0x455 /* Default Unknown Unicast port map */
178 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK_MOD BIT(3) /* Mac address table lock forwarding mode */
180 #define GSWIP_PCE_PCTRL_0_TVM BIT(5) /* Transparent VLAN mode */
181 #define GSWIP_PCE_PCTRL_0_VREP BIT(6) /* VLAN Replace Mode */
219 /* Ethernet Switch Fetch DMA Port Control Register */
221 #define GSWIP_FDMA_PCTRL_EN BIT(0) /* FDMA Port Enable */
230 /* Ethernet Switch Store DMA Port Control Register */
232 #define GSWIP_SDMA_PCTRL_EN BIT(0) /* SDMA Port Enable */
244 * but long packets currently cause lock-ups with an MTU of over 2526. Medium
245 * packets are sometimes dropped (e.g. TCP over 2477, UDP over 2516-2519, ICMP
293 u16 index; // PCE_TBL_ADDR.ADDR = pData->table_index
294 u16 table; // PCE_TBL_CTRL.ADDR = pData->table
329 /** Receive Size 1024-1522 (or more, if configured) Packet Count. */
344 /** Transmit Size 1024-1522 (or more, if configured) Packet Count. */
357 return __raw_readl(priv->gswip + (offset * 4)); in gswip_switch_r()
362 __raw_writel(val, priv->gswip + (offset * 4)); in gswip_switch_w()
380 return readx_poll_timeout(__raw_readl, priv->gswip + (offset * 4), val, in gswip_switch_r_timeout()
386 return __raw_readl(priv->mdio + (offset * 4)); in gswip_mdio_r()
391 __raw_writel(val, priv->mdio + (offset * 4)); in gswip_mdio_w()
406 return __raw_readl(priv->mii + (offset * 4)); in gswip_mii_r()
411 __raw_writel(val, priv->mii + (offset * 4)); in gswip_mii_w()
425 int port) in gswip_mii_mask_cfg() argument
427 /* There's no MII_CFG register for the CPU port */ in gswip_mii_mask_cfg()
428 if (!dsa_is_cpu_port(priv->ds, port)) in gswip_mii_mask_cfg()
429 gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(port)); in gswip_mii_mask_cfg()
433 int port) in gswip_mii_mask_pcdu() argument
435 switch (port) { in gswip_mii_mask_pcdu()
452 while (likely(cnt--)) { in gswip_mdio_poll()
460 return -ETIMEDOUT; in gswip_mdio_poll()
465 struct gswip_priv *priv = bus->priv; in gswip_mdio_wr()
470 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); in gswip_mdio_wr()
485 struct gswip_priv *priv = bus->priv; in gswip_mdio_rd()
490 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); in gswip_mdio_rd()
501 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); in gswip_mdio_rd()
510 struct device_node *mdio_np, *switch_np = priv->dev->of_node; in gswip_mdio()
511 struct device *dev = priv->dev; in gswip_mdio()
515 mdio_np = of_get_compatible_child(switch_np, "lantiq,xrx200-mdio"); in gswip_mdio()
521 err = -ENOMEM; in gswip_mdio()
525 bus->priv = priv; in gswip_mdio()
526 bus->read = gswip_mdio_rd; in gswip_mdio()
527 bus->write = gswip_mdio_wr; in gswip_mdio()
528 bus->name = "lantiq,xrx200-mdio"; in gswip_mdio()
529 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(priv->dev)); in gswip_mdio()
530 bus->parent = priv->dev; in gswip_mdio()
546 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSRD : in gswip_pce_table_entry_read()
549 mutex_lock(&priv->pce_table_lock); in gswip_pce_table_entry_read()
554 mutex_unlock(&priv->pce_table_lock); in gswip_pce_table_entry_read()
558 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR); in gswip_pce_table_entry_read()
561 tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS, in gswip_pce_table_entry_read()
567 mutex_unlock(&priv->pce_table_lock); in gswip_pce_table_entry_read()
571 for (i = 0; i < ARRAY_SIZE(tbl->key); i++) in gswip_pce_table_entry_read()
572 tbl->key[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_KEY(i)); in gswip_pce_table_entry_read()
574 for (i = 0; i < ARRAY_SIZE(tbl->val); i++) in gswip_pce_table_entry_read()
575 tbl->val[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_VAL(i)); in gswip_pce_table_entry_read()
577 tbl->mask = gswip_switch_r(priv, GSWIP_PCE_TBL_MASK); in gswip_pce_table_entry_read()
581 tbl->type = !!(crtl & GSWIP_PCE_TBL_CTRL_TYPE); in gswip_pce_table_entry_read()
582 tbl->valid = !!(crtl & GSWIP_PCE_TBL_CTRL_VLD); in gswip_pce_table_entry_read()
583 tbl->gmap = (crtl & GSWIP_PCE_TBL_CTRL_GMAP_MASK) >> 7; in gswip_pce_table_entry_read()
585 mutex_unlock(&priv->pce_table_lock); in gswip_pce_table_entry_read()
596 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSWR : in gswip_pce_table_entry_write()
599 mutex_lock(&priv->pce_table_lock); in gswip_pce_table_entry_write()
604 mutex_unlock(&priv->pce_table_lock); in gswip_pce_table_entry_write()
608 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR); in gswip_pce_table_entry_write()
611 tbl->table | addr_mode, in gswip_pce_table_entry_write()
614 for (i = 0; i < ARRAY_SIZE(tbl->key); i++) in gswip_pce_table_entry_write()
615 gswip_switch_w(priv, tbl->key[i], GSWIP_PCE_TBL_KEY(i)); in gswip_pce_table_entry_write()
617 for (i = 0; i < ARRAY_SIZE(tbl->val); i++) in gswip_pce_table_entry_write()
618 gswip_switch_w(priv, tbl->val[i], GSWIP_PCE_TBL_VAL(i)); in gswip_pce_table_entry_write()
622 tbl->table | addr_mode, in gswip_pce_table_entry_write()
625 gswip_switch_w(priv, tbl->mask, GSWIP_PCE_TBL_MASK); in gswip_pce_table_entry_write()
630 if (tbl->type) in gswip_pce_table_entry_write()
632 if (tbl->valid) in gswip_pce_table_entry_write()
634 crtl |= (tbl->gmap << 7) & GSWIP_PCE_TBL_CTRL_GMAP_MASK; in gswip_pce_table_entry_write()
641 mutex_unlock(&priv->pce_table_lock); in gswip_pce_table_entry_write()
646 /* Add the LAN port into a bridge with the CPU port by
651 static int gswip_add_single_port_br(struct gswip_priv *priv, int port, bool add) in gswip_add_single_port_br() argument
655 unsigned int cpu_port = priv->hw_info->cpu_port; in gswip_add_single_port_br()
656 unsigned int max_ports = priv->hw_info->max_ports; in gswip_add_single_port_br()
659 if (port >= max_ports) { in gswip_add_single_port_br()
660 dev_err(priv->dev, "single port for %i supported\n", port); in gswip_add_single_port_br()
661 return -EIO; in gswip_add_single_port_br()
664 vlan_active.index = port + 1; in gswip_add_single_port_br()
667 vlan_active.val[0] = port + 1 /* fid */; in gswip_add_single_port_br()
671 dev_err(priv->dev, "failed to write active VLAN: %d\n", err); in gswip_add_single_port_br()
678 vlan_mapping.index = port + 1; in gswip_add_single_port_br()
681 vlan_mapping.val[1] = BIT(port) | BIT(cpu_port); in gswip_add_single_port_br()
685 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); in gswip_add_single_port_br()
692 static int gswip_port_enable(struct dsa_switch *ds, int port, in gswip_port_enable() argument
695 struct gswip_priv *priv = ds->priv; in gswip_port_enable()
698 if (!dsa_is_user_port(ds, port)) in gswip_port_enable()
701 if (!dsa_is_cpu_port(ds, port)) { in gswip_port_enable()
702 err = gswip_add_single_port_br(priv, port, true); in gswip_port_enable()
707 /* RMON Counter Enable for port */ in gswip_port_enable()
708 gswip_switch_w(priv, GSWIP_BM_PCFG_CNTEN, GSWIP_BM_PCFGp(port)); in gswip_port_enable()
710 /* enable port fetch/store dma & VLAN Modification */ in gswip_port_enable()
713 GSWIP_FDMA_PCTRLp(port)); in gswip_port_enable()
715 GSWIP_SDMA_PCTRLp(port)); in gswip_port_enable()
717 if (!dsa_is_cpu_port(ds, port)) { in gswip_port_enable()
721 mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK; in gswip_port_enable()
724 GSWIP_MDIO_PHYp(port)); in gswip_port_enable()
730 static void gswip_port_disable(struct dsa_switch *ds, int port) in gswip_port_disable() argument
732 struct gswip_priv *priv = ds->priv; in gswip_port_disable()
734 if (!dsa_is_user_port(ds, port)) in gswip_port_disable()
738 GSWIP_FDMA_PCTRLp(port)); in gswip_port_disable()
740 GSWIP_SDMA_PCTRLp(port)); in gswip_port_disable()
780 static int gswip_port_vlan_filtering(struct dsa_switch *ds, int port, in gswip_port_vlan_filtering() argument
784 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); in gswip_port_vlan_filtering()
785 struct gswip_priv *priv = ds->priv; in gswip_port_vlan_filtering()
788 if (bridge && !!(priv->port_vlan_filter & BIT(port)) != vlan_filtering) { in gswip_port_vlan_filtering()
791 return -EIO; in gswip_port_vlan_filtering()
795 /* Use port based VLAN tag */ in gswip_port_vlan_filtering()
800 GSWIP_PCE_VCTRL(port)); in gswip_port_vlan_filtering()
802 GSWIP_PCE_PCTRL_0p(port)); in gswip_port_vlan_filtering()
804 /* Use port based VLAN tag */ in gswip_port_vlan_filtering()
809 GSWIP_PCE_VCTRL(port)); in gswip_port_vlan_filtering()
811 GSWIP_PCE_PCTRL_0p(port)); in gswip_port_vlan_filtering()
819 struct gswip_priv *priv = ds->priv; in gswip_setup()
820 unsigned int cpu_port = priv->hw_info->cpu_port; in gswip_setup()
828 /* disable port fetch/store dma on all ports */ in gswip_setup()
829 for (i = 0; i < priv->hw_info->max_ports; i++) { in gswip_setup()
839 dev_err(priv->dev, "writing PCE microcode failed, %i", err); in gswip_setup()
843 /* Default unknown Broadcast/Multicast/Unicast port maps */ in gswip_setup()
855 * to the switch port being completely dead (RX and TX are both not in gswip_setup()
857 * Also with various other PHY / port combinations (PHY11G GPHY, PHY22F in gswip_setup()
870 for (i = 0; i < priv->hw_info->max_ports; i++) in gswip_setup()
875 /* enable special tag insertion on cpu port */ in gswip_setup()
895 dev_err(priv->dev, "MAC flushing didn't finish\n"); in gswip_setup()
899 ds->mtu_enforcement_ingress = true; in gswip_setup()
903 ds->configure_vlan_while_not_filtering = false; in gswip_setup()
909 int port, in gswip_get_tag_protocol() argument
920 unsigned int max_ports = priv->hw_info->max_ports; in gswip_vlan_active_create()
921 int idx = -1; in gswip_vlan_active_create()
926 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { in gswip_vlan_active_create()
927 if (!priv->vlans[i].bridge) { in gswip_vlan_active_create()
933 if (idx == -1) in gswip_vlan_active_create()
934 return -ENOSPC; in gswip_vlan_active_create()
936 if (fid == -1) in gswip_vlan_active_create()
947 dev_err(priv->dev, "failed to write active VLAN: %d\n", err); in gswip_vlan_active_create()
951 priv->vlans[idx].bridge = bridge; in gswip_vlan_active_create()
952 priv->vlans[idx].vid = vid; in gswip_vlan_active_create()
953 priv->vlans[idx].fid = fid; in gswip_vlan_active_create()
968 dev_err(priv->dev, "failed to delete active VLAN: %d\n", err); in gswip_vlan_active_remove()
969 priv->vlans[idx].bridge = NULL; in gswip_vlan_active_remove()
975 struct net_device *bridge, int port) in gswip_vlan_add_unaware() argument
978 unsigned int max_ports = priv->hw_info->max_ports; in gswip_vlan_add_unaware()
979 unsigned int cpu_port = priv->hw_info->cpu_port; in gswip_vlan_add_unaware()
981 int idx = -1; in gswip_vlan_add_unaware()
986 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { in gswip_vlan_add_unaware()
987 if (priv->vlans[i].bridge == bridge) { in gswip_vlan_add_unaware()
994 * entry in a free slot and prepare the VLAN mapping table entry. in gswip_vlan_add_unaware()
996 if (idx == -1) { in gswip_vlan_add_unaware()
997 idx = gswip_vlan_active_create(priv, bridge, -1, 0); in gswip_vlan_add_unaware()
1007 /* Read the existing VLAN mapping entry from the switch */ in gswip_vlan_add_unaware()
1012 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", in gswip_vlan_add_unaware()
1018 /* Update the VLAN mapping entry and write it to the switch */ in gswip_vlan_add_unaware()
1020 vlan_mapping.val[1] |= BIT(port); in gswip_vlan_add_unaware()
1023 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); in gswip_vlan_add_unaware()
1030 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port)); in gswip_vlan_add_unaware()
1035 struct net_device *bridge, int port, in gswip_vlan_add_aware() argument
1040 unsigned int max_ports = priv->hw_info->max_ports; in gswip_vlan_add_aware()
1041 unsigned int cpu_port = priv->hw_info->cpu_port; in gswip_vlan_add_aware()
1043 int idx = -1; in gswip_vlan_add_aware()
1044 int fid = -1; in gswip_vlan_add_aware()
1049 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { in gswip_vlan_add_aware()
1050 if (priv->vlans[i].bridge == bridge) { in gswip_vlan_add_aware()
1051 if (fid != -1 && fid != priv->vlans[i].fid) in gswip_vlan_add_aware()
1052 dev_err(priv->dev, "one bridge with multiple flow ids\n"); in gswip_vlan_add_aware()
1053 fid = priv->vlans[i].fid; in gswip_vlan_add_aware()
1054 if (priv->vlans[i].vid == vid) { in gswip_vlan_add_aware()
1062 * entry in a free slot and prepare the VLAN mapping table entry. in gswip_vlan_add_aware()
1064 if (idx == -1) { in gswip_vlan_add_aware()
1075 /* Read the existing VLAN mapping entry from the switch */ in gswip_vlan_add_aware()
1080 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", in gswip_vlan_add_aware()
1087 /* Update the VLAN mapping entry and write it to the switch */ in gswip_vlan_add_aware()
1090 vlan_mapping.val[1] |= BIT(port); in gswip_vlan_add_aware()
1092 vlan_mapping.val[2] &= ~BIT(port); in gswip_vlan_add_aware()
1094 vlan_mapping.val[2] |= BIT(port); in gswip_vlan_add_aware()
1097 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); in gswip_vlan_add_aware()
1105 gswip_switch_w(priv, idx, GSWIP_PCE_DEFPVID(port)); in gswip_vlan_add_aware()
1111 struct net_device *bridge, int port, in gswip_vlan_remove() argument
1115 unsigned int max_ports = priv->hw_info->max_ports; in gswip_vlan_remove()
1116 unsigned int cpu_port = priv->hw_info->cpu_port; in gswip_vlan_remove()
1117 int idx = -1; in gswip_vlan_remove()
1122 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { in gswip_vlan_remove()
1123 if (priv->vlans[i].bridge == bridge && in gswip_vlan_remove()
1124 (!vlan_aware || priv->vlans[i].vid == vid)) { in gswip_vlan_remove()
1130 if (idx == -1) { in gswip_vlan_remove()
1131 dev_err(priv->dev, "bridge to leave does not exists\n"); in gswip_vlan_remove()
1132 return -ENOENT; in gswip_vlan_remove()
1139 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", err); in gswip_vlan_remove()
1143 vlan_mapping.val[1] &= ~BIT(port); in gswip_vlan_remove()
1144 vlan_mapping.val[2] &= ~BIT(port); in gswip_vlan_remove()
1147 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); in gswip_vlan_remove()
1155 dev_err(priv->dev, "failed to write active VLAN: %d\n", in gswip_vlan_remove()
1163 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port)); in gswip_vlan_remove()
1168 static int gswip_port_bridge_join(struct dsa_switch *ds, int port, in gswip_port_bridge_join() argument
1174 struct gswip_priv *priv = ds->priv; in gswip_port_bridge_join()
1181 err = gswip_vlan_add_unaware(priv, br, port); in gswip_port_bridge_join()
1184 priv->port_vlan_filter &= ~BIT(port); in gswip_port_bridge_join()
1186 priv->port_vlan_filter |= BIT(port); in gswip_port_bridge_join()
1188 return gswip_add_single_port_br(priv, port, false); in gswip_port_bridge_join()
1191 static void gswip_port_bridge_leave(struct dsa_switch *ds, int port, in gswip_port_bridge_leave() argument
1195 struct gswip_priv *priv = ds->priv; in gswip_port_bridge_leave()
1197 gswip_add_single_port_br(priv, port, true); in gswip_port_bridge_leave()
1203 gswip_vlan_remove(priv, br, port, 0, true, false); in gswip_port_bridge_leave()
1206 static int gswip_port_vlan_prepare(struct dsa_switch *ds, int port, in gswip_port_vlan_prepare() argument
1210 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); in gswip_port_vlan_prepare()
1211 struct gswip_priv *priv = ds->priv; in gswip_port_vlan_prepare()
1212 unsigned int max_ports = priv->hw_info->max_ports; in gswip_port_vlan_prepare()
1214 int i, idx = -1; in gswip_port_vlan_prepare()
1217 if (!dsa_is_cpu_port(ds, port) && !bridge) in gswip_port_vlan_prepare()
1218 return -EOPNOTSUPP; in gswip_port_vlan_prepare()
1221 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { in gswip_port_vlan_prepare()
1222 if (priv->vlans[i].bridge == bridge && in gswip_port_vlan_prepare()
1223 priv->vlans[i].vid == vlan->vid) { in gswip_port_vlan_prepare()
1233 if (idx == -1) { in gswip_port_vlan_prepare()
1235 for (; pos < ARRAY_SIZE(priv->vlans); pos++) { in gswip_port_vlan_prepare()
1236 if (!priv->vlans[pos].bridge) { in gswip_port_vlan_prepare()
1243 if (idx == -1) { in gswip_port_vlan_prepare()
1245 return -ENOSPC; in gswip_port_vlan_prepare()
1252 static int gswip_port_vlan_add(struct dsa_switch *ds, int port, in gswip_port_vlan_add() argument
1256 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); in gswip_port_vlan_add()
1257 struct gswip_priv *priv = ds->priv; in gswip_port_vlan_add()
1258 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; in gswip_port_vlan_add()
1259 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; in gswip_port_vlan_add()
1262 err = gswip_port_vlan_prepare(ds, port, vlan, extack); in gswip_port_vlan_add()
1266 /* We have to receive all packets on the CPU port and should not in gswip_port_vlan_add()
1271 if (dsa_is_cpu_port(ds, port)) in gswip_port_vlan_add()
1274 return gswip_vlan_add_aware(priv, bridge, port, vlan->vid, in gswip_port_vlan_add()
1278 static int gswip_port_vlan_del(struct dsa_switch *ds, int port, in gswip_port_vlan_del() argument
1281 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); in gswip_port_vlan_del()
1282 struct gswip_priv *priv = ds->priv; in gswip_port_vlan_del()
1283 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; in gswip_port_vlan_del()
1285 /* We have to receive all packets on the CPU port and should not in gswip_port_vlan_del()
1290 if (dsa_is_cpu_port(ds, port)) in gswip_port_vlan_del()
1293 return gswip_vlan_remove(priv, bridge, port, vlan->vid, pvid, true); in gswip_port_vlan_del()
1296 static void gswip_port_fast_age(struct dsa_switch *ds, int port) in gswip_port_fast_age() argument
1298 struct gswip_priv *priv = ds->priv; in gswip_port_fast_age()
1309 dev_err(priv->dev, "failed to read mac bridge: %d\n", in gswip_port_fast_age()
1320 if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) != port) in gswip_port_fast_age()
1326 dev_err(priv->dev, "failed to write mac bridge: %d\n", in gswip_port_fast_age()
1333 static void gswip_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) in gswip_port_stp_state_set() argument
1335 struct gswip_priv *priv = ds->priv; in gswip_port_stp_state_set()
1341 GSWIP_SDMA_PCTRLp(port)); in gswip_port_stp_state_set()
1354 dev_err(priv->dev, "invalid STP state: %d\n", state); in gswip_port_stp_state_set()
1359 GSWIP_SDMA_PCTRLp(port)); in gswip_port_stp_state_set()
1361 GSWIP_PCE_PCTRL_0p(port)); in gswip_port_stp_state_set()
1364 static int gswip_port_fdb(struct dsa_switch *ds, int port, in gswip_port_fdb() argument
1367 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); in gswip_port_fdb()
1368 struct gswip_priv *priv = ds->priv; in gswip_port_fdb()
1370 unsigned int max_ports = priv->hw_info->max_ports; in gswip_port_fdb()
1371 int fid = -1; in gswip_port_fdb()
1376 return -EINVAL; in gswip_port_fdb()
1378 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { in gswip_port_fdb()
1379 if (priv->vlans[i].bridge == bridge) { in gswip_port_fdb()
1380 fid = priv->vlans[i].fid; in gswip_port_fdb()
1385 if (fid == -1) { in gswip_port_fdb()
1386 dev_err(priv->dev, "Port not part of a bridge\n"); in gswip_port_fdb()
1387 return -EINVAL; in gswip_port_fdb()
1396 mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */ in gswip_port_fdb()
1402 dev_err(priv->dev, "failed to write mac bridge: %d\n", err); in gswip_port_fdb()
1407 static int gswip_port_fdb_add(struct dsa_switch *ds, int port, in gswip_port_fdb_add() argument
1411 return gswip_port_fdb(ds, port, addr, vid, true); in gswip_port_fdb_add()
1414 static int gswip_port_fdb_del(struct dsa_switch *ds, int port, in gswip_port_fdb_del() argument
1418 return gswip_port_fdb(ds, port, addr, vid, false); in gswip_port_fdb_del()
1421 static int gswip_port_fdb_dump(struct dsa_switch *ds, int port, in gswip_port_fdb_dump() argument
1424 struct gswip_priv *priv = ds->priv; in gswip_port_fdb_dump()
1436 dev_err(priv->dev, in gswip_port_fdb_dump()
1452 if (mac_bridge.val[0] & BIT(port)) { in gswip_port_fdb_dump()
1458 if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) == port) { in gswip_port_fdb_dump()
1468 static int gswip_port_max_mtu(struct dsa_switch *ds, int port) in gswip_port_max_mtu() argument
1471 return GSWIP_MAX_PACKET_LENGTH - VLAN_ETH_HLEN - ETH_FCS_LEN; in gswip_port_max_mtu()
1474 static int gswip_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) in gswip_port_change_mtu() argument
1476 struct gswip_priv *priv = ds->priv; in gswip_port_change_mtu()
1477 int cpu_port = priv->hw_info->cpu_port; in gswip_port_change_mtu()
1479 /* CPU port always has maximum mtu of user ports, so use it to set in gswip_port_change_mtu()
1482 if (port == cpu_port) { in gswip_port_change_mtu()
1488 /* Enable MLEN for ports with non-standard MTUs, including the special in gswip_port_change_mtu()
1489 * header on the CPU port added above. in gswip_port_change_mtu()
1493 GSWIP_MAC_CTRL_2p(port)); in gswip_port_change_mtu()
1496 GSWIP_MAC_CTRL_2p(port)); in gswip_port_change_mtu()
1501 static void gswip_xrx200_phylink_get_caps(struct dsa_switch *ds, int port, in gswip_xrx200_phylink_get_caps() argument
1504 switch (port) { in gswip_xrx200_phylink_get_caps()
1507 phy_interface_set_rgmii(config->supported_interfaces); in gswip_xrx200_phylink_get_caps()
1509 config->supported_interfaces); in gswip_xrx200_phylink_get_caps()
1511 config->supported_interfaces); in gswip_xrx200_phylink_get_caps()
1513 config->supported_interfaces); in gswip_xrx200_phylink_get_caps()
1520 config->supported_interfaces); in gswip_xrx200_phylink_get_caps()
1524 phy_interface_set_rgmii(config->supported_interfaces); in gswip_xrx200_phylink_get_caps()
1526 config->supported_interfaces); in gswip_xrx200_phylink_get_caps()
1530 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | in gswip_xrx200_phylink_get_caps()
1534 static void gswip_xrx300_phylink_get_caps(struct dsa_switch *ds, int port, in gswip_xrx300_phylink_get_caps() argument
1537 switch (port) { in gswip_xrx300_phylink_get_caps()
1539 phy_interface_set_rgmii(config->supported_interfaces); in gswip_xrx300_phylink_get_caps()
1541 config->supported_interfaces); in gswip_xrx300_phylink_get_caps()
1543 config->supported_interfaces); in gswip_xrx300_phylink_get_caps()
1551 config->supported_interfaces); in gswip_xrx300_phylink_get_caps()
1555 phy_interface_set_rgmii(config->supported_interfaces); in gswip_xrx300_phylink_get_caps()
1557 config->supported_interfaces); in gswip_xrx300_phylink_get_caps()
1559 config->supported_interfaces); in gswip_xrx300_phylink_get_caps()
1563 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | in gswip_xrx300_phylink_get_caps()
1567 static void gswip_port_set_link(struct gswip_priv *priv, int port, bool link) in gswip_port_set_link() argument
1577 GSWIP_MDIO_PHYp(port)); in gswip_port_set_link()
1580 static void gswip_port_set_speed(struct gswip_priv *priv, int port, int speed, in gswip_port_set_speed() argument
1618 GSWIP_MDIO_PHYp(port)); in gswip_port_set_speed()
1619 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_RATE_MASK, mii_cfg, port); in gswip_port_set_speed()
1621 GSWIP_MAC_CTRL_0p(port)); in gswip_port_set_speed()
1624 static void gswip_port_set_duplex(struct gswip_priv *priv, int port, int duplex) in gswip_port_set_duplex() argument
1637 GSWIP_MAC_CTRL_0p(port)); in gswip_port_set_duplex()
1639 GSWIP_MDIO_PHYp(port)); in gswip_port_set_duplex()
1642 static void gswip_port_set_pause(struct gswip_priv *priv, int port, in gswip_port_set_pause() argument
1666 mac_ctrl_0, GSWIP_MAC_CTRL_0p(port)); in gswip_port_set_pause()
1670 mdio_phy, GSWIP_MDIO_PHYp(port)); in gswip_port_set_pause()
1673 static void gswip_phylink_mac_config(struct dsa_switch *ds, int port, in gswip_phylink_mac_config() argument
1674 unsigned int mode, in gswip_phylink_mac_config() argument
1677 struct gswip_priv *priv = ds->priv; in gswip_phylink_mac_config()
1682 switch (state->interface) { in gswip_phylink_mac_config()
1703 dev_err(ds->dev, in gswip_phylink_mac_config()
1704 "Unsupported interface: %d\n", state->interface); in gswip_phylink_mac_config()
1711 miicfg, port); in gswip_phylink_mac_config()
1713 switch (state->interface) { in gswip_phylink_mac_config()
1716 GSWIP_MII_PCDU_RXDLY_MASK, 0, port); in gswip_phylink_mac_config()
1719 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_RXDLY_MASK, 0, port); in gswip_phylink_mac_config()
1722 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK, 0, port); in gswip_phylink_mac_config()
1729 static void gswip_phylink_mac_link_down(struct dsa_switch *ds, int port, in gswip_phylink_mac_link_down() argument
1730 unsigned int mode, in gswip_phylink_mac_link_down() argument
1733 struct gswip_priv *priv = ds->priv; in gswip_phylink_mac_link_down()
1735 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, port); in gswip_phylink_mac_link_down()
1737 if (!dsa_is_cpu_port(ds, port)) in gswip_phylink_mac_link_down()
1738 gswip_port_set_link(priv, port, false); in gswip_phylink_mac_link_down()
1741 static void gswip_phylink_mac_link_up(struct dsa_switch *ds, int port, in gswip_phylink_mac_link_up() argument
1742 unsigned int mode, in gswip_phylink_mac_link_up() argument
1748 struct gswip_priv *priv = ds->priv; in gswip_phylink_mac_link_up()
1750 if (!dsa_is_cpu_port(ds, port)) { in gswip_phylink_mac_link_up()
1751 gswip_port_set_link(priv, port, true); in gswip_phylink_mac_link_up()
1752 gswip_port_set_speed(priv, port, speed, interface); in gswip_phylink_mac_link_up()
1753 gswip_port_set_duplex(priv, port, duplex); in gswip_phylink_mac_link_up()
1754 gswip_port_set_pause(priv, port, tx_pause, rx_pause); in gswip_phylink_mac_link_up()
1757 gswip_mii_mask_cfg(priv, 0, GSWIP_MII_CFG_EN, port); in gswip_phylink_mac_link_up()
1760 static void gswip_get_strings(struct dsa_switch *ds, int port, u32 stringset, in gswip_get_strings() argument
1787 dev_err(priv->dev, "timeout while reading table: %u, index: %u", in gswip_bcm_ram_entry_read()
1798 static void gswip_get_ethtool_stats(struct dsa_switch *ds, int port, in gswip_get_ethtool_stats() argument
1801 struct gswip_priv *priv = ds->priv; in gswip_get_ethtool_stats()
1809 data[i] = gswip_bcm_ram_entry_read(priv, port, in gswip_get_ethtool_stats()
1810 rmon_cnt->offset); in gswip_get_ethtool_stats()
1811 if (rmon_cnt->size == 2) { in gswip_get_ethtool_stats()
1812 high = gswip_bcm_ram_entry_read(priv, port, in gswip_get_ethtool_stats()
1813 rmon_cnt->offset + 1); in gswip_get_ethtool_stats()
1819 static int gswip_get_sset_count(struct dsa_switch *ds, int port, int sset) in gswip_get_sset_count() argument
1895 { .compatible = "lantiq,xrx200-gphy-fw", .data = NULL },
1896 { .compatible = "lantiq,xrx200a1x-gphy-fw", .data = &xrx200a1x_gphy_data },
1897 { .compatible = "lantiq,xrx200a2x-gphy-fw", .data = &xrx200a2x_gphy_data },
1898 { .compatible = "lantiq,xrx300-gphy-fw", .data = &xrx300_gphy_data },
1899 { .compatible = "lantiq,xrx330-gphy-fw", .data = &xrx300_gphy_data },
1905 struct device *dev = priv->dev; in gswip_gphy_fw_load()
1913 ret = clk_prepare_enable(gphy_fw->clk_gate); in gswip_gphy_fw_load()
1917 reset_control_assert(gphy_fw->reset); in gswip_gphy_fw_load()
1925 ret = request_firmware(&fw, gphy_fw->fw_name, dev); in gswip_gphy_fw_load()
1928 gphy_fw->fw_name, ret); in gswip_gphy_fw_load()
1935 size = fw->size + XRX200_GPHY_FW_ALIGN; in gswip_gphy_fw_load()
1941 memcpy(fw_addr, fw->data, fw->size); in gswip_gphy_fw_load()
1945 return -ENOMEM; in gswip_gphy_fw_load()
1950 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, dev_addr); in gswip_gphy_fw_load()
1954 reset_control_deassert(gphy_fw->reset); in gswip_gphy_fw_load()
1963 struct device *dev = priv->dev; in gswip_gphy_fw_probe()
1970 gphy_fw->clk_gate = devm_clk_get(dev, gphyname); in gswip_gphy_fw_probe()
1971 if (IS_ERR(gphy_fw->clk_gate)) { in gswip_gphy_fw_probe()
1973 return PTR_ERR(gphy_fw->clk_gate); in gswip_gphy_fw_probe()
1976 ret = of_property_read_u32(gphy_fw_np, "reg", &gphy_fw->fw_addr_offset); in gswip_gphy_fw_probe()
1980 ret = of_property_read_u32(gphy_fw_np, "lantiq,gphy-mode", &gphy_mode); in gswip_gphy_fw_probe()
1981 /* Default to GE mode */ in gswip_gphy_fw_probe()
1987 gphy_fw->fw_name = priv->gphy_fw_name_cfg->fe_firmware_name; in gswip_gphy_fw_probe()
1990 gphy_fw->fw_name = priv->gphy_fw_name_cfg->ge_firmware_name; in gswip_gphy_fw_probe()
1993 dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode); in gswip_gphy_fw_probe()
1994 return -EINVAL; in gswip_gphy_fw_probe()
1997 gphy_fw->reset = of_reset_control_array_get_exclusive(gphy_fw_np); in gswip_gphy_fw_probe()
1998 if (IS_ERR(gphy_fw->reset)) in gswip_gphy_fw_probe()
1999 return dev_err_probe(dev, PTR_ERR(gphy_fw->reset), in gswip_gphy_fw_probe()
2011 if (!gphy_fw->fw_name) in gswip_gphy_fw_remove()
2014 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, 0); in gswip_gphy_fw_remove()
2016 dev_err(priv->dev, "can not reset GPHY FW pointer"); in gswip_gphy_fw_remove()
2018 clk_disable_unprepare(gphy_fw->clk_gate); in gswip_gphy_fw_remove()
2020 reset_control_put(gphy_fw->reset); in gswip_gphy_fw_remove()
2026 struct device *dev = priv->dev; in gswip_gphy_fw_list()
2036 if (of_device_is_compatible(gphy_fw_list_np, "lantiq,xrx200-gphy-fw")) { in gswip_gphy_fw_list()
2039 priv->gphy_fw_name_cfg = &xrx200a1x_gphy_data; in gswip_gphy_fw_list()
2042 priv->gphy_fw_name_cfg = &xrx200a2x_gphy_data; in gswip_gphy_fw_list()
2046 return -ENOENT; in gswip_gphy_fw_list()
2051 if (match && match->data) in gswip_gphy_fw_list()
2052 priv->gphy_fw_name_cfg = match->data; in gswip_gphy_fw_list()
2054 if (!priv->gphy_fw_name_cfg) { in gswip_gphy_fw_list()
2056 return -ENOENT; in gswip_gphy_fw_list()
2059 priv->num_gphy_fw = of_get_available_child_count(gphy_fw_list_np); in gswip_gphy_fw_list()
2060 if (!priv->num_gphy_fw) in gswip_gphy_fw_list()
2061 return -ENOENT; in gswip_gphy_fw_list()
2063 priv->rcu_regmap = syscon_regmap_lookup_by_phandle(gphy_fw_list_np, in gswip_gphy_fw_list()
2065 if (IS_ERR(priv->rcu_regmap)) in gswip_gphy_fw_list()
2066 return PTR_ERR(priv->rcu_regmap); in gswip_gphy_fw_list()
2068 priv->gphy_fw = devm_kmalloc_array(dev, priv->num_gphy_fw, in gswip_gphy_fw_list()
2069 sizeof(*priv->gphy_fw), in gswip_gphy_fw_list()
2071 if (!priv->gphy_fw) in gswip_gphy_fw_list()
2072 return -ENOMEM; in gswip_gphy_fw_list()
2075 err = gswip_gphy_fw_probe(priv, &priv->gphy_fw[i], in gswip_gphy_fw_list()
2086 * taken out of reset. For the SoC-internal GPHY variant there in gswip_gphy_fw_list()
2097 for (i = 0; i < priv->num_gphy_fw; i++) in gswip_gphy_fw_list()
2098 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); in gswip_gphy_fw_list()
2105 struct device *dev = &pdev->dev; in gswip_probe()
2113 return -ENOMEM; in gswip_probe()
2115 priv->gswip = devm_platform_ioremap_resource(pdev, 0); in gswip_probe()
2116 if (IS_ERR(priv->gswip)) in gswip_probe()
2117 return PTR_ERR(priv->gswip); in gswip_probe()
2119 priv->mdio = devm_platform_ioremap_resource(pdev, 1); in gswip_probe()
2120 if (IS_ERR(priv->mdio)) in gswip_probe()
2121 return PTR_ERR(priv->mdio); in gswip_probe()
2123 priv->mii = devm_platform_ioremap_resource(pdev, 2); in gswip_probe()
2124 if (IS_ERR(priv->mii)) in gswip_probe()
2125 return PTR_ERR(priv->mii); in gswip_probe()
2127 priv->hw_info = of_device_get_match_data(dev); in gswip_probe()
2128 if (!priv->hw_info) in gswip_probe()
2129 return -EINVAL; in gswip_probe()
2131 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); in gswip_probe()
2132 if (!priv->ds) in gswip_probe()
2133 return -ENOMEM; in gswip_probe()
2135 priv->ds->dev = dev; in gswip_probe()
2136 priv->ds->num_ports = priv->hw_info->max_ports; in gswip_probe()
2137 priv->ds->priv = priv; in gswip_probe()
2138 priv->ds->ops = priv->hw_info->ops; in gswip_probe()
2139 priv->dev = dev; in gswip_probe()
2140 mutex_init(&priv->pce_table_lock); in gswip_probe()
2143 np = dev->of_node; in gswip_probe()
2147 if (!of_device_is_compatible(np, "lantiq,xrx200-gswip")) in gswip_probe()
2148 return -EINVAL; in gswip_probe()
2152 if (!of_device_is_compatible(np, "lantiq,xrx300-gswip") && in gswip_probe()
2153 !of_device_is_compatible(np, "lantiq,xrx330-gswip")) in gswip_probe()
2154 return -EINVAL; in gswip_probe()
2158 return -ENOENT; in gswip_probe()
2162 gphy_fw_np = of_get_compatible_child(dev->of_node, "lantiq,gphy-fw"); in gswip_probe()
2179 err = dsa_register_switch(priv->ds); in gswip_probe()
2184 if (!dsa_is_cpu_port(priv->ds, priv->hw_info->cpu_port)) { in gswip_probe()
2185 dev_err(dev, "wrong CPU port defined, HW only supports port: %i", in gswip_probe()
2186 priv->hw_info->cpu_port); in gswip_probe()
2187 err = -EINVAL; in gswip_probe()
2200 dsa_unregister_switch(priv->ds); in gswip_probe()
2202 for (i = 0; i < priv->num_gphy_fw; i++) in gswip_probe()
2203 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); in gswip_probe()
2218 dsa_unregister_switch(priv->ds); in gswip_remove()
2220 for (i = 0; i < priv->num_gphy_fw; i++) in gswip_remove()
2221 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); in gswip_remove()
2231 dsa_switch_shutdown(priv->ds); in gswip_shutdown()
2249 { .compatible = "lantiq,xrx200-gswip", .data = &gswip_xrx200 },
2250 { .compatible = "lantiq,xrx300-gswip", .data = &gswip_xrx300 },
2251 { .compatible = "lantiq,xrx330-gswip", .data = &gswip_xrx300 },
2274 MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>");