dsa/hirschmann/hellcreek.h

1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
6  * Copyright (C) 2019-2021 Linutronix GmbH
20 #include <linux/platform_data/hirschmann-hellcreek.h>
27  *  - 0: CPU
28  *  - 1: Tunnel
29  *  - 2: TSN front port 1
30  *  - 3: TSN front port 2
31  *  - ...
33 #define CPU_PORT			0
36 #define HELLCREEK_VLAN_NO_MEMBER	0x0
37 #define HELLCREEK_VLAN_UNTAGGED_MEMBER	0x1
38 #define HELLCREEK_VLAN_TAGGED_MEMBER	0x3
43 #define HR_MODID_C			(0 * 2)
44 #define HR_REL_L_C			(1 * 2)
45 #define HR_REL_H_C			(2 * 2)
46 #define HR_BLD_L_C			(3 * 2)
47 #define HR_BLD_H_C			(4 * 2)
48 #define HR_CTRL_C			(5 * 2)
51 #define HR_CTRL_C_ENABLE		BIT(0)
53 #define HR_PSEL				(0xa6 * 2)
56 #define HR_PSEL_PRTCWSEL_SHIFT		0
57 #define HR_PSEL_PRTCWSEL_MASK		GENMASK(2, 0)
59 #define HR_PTCFG			(0xa7 * 2)
68 #define HR_PTCFG_BLOCKED		BIT(2)
70 #define HR_PTCFG_ADMIN_EN		BIT(0)
72 #define HR_PRTCCFG			(0xa8 * 2)
73 #define HR_PRTCCFG_PCP_TC_MAP_SHIFT	0
74 #define HR_PRTCCFG_PCP_TC_MAP_MASK	GENMASK(2, 0)
76 #define HR_PTPRTCCFG			(0xa9 * 2)
79 #define HR_PTPRTCCFG_MAXSDU_SHIFT	0
80 #define HR_PTPRTCCFG_MAXSDU_MASK	GENMASK(10, 0)
82 #define HR_CSEL				(0x8d * 2)
83 #define HR_CSEL_SHIFT			0
84 #define HR_CSEL_MASK			GENMASK(7, 0)
85 #define HR_CRDL				(0x8e * 2)
86 #define HR_CRDH				(0x8f * 2)
88 #define HR_SWTRC_CFG			(0x90 * 2)
89 #define HR_SWTRC0			(0x91 * 2)
90 #define HR_SWTRC1			(0x92 * 2)
91 #define HR_PFREE			(0x93 * 2)
92 #define HR_MFREE			(0x94 * 2)
94 #define HR_FDBAGE			(0x97 * 2)
95 #define HR_FDBMAX			(0x98 * 2)
96 #define HR_FDBRDL			(0x99 * 2)
97 #define HR_FDBRDM			(0x9a * 2)
98 #define HR_FDBRDH			(0x9b * 2)
100 #define HR_FDBMDRD			(0x9c * 2)
101 #define HR_FDBMDRD_PORTMASK_SHIFT	0
102 #define HR_FDBMDRD_PORTMASK_MASK	GENMASK(3, 0)
112 #define HR_FDBWDL			(0x9d * 2)
113 #define HR_FDBWDM			(0x9e * 2)
114 #define HR_FDBWDH			(0x9f * 2)
115 #define HR_FDBWRM0			(0xa0 * 2)
116 #define HR_FDBWRM0_PORTMASK_SHIFT	0
117 #define HR_FDBWRM0_PORTMASK_MASK	GENMASK(3, 0)
123 #define HR_FDBWRM1			(0xa1 * 2)
125 #define HR_FDBWRCMD			(0xa2 * 2)
128 #define HR_SWCFG			(0xa3 * 2)
132 #define HR_SWCFG_LAS_OFF		(0x00)
133 #define HR_SWCFG_LAS_ON			(0x01)
134 #define HR_SWCFG_LAS_STATIC		(0x10)
141 #define HR_SWSTAT			(0xa4 * 2)
143 #define HR_SWSTAT_BUSY			BIT(0)
145 #define HR_SWCMD			(0xa5 * 2)
146 #define HW_SWCMD_FLUSH			BIT(0)
148 #define HR_VIDCFG			(0xaa * 2)
149 #define HR_VIDCFG_VID_SHIFT		0
150 #define HR_VIDCFG_VID_MASK		GENMASK(11, 0)
153 #define HR_VIDMBRCFG			(0xab * 2)
154 #define HR_VIDMBRCFG_P0MBR_SHIFT	0
155 #define HR_VIDMBRCFG_P0MBR_MASK		GENMASK(1, 0)
156 #define HR_VIDMBRCFG_P1MBR_SHIFT	2
157 #define HR_VIDMBRCFG_P1MBR_MASK		GENMASK(3, 2)
163 #define HR_FEABITS0			(0xac * 2)
171 #define TR_QTRACK			(0xb1 * 2)
172 #define TR_TGDVER			(0xb3 * 2)
173 #define TR_TGDVER_REV_MIN_MASK		GENMASK(7, 0)
174 #define TR_TGDVER_REV_MIN_SHIFT		0
177 #define TR_TGDSEL			(0xb4 * 2)
178 #define TR_TGDSEL_TDGSEL_MASK		GENMASK(1, 0)
179 #define TR_TGDSEL_TDGSEL_SHIFT		0
180 #define TR_TGDCTRL			(0xb5 * 2)
181 #define TR_TGDCTRL_GATE_EN		BIT(0)
186 #define TR_TGDSTAT0			(0xb6 * 2)
187 #define TR_TGDSTAT1			(0xb7 * 2)
188 #define TR_ESTWRL			(0xb8 * 2)
189 #define TR_ESTWRH			(0xb9 * 2)
190 #define TR_ESTCMD			(0xba * 2)
191 #define TR_ESTCMD_ESTSEC_MASK		GENMASK(2, 0)
192 #define TR_ESTCMD_ESTSEC_SHIFT		0
195 #define TR_EETWRL			(0xbb * 2)
196 #define TR_EETWRH			(0xbc * 2)
197 #define TR_EETCMD			(0xbd * 2)
198 #define TR_EETCMD_EETSEC_MASK		GEMASK(2, 0)
199 #define TR_EETCMD_EETSEC_SHIFT		0
201 #define TR_CTWRL			(0xbe * 2)
202 #define TR_CTWRH			(0xbf * 2)
203 #define TR_LCNSL			(0xc1 * 2)
204 #define TR_LCNSH			(0xc2 * 2)
205 #define TR_LCS				(0xc3 * 2)
206 #define TR_GCLDAT			(0xc4 * 2)
207 #define TR_GCLDAT_GCLWRGATES_MASK	GENMASK(7, 0)
208 #define TR_GCLDAT_GCLWRGATES_SHIFT	0
211 #define TR_GCLTIL			(0xc5 * 2)
212 #define TR_GCLTIH			(0xc6 * 2)
213 #define TR_GCLCMD			(0xc7 * 2)
214 #define TR_GCLCMD_GCLWRADR_MASK		GENMASK(7, 0)
215 #define TR_GCLCMD_GCLWRADR_SHIFT	0
255 	/* Per-port timestamping resources */
258 	/* Per-port Qbv schedule information */
303  * cannot be armed directly to $base_time - 8 + X, because for large deltas the
306 #define HELLCREEK_SCHEDULE_PERIOD	(2 * HZ)