Lines Matching +full:nand +full:- +full:ecc +full:- +full:placement
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright © 2004-2008 Simtec Electronics
7 * Samsung S3C2410/S3C2440/S3C2412 NAND driver
10 #define pr_fmt(fmt) "nand-s3c2410: " fmt
34 #include <linux/platform_data/mtd-nand-s3c2410.h>
71 /* new oob placement block for use with hardware ecc generation
77 return -ERANGE; in s3c2410_ooblayout_ecc()
79 oobregion->offset = 0; in s3c2410_ooblayout_ecc()
80 oobregion->length = 3; in s3c2410_ooblayout_ecc()
89 return -ERANGE; in s3c2410_ooblayout_free()
91 oobregion->offset = 8; in s3c2410_ooblayout_free()
92 oobregion->length = 8; in s3c2410_ooblayout_free()
98 .ecc = s3c2410_ooblayout_ecc,
107 * struct s3c2410_nand_mtd - driver MTD structure
108 * @chip: The NAND chip information.
109 * @set: The platform information supplied for this set of NAND chips.
130 /* overview of the s3c2410 nand state */
133 * struct s3c2410_nand_info - NAND controller state.
140 * @sel_reg: Pointer to the register controlling the NAND selection.
141 * @sel_bit: The bit in @sel_reg to select the NAND chip.
194 return s3c2410_nand_mtd_toours(mtd)->info; in s3c2410_nand_mtd_toinfo()
204 return dev_get_platdata(&dev->dev); in to_nand_plat()
217 * s3c2410_nand_clk_set_state - Enable, disable or suspend NAND clock.
227 if (info->clk_state == CLOCK_ENABLE) { in s3c2410_nand_clk_set_state()
229 clk_disable_unprepare(info->clk); in s3c2410_nand_clk_set_state()
232 clk_prepare_enable(info->clk); in s3c2410_nand_clk_set_state()
235 info->clk_state = new_state; in s3c2410_nand_clk_set_state()
243 * s3c_nand_calc_rate - calculate timing data.
261 return -1; in s3c_nand_calc_rate()
275 * s3c2410_nand_setrate - setup controller timing information.
284 struct s3c2410_platform_nand *plat = info->platform; in s3c2410_nand_setrate()
285 int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4; in s3c2410_nand_setrate()
287 unsigned long clkrate = clk_get_rate(info->clk); in s3c2410_nand_setrate()
293 info->clk_rate = clkrate; in s3c2410_nand_setrate()
297 tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max); in s3c2410_nand_setrate()
298 twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8); in s3c2410_nand_setrate()
299 twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8); in s3c2410_nand_setrate()
308 dev_err(info->device, "cannot get suitable timings\n"); in s3c2410_nand_setrate()
309 return -EINVAL; in s3c2410_nand_setrate()
312 dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n", in s3c2410_nand_setrate()
316 switch (info->cpu_type) { in s3c2410_nand_setrate()
322 set |= S3C2410_NFCONF_TACLS(tacls - 1); in s3c2410_nand_setrate()
323 set |= S3C2410_NFCONF_TWRPH0(twrph0 - 1); in s3c2410_nand_setrate()
324 set |= S3C2410_NFCONF_TWRPH1(twrph1 - 1); in s3c2410_nand_setrate()
329 mask = (S3C2440_NFCONF_TACLS(tacls_max - 1) | in s3c2410_nand_setrate()
333 set = S3C2440_NFCONF_TACLS(tacls - 1); in s3c2410_nand_setrate()
334 set |= S3C2440_NFCONF_TWRPH0(twrph0 - 1); in s3c2410_nand_setrate()
335 set |= S3C2440_NFCONF_TWRPH1(twrph1 - 1); in s3c2410_nand_setrate()
344 cfg = readl(info->regs + S3C2410_NFCONF); in s3c2410_nand_setrate()
347 writel(cfg, info->regs + S3C2410_NFCONF); in s3c2410_nand_setrate()
351 dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg); in s3c2410_nand_setrate()
357 * s3c2410_nand_inithw - basic hardware initialisation
371 switch (info->cpu_type) { in s3c2410_nand_inithw()
378 /* enable the controller and de-assert nFCE */ in s3c2410_nand_inithw()
380 writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT); in s3c2410_nand_inithw()
387 * s3c2410_nand_select_chip - select the given nand chip
388 * @this: NAND chip object.
393 * chip can be de-selected.
406 info = nmtd->info; in s3c2410_nand_select_chip()
408 if (chip != -1) in s3c2410_nand_select_chip()
411 cur = readl(info->sel_reg); in s3c2410_nand_select_chip()
413 if (chip == -1) { in s3c2410_nand_select_chip()
414 cur |= info->sel_bit; in s3c2410_nand_select_chip()
416 if (nmtd->set != NULL && chip > nmtd->set->nr_chips) { in s3c2410_nand_select_chip()
417 dev_err(info->device, "invalid chip %d\n", chip); in s3c2410_nand_select_chip()
421 if (info->platform != NULL) { in s3c2410_nand_select_chip()
422 if (info->platform->select_chip != NULL) in s3c2410_nand_select_chip()
423 (info->platform->select_chip) (nmtd->set, chip); in s3c2410_nand_select_chip()
426 cur &= ~info->sel_bit; in s3c2410_nand_select_chip()
429 writel(cur, info->sel_reg); in s3c2410_nand_select_chip()
431 if (chip == -1) in s3c2410_nand_select_chip()
450 writeb(cmd, info->regs + S3C2410_NFCMD); in s3c2410_nand_hwcontrol()
452 writeb(cmd, info->regs + S3C2410_NFADDR); in s3c2410_nand_hwcontrol()
467 writeb(cmd, info->regs + S3C2440_NFCMD); in s3c2440_nand_hwcontrol()
469 writeb(cmd, info->regs + S3C2440_NFADDR); in s3c2440_nand_hwcontrol()
474 * returns 0 if the nand is busy, 1 if it is ready
481 return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY; in s3c2410_nand_devready()
488 return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY; in s3c2440_nand_devready()
495 return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY; in s3c2412_nand_devready()
498 /* ECC handling functions */
519 return 0; /* ECC is ok */ in s3c2410_nand_correct_data()
521 /* sometimes people do not think about using the ECC, so check in s3c2410_nand_correct_data()
522 * to see if we have an 0xff,0xff,0xff read ECC and then ignore in s3c2410_nand_correct_data()
523 * the error, on the assumption that this is an un-eccd page. in s3c2410_nand_correct_data()
526 && info->platform->ignore_unset_ecc) in s3c2410_nand_correct_data()
529 /* Can we correct this ECC (ie, one row and column change). in s3c2410_nand_correct_data()
553 dev_dbg(info->device, "correcting error bit %d, byte %d\n", in s3c2410_nand_correct_data()
560 /* if there is only one bit difference in the ECC, then in s3c2410_nand_correct_data()
562 * means the error is most probably in the ECC itself */ in s3c2410_nand_correct_data()
568 if ((diff0 & (diff0 - 1)) == 0) in s3c2410_nand_correct_data()
571 return -1; in s3c2410_nand_correct_data()
574 /* ECC functions
576 * These allow the s3c2410 and s3c2440 to use the controller's ECC
577 * generator block to ECC the data as it passes through]
586 ctrl = readl(info->regs + S3C2410_NFCONF); in s3c2410_nand_enable_hwecc()
588 writel(ctrl, info->regs + S3C2410_NFCONF); in s3c2410_nand_enable_hwecc()
597 ctrl = readl(info->regs + S3C2440_NFCONT); in s3c2412_nand_enable_hwecc()
599 info->regs + S3C2440_NFCONT); in s3c2412_nand_enable_hwecc()
608 ctrl = readl(info->regs + S3C2440_NFCONT); in s3c2440_nand_enable_hwecc()
609 writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT); in s3c2440_nand_enable_hwecc()
618 ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0); in s3c2410_nand_calculate_ecc()
619 ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1); in s3c2410_nand_calculate_ecc()
620 ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2); in s3c2410_nand_calculate_ecc()
622 pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code); in s3c2410_nand_calculate_ecc()
632 unsigned long ecc = readl(info->regs + S3C2412_NFMECC0); in s3c2412_nand_calculate_ecc() local
634 ecc_code[0] = ecc; in s3c2412_nand_calculate_ecc()
635 ecc_code[1] = ecc >> 8; in s3c2412_nand_calculate_ecc()
636 ecc_code[2] = ecc >> 16; in s3c2412_nand_calculate_ecc()
638 pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code); in s3c2412_nand_calculate_ecc()
648 unsigned long ecc = readl(info->regs + S3C2440_NFMECC0); in s3c2440_nand_calculate_ecc() local
650 ecc_code[0] = ecc; in s3c2440_nand_calculate_ecc()
651 ecc_code[1] = ecc >> 8; in s3c2440_nand_calculate_ecc()
652 ecc_code[2] = ecc >> 16; in s3c2440_nand_calculate_ecc()
654 pr_debug("%s: returning ecc %06lx\n", __func__, ecc & 0xffffff); in s3c2440_nand_calculate_ecc()
659 /* over-ride the standard functions for a little more speed. We can
665 readsb(this->legacy.IO_ADDR_R, buf, len); in s3c2410_nand_read_buf()
673 readsl(info->regs + S3C2440_NFDATA, buf, len >> 2); in s3c2440_nand_read_buf()
679 for (; len & 3; len--) in s3c2440_nand_read_buf()
680 *buf++ = readb(info->regs + S3C2440_NFDATA); in s3c2440_nand_read_buf()
687 writesb(this->legacy.IO_ADDR_W, buf, len); in s3c2410_nand_write_buf()
696 writesl(info->regs + S3C2440_NFDATA, buf, len >> 2); in s3c2440_nand_write_buf()
702 for (; len & 3; len--, buf++) in s3c2440_nand_write_buf()
703 writeb(*buf, info->regs + S3C2440_NFDATA); in s3c2440_nand_write_buf()
720 if (info->mtds != NULL) { in s3c24xx_nand_remove()
721 struct s3c2410_nand_mtd *ptr = info->mtds; in s3c24xx_nand_remove()
724 for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) { in s3c24xx_nand_remove()
726 WARN_ON(mtd_device_unregister(nand_to_mtd(&ptr->chip))); in s3c24xx_nand_remove()
727 nand_cleanup(&ptr->chip); in s3c24xx_nand_remove()
733 if (!IS_ERR(info->clk)) in s3c24xx_nand_remove()
742 struct mtd_info *mtdinfo = nand_to_mtd(&mtd->chip); in s3c2410_nand_add_partition()
744 mtdinfo->name = set->name; in s3c2410_nand_add_partition()
746 return mtd_device_register(mtdinfo, set->partitions, in s3c2410_nand_add_partition()
747 set->nr_partitions); in s3c2410_nand_add_partition()
750 return -ENODEV; in s3c2410_nand_add_partition()
758 struct s3c2410_platform_nand *pdata = info->platform; in s3c2410_nand_setup_interface()
764 return -ENOTSUPP; in s3c2410_nand_setup_interface()
766 tacls = timings->tCLS_min - timings->tWP_min; in s3c2410_nand_setup_interface()
770 pdata->tacls = DIV_ROUND_UP(tacls, 1000); in s3c2410_nand_setup_interface()
771 pdata->twrph0 = DIV_ROUND_UP(timings->tWP_min, 1000); in s3c2410_nand_setup_interface()
772 pdata->twrph1 = DIV_ROUND_UP(timings->tCLH_min, 1000); in s3c2410_nand_setup_interface()
778 * s3c2410_nand_init_chip - initialise a single instance of an chip
779 * @info: The base NAND controller the chip is on.
791 struct device_node *np = info->device->of_node; in s3c2410_nand_init_chip()
792 struct nand_chip *chip = &nmtd->chip; in s3c2410_nand_init_chip()
793 void __iomem *regs = info->regs; in s3c2410_nand_init_chip()
795 nand_set_flash_node(chip, set->of_node); in s3c2410_nand_init_chip()
797 chip->legacy.write_buf = s3c2410_nand_write_buf; in s3c2410_nand_init_chip()
798 chip->legacy.read_buf = s3c2410_nand_read_buf; in s3c2410_nand_init_chip()
799 chip->legacy.select_chip = s3c2410_nand_select_chip; in s3c2410_nand_init_chip()
800 chip->legacy.chip_delay = 50; in s3c2410_nand_init_chip()
802 chip->options = set->options; in s3c2410_nand_init_chip()
803 chip->controller = &info->controller; in s3c2410_nand_init_chip()
807 * auto-detect timings only when booting with a device tree. in s3c2410_nand_init_chip()
810 chip->options |= NAND_KEEP_TIMINGS; in s3c2410_nand_init_chip()
812 switch (info->cpu_type) { in s3c2410_nand_init_chip()
814 chip->legacy.IO_ADDR_W = regs + S3C2410_NFDATA; in s3c2410_nand_init_chip()
815 info->sel_reg = regs + S3C2410_NFCONF; in s3c2410_nand_init_chip()
816 info->sel_bit = S3C2410_NFCONF_nFCE; in s3c2410_nand_init_chip()
817 chip->legacy.cmd_ctrl = s3c2410_nand_hwcontrol; in s3c2410_nand_init_chip()
818 chip->legacy.dev_ready = s3c2410_nand_devready; in s3c2410_nand_init_chip()
822 chip->legacy.IO_ADDR_W = regs + S3C2440_NFDATA; in s3c2410_nand_init_chip()
823 info->sel_reg = regs + S3C2440_NFCONT; in s3c2410_nand_init_chip()
824 info->sel_bit = S3C2440_NFCONT_nFCE; in s3c2410_nand_init_chip()
825 chip->legacy.cmd_ctrl = s3c2440_nand_hwcontrol; in s3c2410_nand_init_chip()
826 chip->legacy.dev_ready = s3c2440_nand_devready; in s3c2410_nand_init_chip()
827 chip->legacy.read_buf = s3c2440_nand_read_buf; in s3c2410_nand_init_chip()
828 chip->legacy.write_buf = s3c2440_nand_write_buf; in s3c2410_nand_init_chip()
832 chip->legacy.IO_ADDR_W = regs + S3C2440_NFDATA; in s3c2410_nand_init_chip()
833 info->sel_reg = regs + S3C2440_NFCONT; in s3c2410_nand_init_chip()
834 info->sel_bit = S3C2412_NFCONT_nFCE0; in s3c2410_nand_init_chip()
835 chip->legacy.cmd_ctrl = s3c2440_nand_hwcontrol; in s3c2410_nand_init_chip()
836 chip->legacy.dev_ready = s3c2412_nand_devready; in s3c2410_nand_init_chip()
839 dev_info(info->device, "System booted from NAND\n"); in s3c2410_nand_init_chip()
844 chip->legacy.IO_ADDR_R = chip->legacy.IO_ADDR_W; in s3c2410_nand_init_chip()
846 nmtd->info = info; in s3c2410_nand_init_chip()
847 nmtd->set = set; in s3c2410_nand_init_chip()
849 chip->ecc.engine_type = info->platform->engine_type; in s3c2410_nand_init_chip()
852 * If you use u-boot BBT creation code, specifying this flag will in s3c2410_nand_init_chip()
853 * let the kernel fish out the BBT from the NAND. in s3c2410_nand_init_chip()
855 if (set->flash_bbt) in s3c2410_nand_init_chip()
856 chip->bbt_options |= NAND_BBT_USE_FLASH; in s3c2410_nand_init_chip()
860 * s3c2410_nand_attach_chip - Init the ECC engine after NAND scan
861 * @chip: The NAND chip
863 * This hook is called by the core after the identification of the NAND chip,
864 * once the relevant per-chip information is up to date.. This call ensure that
867 * The internal state is currently limited to the ECC state information.
874 switch (chip->ecc.engine_type) { in s3c2410_nand_attach_chip()
877 dev_info(info->device, "ECC disabled\n"); in s3c2410_nand_attach_chip()
882 * This driver expects Hamming based ECC when engine_type is set in s3c2410_nand_attach_chip()
883 * to NAND_ECC_ENGINE_TYPE_SOFT. Force ecc.algo to in s3c2410_nand_attach_chip()
887 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; in s3c2410_nand_attach_chip()
888 dev_info(info->device, "soft ECC\n"); in s3c2410_nand_attach_chip()
892 chip->ecc.calculate = s3c2410_nand_calculate_ecc; in s3c2410_nand_attach_chip()
893 chip->ecc.correct = s3c2410_nand_correct_data; in s3c2410_nand_attach_chip()
894 chip->ecc.strength = 1; in s3c2410_nand_attach_chip()
896 switch (info->cpu_type) { in s3c2410_nand_attach_chip()
898 chip->ecc.hwctl = s3c2410_nand_enable_hwecc; in s3c2410_nand_attach_chip()
899 chip->ecc.calculate = s3c2410_nand_calculate_ecc; in s3c2410_nand_attach_chip()
903 chip->ecc.hwctl = s3c2412_nand_enable_hwecc; in s3c2410_nand_attach_chip()
904 chip->ecc.calculate = s3c2412_nand_calculate_ecc; in s3c2410_nand_attach_chip()
908 chip->ecc.hwctl = s3c2440_nand_enable_hwecc; in s3c2410_nand_attach_chip()
909 chip->ecc.calculate = s3c2440_nand_calculate_ecc; in s3c2410_nand_attach_chip()
913 dev_dbg(info->device, "chip %p => page shift %d\n", in s3c2410_nand_attach_chip()
914 chip, chip->page_shift); in s3c2410_nand_attach_chip()
917 * the large or small page nand device */ in s3c2410_nand_attach_chip()
918 if (chip->page_shift > 10) { in s3c2410_nand_attach_chip()
919 chip->ecc.size = 256; in s3c2410_nand_attach_chip()
920 chip->ecc.bytes = 3; in s3c2410_nand_attach_chip()
922 chip->ecc.size = 512; in s3c2410_nand_attach_chip()
923 chip->ecc.bytes = 3; in s3c2410_nand_attach_chip()
928 dev_info(info->device, "hardware ECC\n"); in s3c2410_nand_attach_chip()
932 dev_err(info->device, "invalid ECC mode!\n"); in s3c2410_nand_attach_chip()
933 return -EINVAL; in s3c2410_nand_attach_chip()
936 if (chip->bbt_options & NAND_BBT_USE_FLASH) in s3c2410_nand_attach_chip()
937 chip->options |= NAND_SKIP_BBTSCAN; in s3c2410_nand_attach_chip()
949 .compatible = "samsung,s3c2410-nand",
953 .compatible = "samsung,s3c2412-nand",
956 .compatible = "samsung,s3c2440-nand",
968 struct device_node *np = pdev->dev.of_node, *child; in s3c24xx_nand_probe_dt()
971 devtype_data = of_device_get_match_data(&pdev->dev); in s3c24xx_nand_probe_dt()
973 return -ENODEV; in s3c24xx_nand_probe_dt()
975 info->cpu_type = devtype_data->type; in s3c24xx_nand_probe_dt()
977 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); in s3c24xx_nand_probe_dt()
979 return -ENOMEM; in s3c24xx_nand_probe_dt()
981 pdev->dev.platform_data = pdata; in s3c24xx_nand_probe_dt()
983 pdata->nr_sets = of_get_child_count(np); in s3c24xx_nand_probe_dt()
984 if (!pdata->nr_sets) in s3c24xx_nand_probe_dt()
987 sets = devm_kcalloc(&pdev->dev, pdata->nr_sets, sizeof(*sets), in s3c24xx_nand_probe_dt()
990 return -ENOMEM; in s3c24xx_nand_probe_dt()
992 pdata->sets = sets; in s3c24xx_nand_probe_dt()
995 sets->name = (char *)child->name; in s3c24xx_nand_probe_dt()
996 sets->of_node = child; in s3c24xx_nand_probe_dt()
997 sets->nr_chips = 1; in s3c24xx_nand_probe_dt()
1011 info->cpu_type = platform_get_device_id(pdev)->driver_data; in s3c24xx_nand_probe_pdata()
1021 * nand layer to look for devices
1035 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); in s3c24xx_nand_probe()
1037 err = -ENOMEM; in s3c24xx_nand_probe()
1043 nand_controller_init(&info->controller); in s3c24xx_nand_probe()
1044 info->controller.ops = &s3c24xx_nand_controller_ops; in s3c24xx_nand_probe()
1048 info->clk = devm_clk_get(&pdev->dev, "nand"); in s3c24xx_nand_probe()
1049 if (IS_ERR(info->clk)) { in s3c24xx_nand_probe()
1050 dev_err(&pdev->dev, "failed to get clock\n"); in s3c24xx_nand_probe()
1051 err = -ENOENT; in s3c24xx_nand_probe()
1057 if (pdev->dev.of_node) in s3c24xx_nand_probe()
1070 res = pdev->resource; in s3c24xx_nand_probe()
1073 info->device = &pdev->dev; in s3c24xx_nand_probe()
1074 info->platform = plat; in s3c24xx_nand_probe()
1076 info->regs = devm_ioremap_resource(&pdev->dev, res); in s3c24xx_nand_probe()
1077 if (IS_ERR(info->regs)) { in s3c24xx_nand_probe()
1078 err = PTR_ERR(info->regs); in s3c24xx_nand_probe()
1082 dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs); in s3c24xx_nand_probe()
1084 if (!plat->sets || plat->nr_sets < 1) { in s3c24xx_nand_probe()
1085 err = -EINVAL; in s3c24xx_nand_probe()
1089 sets = plat->sets; in s3c24xx_nand_probe()
1090 nr_sets = plat->nr_sets; in s3c24xx_nand_probe()
1092 info->mtd_count = nr_sets; in s3c24xx_nand_probe()
1096 size = nr_sets * sizeof(*info->mtds); in s3c24xx_nand_probe()
1097 info->mtds = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); in s3c24xx_nand_probe()
1098 if (info->mtds == NULL) { in s3c24xx_nand_probe()
1099 err = -ENOMEM; in s3c24xx_nand_probe()
1105 nmtd = info->mtds; in s3c24xx_nand_probe()
1108 struct mtd_info *mtd = nand_to_mtd(&nmtd->chip); in s3c24xx_nand_probe()
1113 mtd->dev.parent = &pdev->dev; in s3c24xx_nand_probe()
1116 err = nand_scan(&nmtd->chip, sets ? sets->nr_chips : 1); in s3c24xx_nand_probe()
1129 dev_info(&pdev->dev, "clock idle support enabled\n"); in s3c24xx_nand_probe()
1139 err = -EINVAL; in s3c24xx_nand_probe()
1151 info->save_sel = readl(info->sel_reg); in s3c24xx_nand_suspend()
1158 writel(info->save_sel | info->sel_bit, info->sel_reg); in s3c24xx_nand_suspend()
1177 sel = readl(info->sel_reg); in s3c24xx_nand_resume()
1178 sel &= ~info->sel_bit; in s3c24xx_nand_resume()
1179 sel |= info->save_sel & info->sel_bit; in s3c24xx_nand_resume()
1180 writel(sel, info->sel_reg); in s3c24xx_nand_resume()
1197 .name = "s3c2410-nand",
1200 .name = "s3c2440-nand",
1203 .name = "s3c2412-nand",
1206 .name = "s3c6400-nand",
1221 .name = "s3c24xx-nand",
1230 MODULE_DESCRIPTION("S3C24XX MTD NAND driver");